201108906 、發明說明： 【發明所屬之技術領域】 本發明係關於一種採用LDI (雷射直接描繪）曝光機， 掃描雷射光束，將希望之圖案直接描繪於絕緣基板上的阻 絕層，而在絕緣基板上形成電路圖案的疊層基板之製造方 法。 【先前技術】 先前，採用掃描雷射光束而形成希望之電路圖案的雷 射直接描繪曝光機（以下，稱為LDI曝光機）之多層積板 等的疊層基板之製造方法，由於無須採用光遮罩，即可將 電路圖案直接描繪於絕緣基板上之阻絕層，因此在以多種 少量生產而製造之多層基板中，可減少成本與縮短交貨 期。此外，可光學性進行製造多層積板時之對準，而可正 確疊層。 例如，採用揭示於專利文獻1之LDI曝光機的描繪方 法，係使雷射光束偏向於主掃描方向，並且使放置於台上 之被描纟會體向副掃描方向移動’而在被描繪體之表面描繪 圖案，進一步將在被描繪體之背面形成有底之凹部作為標 記的凹部形成手段設於前述台者。藉此，不論感光材料之 種類為何，均可瞭解對準標記之位置，而可精確設定背面 側對表面側之位置。 【先前技術文獻】 【專利文獻】 201108906 【專利文獻1】日本特開2〇〇9_589〇5號公鈒 【發明内容】 <發明所欲解決之問題> 但是，由於先前採用LDI曝光機的疊層基板之製造方 法的情況，係在母次逐片堆疊絕緣基板時進行對準，並藉 由雷射光進行曝光，因此發生疊層誤差累積的問題。亦即 如第5A圖所示’在絕緣基板2之背面侧形成銅箔之電路圖 案的接端面部4’並在其絕緣基板2之表面側經由接著層之 黏合片7堆疊銅箔6而圖案化時，如第5A圖所示，接端面 部4之中心位置對連接表面與背面之電路的導通孔5之基 準位置P0，因絕緣基板2與黏合片7熱壓合成形時之收縮 而偏差P1。在此狀態下，於其次步驟中，以導通孔5位於 指定之基準位置PO的方式，藉由蝕刻或雷射光進行導通孔 5之開孔及導通孔5之電鑛8時，如第5B圖所示，可能背 面之接端面部4與導通孔5之電鍵8不連接。其後，即使 進行銅箔6之圖案化，仍然成為表面與背面之電路不連接 的瑕疵I品（第5C圖）。 因此’如第6A圖至第6D圖所示’在採用LDI曝光機 製造疊層基板中，亦進行配合絕緣基板2因熱壓合成形而 縮小，使導通孔5之中心位置移動至P1，再藉由餘刻或雷 射光實施導通孔5之開孔及在導通孔5中實施電鍍8 (第 6A圖及第6B圖）。 此時，雖然導通孔5或其他電路圖案對收縮之絕緣基 201108906 板2及其接端面部4不發生位置偏差的問題，但是在最初 發生大的位置偏差時，如此進行其次步驟（第6C圖），最 後將基準位置P0作為基準而進行防焊阻絕層9之塗布或與 其他構件之對準時，如第6D圖所示，與最外層之防焊阻絕 層9等不對準，而成為瑕疵品。 本發明係鑑於上述先前技術而構成者，其目的為提供 一種採用LDI曝光方式製造疊層基板時，可抑制因疊層造 成位置偏差之累積，而使製品之良率提高的疊層基板之製 造方法。 <解決問題之手段> 解決前述問題之手段如下。亦即， <1> 一種疊層基板之製造方法，係採用LDI曝光方 式在絕緣基板之表面形成電路圖案，並經由導通孔層間連 接位於前述絕緣基板之表面與背面的各接端面部， 且係在挾著前述絕緣基板，而形成與一方侧之接端面 部連接的導通孔及另一方側之接端面部時，對前述一方側 之接端面部與指定之基準位置的偏差量進行位置修正，使 前述另一方側之接端面部的位置移動於一方向，以減少與 前述一方侧之接端面部的前述偏差量，並藉由雷射光描繪 電路圖案，經由前述導通孔而層間連接前述一方側之接端 面部與前述另一方側之接端面部。201108906, invention description: [Technical Field] The present invention relates to a barrier layer using an LDI (Laser Direct Depiction) exposure machine that scans a laser beam and directly draws a desired pattern on an insulating substrate while insulating A method of manufacturing a laminated substrate on which a circuit pattern is formed on a substrate. [Prior Art] Previously, a method of manufacturing a laminated substrate using a multilayer direct plating plate of a laser direct drawing exposure machine (hereinafter referred to as an LDI exposure machine) for forming a desired circuit pattern by scanning a laser beam does not require light. The mask can directly trace the circuit pattern on the insulating substrate, so that the multilayer substrate manufactured in a plurality of small quantities can be reduced in cost and shortened delivery time. Further, the alignment at the time of manufacturing the multilayered board can be optically performed, and the lamination can be performed correctly. For example, according to the drawing method of the LDI exposure machine disclosed in Patent Document 1, the laser beam is biased in the main scanning direction, and the tracing body placed on the stage is moved in the sub-scanning direction. In the surface drawing pattern, a recess forming means for forming a recessed portion having a bottom on the back surface of the object to be drawn is provided on the table. Thereby, regardless of the type of the photosensitive material, the position of the alignment mark can be understood, and the position of the back side to the surface side can be accurately set. [PRIOR ART DOCUMENT] [Patent Document 1] 201108906 [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. 5, No. 5, No. 5, the disclosure of the present invention, the present invention, the problem to be solved by the invention, however, due to the previous use of the LDI exposure machine In the case of the method of manufacturing a laminated substrate, alignment is performed when the mother substrate is stacked one by one, and exposure is performed by laser light, so that the stacking error is accumulated. That is, as shown in FIG. 5A, the end face portion 4' of the circuit pattern of the copper foil is formed on the back side of the insulating substrate 2, and the copper foil 6 is stacked on the surface side of the insulating substrate 2 via the adhesive sheet 7 of the adhesive layer. When the film is formed, as shown in FIG. 5A, the center position of the terminal portion 4 is offset from the reference position P0 of the via hole 5 of the circuit connecting the surface and the back surface due to shrinkage of the insulating substrate 2 and the bonding sheet 7 during hot pressing. P1. In this state, in the second step, the opening of the via hole 5 and the electric ore of the via hole 5 are performed by etching or laser light in such a manner that the via hole 5 is located at the designated reference position PO, as shown in FIG. 5B. As shown, the contact face portion 4 of the back side may not be connected to the key 8 of the via hole 5. Thereafter, even if the copper foil 6 is patterned, it is a product which is not connected to the circuit on the front surface and the back surface (Fig. 5C). Therefore, as shown in FIGS. 6A to 6D, in the case of manufacturing a laminated substrate using an LDI exposure machine, the insulating substrate 2 is also shrunk due to the hot press forming, and the center position of the via 5 is moved to P1. The opening of the via hole 5 is performed by the residual or laser light and the plating 8 is performed in the via hole 5 (Figs. 6A and 6B). At this time, although the via hole 5 or other circuit pattern does not cause a positional deviation of the contracted insulating base 201108906 plate 2 and its terminal end face 4, when a large positional deviation initially occurs, the next step is performed (FIG. 6C). When the solder resist layer 9 is applied or the other components are aligned with the reference position P0 as a reference, as shown in FIG. 6D, the outermost solder resist layer 9 is not aligned, and the product is defective. . The present invention has been made in view of the above-described prior art, and an object thereof is to provide a laminate substrate which can suppress the accumulation of positional deviation due to lamination and improve the yield of a product when the laminated substrate is manufactured by the LDI exposure method. method. <Means for Solving the Problem> The means for solving the aforementioned problems are as follows. In the method of manufacturing a laminated substrate, a circuit pattern is formed on the surface of the insulating substrate by an LDI exposure method, and each of the contact surface portions on the front surface and the back surface of the insulating substrate is connected between the via holes. When the through-holes connected to the one end side surface portion and the other end-side end surface are formed next to the insulating substrate, positional correction is performed on the amount of deviation between the one end side end surface and the designated reference position And shifting the position of the other end side surface in one direction to reduce the amount of deviation from the one end side surface portion, and connecting the one side layer via the through hole by the laser light drawing circuit pattern The connecting end face of the side and the connecting end face of the other side.
<2>如前述<1>的疊層基板之製造方法，其+在表 面設有銅箔之前述絕緣基板上，藉由雷射光於指定位置形 成前述導通孔時，進行與前述位置修正同樣之前述位置修[S 201108906 正，其後，在前述導通孔内實施電鍍，並實施前述位置修 正，而藉由前述雷射光進行電路圖案之描繪。 <3>如前述<1>或<2>的疊層基板之製造方法， 其中前述絕緣基板係軟性基板。 <發明之效果> 按照本發明的疊層基板之製造方法，即使採用LDI曝 光方式製造豐層基板，仍可抑制因堆疊造成導通孔等之位 置偏差，而使製品之良率提咼。藉此可提高多種少量生產 時之疊層基板的製造效率，以抑制成本。 【實施方式】 以下，就本發明的疊層基板之製造方法的一種實施形 態，依據第1A圖至第4圖作說明。本實施形態之疊層基板 ίο係堆疊了複數層堆疊之聚醯亞胺等的軟性絕緣基板12 者，並在各層間採用LDI曝光方式而形成電路圖案及其電 路圖案之接端面部14。並挾著各絕緣基板12而在表面與背 面形成有連接電路圖案之各接端面部14的導通孔ι5。各層 之電路藉由導通孔15之電鍍18而層間連接，以尋求電性 連接。 該疊層基板10之製造方法如第2A圖所示，係在其背 面側形成有銅箔之電路圖案的接端面部14之絕緣基板12 的表面侧’經由接著層之黏合片17而堆疊銅箔16。此時， 背面側之接端面部14的位置對預定之各接端面部的位置之 基準位置P0,藉由絕緣基板12與黏合片π之熱壓合成形 201108906 時的收縮，接端面部14之中心位置偏差P1。該收縮藉由 習知之手段，在絕緣基板12之成形前後，可藉由讀取設於 絕緣基板12之檢測用的標記位置而瞭解。 因此，本實施形態中之採用LDI曝光方式的疊層基板 之製造方法，係逐漸修正位置偏差而進行電路圖案之描繪 者。首先，如第3圖所示，在藉由雷射光曝光之前，將修 正熱收縮造成之偏差的修正用伸縮率，例如在X軸方向設 定為<2，在Y轴方向設定為/3 (si)。進一步比較指定之臨 限值（s 2)。該臨限值例如係即使修正仍無法確實形成與接端 面部14之連接的大偏差量。其次，設定其絕緣基板12之 基準位置P0的座標（S3)。此時，依修正用伸縮率之位置修 正量=| P1 — P2 |係導通孔15之底部不致從接端面部14 脫落程度的量。此時，收縮位置=P1，修正位置=P2。之 後開始藉由雷射光曝光(S4)。 在藉由雷射光描繪電路圖案之前，對於其基板成形後 之收縮位置P1的測定值，就與基準位置P0之各座標的差 =| P0 —PI |與上述臨限值比較(s5)〇藉由該比較，於偏差 量為指定之臨限值，例如為即使修正仍無法確實形成與接 端面部14之連接的大偏差量時，即瞭解其為瑕疵基板。另 外，在臨限值以内時，則判斷與基準位置P0之各座標的差 =| P0 — P1丨是否在藉由預設之修正用伸縮率的修正量範 圍内（s6)。 與基準位置P0之各座標的差=I P〇 —P1 I係位置修 正量的範圍以内時，不進行修正，而依據基準位置P0藉由[s 201108906 雷射光描繪電路圖案，以形成電路圖案及導通孔15(s7)。 亦即，就預設之修正用伸縮率（α,万）以内的位置偏差，如 第4圖之點e所示，係進行將基準位置ΡΟ作為基準之描繪， 不進行伸縮之修正而實施曝光。這是因為此時收縮造成之 位置偏差量遠比接端面部14之半徑小，可確實藉由導通孔 15連接表面與背面之接端面部14。 另外，該差超出修正用伸縮率之修正量範圍時，係將 雷射光之描繪以在X軸方向乘上α程度之伸縮率，在Y轴 方向乘上>3程度之伸縮率的值修正位置而進行描繪(s7)。此 時如第4圖之點f，g所示，即使X軸方向或Y軸方向之一 方的偏差比修正用伸縮率大，只要藉由修正而修正至指定 臨限值以内，即可層間連接。再者，如點h所示，即使在 XY兩軸方向均有大的偏差，仍可藉由修正而到達可層間連 接之範圍，亦即藉由修正至臨限值之範圍内，如後述，在 疊層基板10中，可縮小最後之偏差量，而到達指定之容許 誤差的範圍内。 該狀態下，如第1A圖及第2C圖所示，成為藉由導通 孔15連接表面與背面之接端面部14,而確實尋求層間連接 之狀態。另外，如第2B圖及第2C圖所示，導通孔15之 形成、藉由雷射照射之曝光及形成外層之電路圖案後，因 這期間雷射照射及圖案化處理產生之熱的影響，絕緣基板 12產生收縮，因絕緣基板12之收縮而產生少許的位置偏 差。因此，首先在形成導通孔15時，設定對成形後之絕緣 基板12的上述修正用伸縮率，而藉由蝕刻或雷射加工進行 201108906 導通孔15之開孔。再者，就其導通孔15之位置，如— 圖所示，係設定上述修正用伸縮率，將收縮至修正俊$ 2C P3的位置作為基準，藉由阻絕層之塗布及銅箔l6置^ 路圖案之曝光及蝕刻。再者，如第2D圖所示，在進疒仃電 阻絕層19之塗布或與其他構件之對準時，如第订防埤 將基準位置P0作為基準予以圖案化即可。 所示，(2) The method of manufacturing a laminated substrate according to the above <1>, wherein the position correction is performed when the via hole is formed at a predetermined position by the laser light on the insulating substrate provided with the copper foil on the surface Similarly, the position is repaired [S 201108906], and thereafter, plating is performed in the via hole, and the position correction is performed, and the circuit pattern is drawn by the laser light. The method of manufacturing a laminated substrate according to the above <1> or <2>, wherein the insulating substrate is a flexible substrate. <Effect of the Invention> According to the method for producing a laminated substrate of the present invention, even if the layered substrate is produced by the LDI exposure method, the positional deviation of the via holes and the like due to the stack can be suppressed, and the yield of the product can be improved. Thereby, the manufacturing efficiency of the laminated substrate in a plurality of small-scale production can be improved to suppress the cost. [Embodiment] Hereinafter, an embodiment of a method for producing a laminated substrate of the present invention will be described with reference to Figs. 1A to 4 . In the laminated substrate of the present embodiment, the flexible insulating substrate 12 such as polyimine which is stacked in a plurality of layers is stacked, and the circuit pattern and the end surface portion 14 of the circuit pattern are formed by LDI exposure between the layers. The conductive holes 12 are formed on the front surface and the back surface with the via holes ι5 connecting the respective end surface portions 14 of the circuit pattern. The circuits of the respective layers are layer-by-layer connected by plating 18 of via holes 15 to seek electrical connection. As shown in FIG. 2A, the method of manufacturing the laminated substrate 10 is such that the surface side of the insulating substrate 12 on which the terminal surface portion 14 of the circuit pattern of the copper foil is formed on the back surface side is stacked via the adhesive sheet 17 of the adhesive layer. Foil 16. At this time, the reference position P0 of the position of the end face portion 14 on the back side to the predetermined position of each of the contact end faces is contracted by the heat pressing of the insulating substrate 12 and the bonding sheet π to form a shape 201108906, and the end face portion 14 is Center position deviation P1. This shrinkage can be understood by reading the position of the mark provided on the insulating substrate 12 before and after the formation of the insulating substrate 12 by conventional means. Therefore, in the method of manufacturing a laminated substrate using the LDI exposure method in the present embodiment, the pattern deviation is gradually corrected to trace the circuit pattern. First, as shown in Fig. 3, before the exposure by laser light, the correction expansion ratio for correcting the deviation due to thermal contraction is set to, for example, <2 in the X-axis direction and /3 in the Y-axis direction ( Si). Further compare the specified threshold (s 2). The threshold value is, for example, a large deviation amount that cannot be surely formed in connection with the joint face portion 14 even if it is corrected. Next, the coordinates of the reference position P0 of the insulating substrate 12 are set (S3). At this time, the position correction amount according to the correction expansion ratio =| P1 - P2 | is the amount by which the bottom of the via hole 15 does not fall off from the terminal end portion 14. At this time, the contraction position = P1 and the correction position = P2. Exposure by laser light is then initiated (S4). Before the circuit pattern is drawn by the laser light, the difference between the measured value of the contraction position P1 after the substrate is formed and the coordinate of the reference position P0 =| P0 —PI | is compared with the above threshold (s5). In this comparison, when the amount of deviation is a predetermined threshold value, for example, if a large amount of deviation from the connection with the terminal end portion 14 cannot be surely formed even if the correction is made, it is understood that it is a 瑕疵 substrate. Further, when it is within the threshold value, it is judged whether or not the difference from the coordinates of the reference position P0 =| P0 - P1 丨 is within the correction amount range by the preset correction expansion ratio (s6). When the difference between the coordinates of the reference position P0 = IP〇 - P1 I is within the range of the position correction amount, the correction is not performed, and the circuit pattern is drawn by the [s 201108906 laser light according to the reference position P0 to form a circuit pattern and conduct. Hole 15 (s7). In other words, as for the positional deviation within the predetermined correction expansion ratio (α, 10,000), as shown by the point e in FIG. 4, the reference position ΡΟ is used as a reference, and the exposure is performed without performing the correction of the expansion and contraction. . This is because the amount of positional deviation caused by the contraction at this time is much smaller than the radius of the end face portion 14, and the contact surface portion 14 between the front surface and the back surface can be surely connected by the via hole 15. In addition, when the difference exceeds the correction amount range of the correction expansion ratio, the projection of the laser light is multiplied by the expansion ratio of α in the X-axis direction, and the value of the expansion ratio of the degree of >3 is corrected in the Y-axis direction. The position is drawn (s7). At this time, as shown by the point f and g in FIG. 4, even if the deviation in one of the X-axis direction or the Y-axis direction is larger than the correction expansion ratio, it can be corrected within the specified threshold value by correction, and the interlayer connection can be performed. . Furthermore, as shown by the point h, even if there is a large deviation in the XY two-axis direction, the range of the inter-layer connection can be reached by correction, that is, by being corrected to the range of the threshold, as will be described later. In the laminated substrate 10, the final amount of deviation can be reduced to reach the range of the specified tolerance. In this state, as shown in Figs. 1A and 2C, the contact surface portions 14 of the front surface and the back surface are connected by the via holes 15, and the interlayer connection is surely sought. Further, as shown in FIGS. 2B and 2C, the formation of the via hole 15, the exposure by the laser irradiation, and the formation of the circuit pattern of the outer layer are affected by the heat generated by the laser irradiation and the patterning process during this period. The insulating substrate 12 is shrunk, and a slight positional deviation occurs due to shrinkage of the insulating substrate 12. Therefore, first, when the via hole 15 is formed, the above-described correction expansion ratio of the insulating substrate 12 after molding is set, and the opening of the 201108906 via hole 15 is performed by etching or laser processing. Further, as for the position of the via hole 15, as shown in the figure, the above-described correction expansion ratio is set, and the position of the shrinkage to the corrected volume $2C P3 is used as a reference, and the coating of the barrier layer and the copper foil 16 are set. Exposure and etching of road patterns. Further, as shown in Fig. 2D, when the coating of the barrier layer 19 or the alignment with other members is performed, the predetermined position can be patterned by using the reference position P0 as a reference. As shown,
如此，在複數個步驟中，於絕緣基板12產生收 藉由在疊層步驟的適宜階段適用考慮了收縮率之修雉時， 縮率，可將最後之電路圖案的位置偏差抑制在最=正用伸 此外，即使疊層基板10因複數次反覆而如第1A圖度。 圖所示，第1層之絕緣基板12a的收縮量=位置偽差㈢第 P0-P1 |大’例如就最後之表層的電路圖案， 里I 八 ^出用於推 行焊接等之位置的容許誤差，仍可反覆實施上述之佟正 藉由指定之修正用伸縮率（α，々）進行修正，使第2層=絕 緣基板12b的位置接近基準位置P0，並藉由在其次 層的絕緣基板12c之疊層中亦進行上述之修正，而逐漸接 近基準位置P0，最後可縮小至容許誤差的範圍内。 本實施形態的疊層基板之製造方法，在採用Lm曝光 方式製造多種少量生產之疊層基板時，即使因纟邑緣基板 之收縮而在各層間發生導通孔15與接端面部ι4之位置偏 差’仍可確實進行層間連接’並可將最後之電路圖案的各 部之位置偏差縮小至容許誤差的範圍内。藉此，疊層基板 10之製造良率提南’生產效率提南，亦有助於減少成本。 另外’本發明的疊層基板之製造方法可適宜設定絕緣 201108906 基板之修正用伸縮率，且可依其絕緣基板之疊層樹、熱膨 脹係數、收縮率及厚度等而適宜設定。此外，適用之絕緣 基板除了適合聚醯亞胺等軟性基板之外，亦可適用於剛性 基板。 【圖式簡單說明】 第1A圖係顯示本發明一種實施形態之疊層基板的製 造步驟之一部分的概略剖面圖（之一）。 第1B圖係顯示本發明一種實施形態之疊層基板的製 造步驟之一部分的概略剖面圖（之二）。 第1C圖係顯示本發明一種實施形態之疊層基板的製 造步驟之一部分的概略剖面圖（之三）。 第2A圖係顯示本發明一種實施形態之疊層基板的疊 層步驟之一部分的概略剖面圖（之一）。 第2B圖係顯示本發明一種實施形態之疊層基板的疊 層步驟之一部分的概略剖面圖（之二）。 第2C圖係顯示本發明一種實施形態之疊層基板的疊 層步驟之一部分的概略剖面圖（之三）。 第2D圖係顯示本發明一種實施形態之疊層基板的疊 層步驟之一部分的概略剖面圖（之四）。 第3圖係本發明一種實施形態之疊層基板的疊層步驟 之流程圖。 第4圖係顯示本發明一種實施形態之疊層基板的對準 之概念圖。 201108906 第5A圖係顯示先前之疊層基板的疊層步驟之一部分 的概略剖面圖（之一）。 第5B圖係顯示先前之疊層基板的疊層步驟之一部分 的概略剖面圖（之二）。 第5C圖係顯示先前之疊層基板的疊層步驟之一部分 的概略剖面圖（之三）。 第6A圖係顯示先前之疊層基板藉由自動對準的疊層 步驟之一部分的概略剖面圖（之一）。 第6B圖係顯示先前之疊層基板藉由自動對準的疊層 步驟之一部分的概略剖面圖（之二）。 第6C圖係顯示先前之疊層基板藉由自動對準的疊層 步驟之一部分的概略剖面圖（之三）。 第6D圖係顯示先前之疊層基板藉由自動對準的疊層 步驟之一部分的概略剖面圖（之四）。 【主要元件符號說明】 2 絕緣基板 4 接端面部 5 導通孔 6 銅羯 7 黏合片 8 電鍍 9 防焊阻絕層 10 疊層基板 11 201108906 12, 12a,12b,12c 絕緣基板 14 接端面部 15 導通孔 16 銅落 17 黏合片 18 電鍍 19 防焊阻絕層 P0 基準位置 PI 收縮位置 P2 修正位置 a , β 修正用伸縮率 P3 修正位置 e, f, g, h 點 12In this way, in a plurality of steps, the insulating substrate 12 is generated and received by the shrinkage rate in consideration of the shrinkage rate at the appropriate stage of the laminating step, and the positional deviation of the last circuit pattern can be suppressed to the most = positive In addition, even if the laminated substrate 10 is repeated as many times as in the first AA pattern. As shown in the figure, the amount of shrinkage of the insulating substrate 12a of the first layer = positional artifact (3) P0-P1 | large ', for example, the circuit pattern of the last surface layer, the tolerance of the position for pushing the solder, etc. The above-described correction can be performed by the specified correction expansion ratio (α, 々) so that the position of the second layer = the insulating substrate 12b is close to the reference position P0, and by the insulating substrate 12c of the second layer The above-mentioned correction is also performed in the stack, and gradually approaches the reference position P0, and finally can be reduced to within the allowable error range. In the method for producing a laminated substrate of the present embodiment, when a plurality of laminated substrates produced in a small amount are produced by the Lm exposure method, the positional deviation between the via holes 15 and the contact face portion ι4 occurs between the respective layers even due to the shrinkage of the flange substrate. 'The interlayer connection can still be made sure' and the positional deviation of each part of the last circuit pattern can be reduced to the tolerance. Thereby, the manufacturing yield of the laminated substrate 10 is increased, and the production efficiency is also increased, which also contributes to cost reduction. Further, the method for producing a laminated substrate of the present invention can be suitably set so as to adjust the expansion ratio of the insulating substrate of the 201108906 substrate, and can be appropriately set depending on the laminated tree of the insulating substrate, the coefficient of thermal expansion, the shrinkage ratio, and the thickness. Further, the applicable insulating substrate can be applied to a rigid substrate in addition to a flexible substrate such as polyimide. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic cross-sectional view (part 1) showing a part of a manufacturing process of a laminated substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view (part 2) showing a part of a manufacturing process of a laminated substrate according to an embodiment of the present invention. Fig. 1C is a schematic cross-sectional view (part 3) showing a part of a manufacturing process of a laminated substrate according to an embodiment of the present invention. Fig. 2A is a schematic cross-sectional view (part 1) showing a part of a lamination step of a laminated substrate according to an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view (part 2) showing a part of the lamination step of the laminated substrate of one embodiment of the present invention. Fig. 2C is a schematic cross-sectional view (part 3) showing a part of the lamination step of the laminated substrate of one embodiment of the present invention. Fig. 2D is a schematic cross-sectional view (part 4) showing a part of the lamination step of the laminated substrate of one embodiment of the present invention. Fig. 3 is a flow chart showing the lamination step of the laminated substrate of one embodiment of the present invention. Fig. 4 is a conceptual view showing the alignment of a laminated substrate according to an embodiment of the present invention. 201108906 Fig. 5A is a schematic cross-sectional view (part 1) showing a part of the lamination step of the prior laminated substrate. Fig. 5B is a schematic cross-sectional view (part 2) showing a part of the lamination step of the prior laminated substrate. Fig. 5C is a schematic cross-sectional view (part 3) showing a part of the lamination step of the prior laminated substrate. Fig. 6A is a schematic cross-sectional view (part 1) showing a portion of the lamination step of the prior laminated substrate by self-alignment. Fig. 6B is a schematic cross-sectional view (part 2) showing a portion of the lamination step of the prior laminated substrate by self-alignment. Fig. 6C is a schematic cross-sectional view (part 3) showing a portion of the lamination step of the prior laminated substrate by self-alignment. Fig. 6D is a schematic cross-sectional view (fourth) showing a portion of the lamination step of the previous laminated substrate by self-alignment. [Main component symbol description] 2 Insulating substrate 4 Terminal surface 5 Via hole 6 Copper crucible 7 Adhesive sheet 8 Plating 9 Solder resist layer 10 Laminated substrate 11 201108906 12, 12a, 12b, 12c Insulating substrate 14 Connecting end face 15 Conduction Hole 16 Copper drop 17 Adhesive sheet 18 Plating 19 Solder resist layer P0 Reference position PI Shrink position P2 Correct position a , β Correction expansion ratio P3 Correct position e, f, g, h Point 12