201039701 · 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係關於一種多重負載拓撲架構。 [先前技術] [00〇2] 電子技術的發展使得1C (積體電路）的工作速度愈來愈 快，工作頻率愈來愈高，其上設計的負載即晶片數也愈 來愈多’於是設計者在設計時經常需要將一個訊號控制 端連接至兩個甚至多個晶片’用於為該等晶片提供訊號 〇 [〇〇〇3]請參照圖1，其為習知技術中多重負載拓撲架構圖，其中 包含有一訊號控制端1〇及六個接收端2〇、3〇、4〇、5〇、 60、70 ’其中該訊號控制端1〇與該等接收端2〇、3〇、4〇 ' 50、60 ' 70之間採用菊花鏈拓撲架構相連接該等接 收端20、30、40、5〇、60、70可以為各種晶片。201039701 · VI. Description of the invention: [Technical field to which the invention pertains] [0001] The present invention relates to a multiple load topology architecture. [Prior Art] [00〇2] The development of electronic technology has made 1C (integrated circuit) work faster and faster, and the operating frequency is getting higher and higher, and the load on the design is more and more. Designers often need to connect a signal control terminal to two or more chips during design to provide signals for the chips. [〇〇〇3] Please refer to Figure 1, which is a multi-load topology in the prior art. The architecture diagram includes a signal control terminal 1〇 and six receiving terminals 2〇, 3〇, 4〇, 5〇, 60, 70′, wherein the signal control terminal 1〇 and the receiving terminals 2〇, 3〇, 4接收' 50, 60' 70 are connected by a daisy chain topology. The receiving ends 20, 30, 40, 5, 60, 70 may be various types of wafers.
LU0U4J 〇 [0005] 098113130 在此架構中，驅動訊號是從峨_端1崎出沿傳輸線 在傳輸過程中要分流至各個接收額、⑽ 、70 ’只要傳輸路徑不連續即會造成阻抗不匹配，驅動 訊號沿傳輸㈣傳輸時如阻抗#配就會產生大小不 -二彈訊號’各種雜亂的反彈訊號叠加於各個接收端 20、30、40、50、60、7n ㈣單調，核編大或過小，甚至訊號完整性，更嚴重料㈣）現象發生，從而影響了 f導致時序與數位運算發生錯誤。 =繼續參照圖2,其為對則中六個接收糊、3〇、40、 50、60、70所接收的沖妹、表單編號A0101 D娓進行仿真驗證的波形圖，圖中 第3頁/共12頁 0982021946- 201039701 % [0006] [0007] [0008] [0009] 098113130 的六條訊號曲線分別對應為該接收端20、3〇、4〇、50、 6〇、70的訊號仿真曲線，從圖中我們可以看出，有部分 訊號仿真曲線在9〇ns-1 〇0ns時間段内產生了嚴重的非單 調現象，其有可能會影響訊號的完整性，更有可能導致 時序和數位運算錯誤。另外，正常的操作電壓範圍為 0-3. 3V，但由於阻抗不匹配所造成的反彈電壓疊加到各 個接收端使操作電壓範圍變為-0.8-4V，長期使用可能會 造成晶片損壞。 【發明内容】 鑒於以上内容’有必要提供—種多重負載㈣架構用 於減弱因阻抗不匹配而！丨起的反彈訊號及接收端所接收 Λ號的非單調現象’以提升系統工作的穩定性。 。種多重貞撲架構’包括一用於發送ϋ動訊號的訊 號控制端、複數接收該驅動訊號的接收端及複數傳輸線 該I號控制端透過該等傳輸線依次連接該等接收端， 該Λ號控制端與其相鄰的接收端之間的傳輸線的寬度及 距離訊號㈣端最遠的兩相#接收端之間的傳輸線的 寬度大於其他部分傳輪線的寬度。 上述多負载托撲架中’透過將該接收端的頭尾兩段傳輸 線的寬度加寬’可使該兩段傳輸線上的阻抗值最小，從 而使因阻抗不匹配而引起的反彈訊號大大減弱，提高了 系統工作的穩定性。【實施方式】 請參照圖3 ’本發明多重負載拓撲架構較佳實施方式包括 一说號控制端⑽、六個接收端2GG、3GG、4GG、500、 表單編號A0101 第 4 頁/共 12 頁 0982021946-0 201039701 600、700、兩電阻RSI、RS2及複數傳輸線，其中該訊號 控制端100與該等接收端2〇〇、300、400、500、600、 700之間採用菊花鏈拓撲方式相連接，該訊號控制端1〇〇 透過該等傳輸線依次連接該等接收端200、300、400、 •500、600、700。 [0010] 該訊號控制端100與該等接收端200、300、400、500、 600、700之間的傳輸線中，位於頭尾兩部分的傳輸線， Ο 即該訊號控制端100與該接收端200之間的傳輸線以及該 接收端600與該接收端700之間的傳輸線設置為加寬的傳 輸線，即該訊號控制端100與該接收端200之間的傳輸線 以及該接收端600與該接收端700之間的傳輸線的寬度大 於其他部分傳輸線的寬度。由於頭尾兩部分的傳輸線被 加寬，故此兩部分傳輸線上的阻抗值最小，從而可使因 阻抗不匹配而引起的反彈訊號減弱，提高了系統工作的 穩定性。 ：；；；： .:；^ [0011] ο 該電阻RS1設置於接收端300與400之間的傳輸線上，該 電阻RS2設置於接收端400與500之間的傳輸線上。本實 施方式中，該接收端300與400所接收的訊號容易產生非 單調現象，故將他們的後端連接該兩電阻RS1及RS2 ’透 過連接該兩電阻RS1及RS2可減弱該接收端300與400所接 收的訊號的非單調現象，此處可設定該兩電阻以丨及1^2 的電阻值均為47歐姆。其他實施方式中，可在實際會產 生非單調現象的接收端後連接相應的電阻’不局限於本 實施方式中設置在該兩個接收端300與400之後，如果每 個接收端均不會產生非單調現象則不需設置電阻’如果 098113130 表單編號A0101 第5頁/共12頁 0982021946-0 201039701 設置電阻的咭， ° 对於電阻值的確定可透過多次試驗得出 最佳值。 [0012] [0013] [0014] 上述菊化鏈拓撲架構中，還可將傳輸線頭尾兩個位置設 置為最重要的元件（如功能晶片），即設置該兩接收端 及7〇〇為最重要的元件’中間位置設置相對不重要的 凡件（如測試用元件或接頭式元件等），由於頭尾兩個 位置的訊號干擾較其他位置的訊號干擾相對要弱，故將 最重要的兀件設置在頭尾兩個位置可提高系統的穩定性 。如果該等接收端200、300、400、500、600、700的 〇 元件同樣重要的話，各元件的擺放位置可任意設置。 清繼續參照圖4，其為對圖3中六嗰接收端2〇〇、300、 仙〇、500、600、7〇〇所接收的訊號進行仿真驗證的波形 圖，圖中的六條訊號曲線分別對應為該接收端2〇〇、3〇〇 、400、500、600、700的訊號仿真曲線，從圖中我們可 以看出，所有訊號仿真曲線的非單調現象均以基本消除 ，並且電壓範圍也基本介於.主.常的操作.電壓範圍（ 0·"3. 3V)之間，故該系統工作的穩定性得到了大大的提 I》 高。 综上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟’以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化’皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係習知多重負載拓撲架構示意圖。 098113130 表單編號A0101 第6頁/共12頁 0982021946-0 [0015] 201039701 [0016] 圖2係對圖1中多負載所接收的訊號進行仿真驗證的波形 圖。 [0017] 圖3係本發明多重負載拓撲架構較佳實施方式的架構示意 圖。 [0018] 圖4係對圖3中多負載所接收的訊號進行仿真驗證的波形 圖。 【主要元件符號說明】 訊號控制端 100 電阻 RSI 、 RS2 接收端 200、300、400、500、600 ' 700 [0019] 〇 〇 098113130 表單編號A0101 第7頁/共12頁 0982021946-0LU0U4J 〇[0005] 098113130 In this architecture, the drive signal is shunted from the 峨_terminal 1 out of the transmission line to each receiving amount during transmission, (10), 70 ' as long as the transmission path is discontinuous, it will cause impedance mismatch, When the drive signal is transmitted along the transmission (4), if the impedance is matched, the size will not be generated. - The second alarm signal is generated. The various random rebound signals are superimposed on each of the receiving ends 20, 30, 40, 50, 60, 7n (4) Monotonous, and the core is large or too small. Even the signal integrity, more serious (4)) phenomenon occurs, which affects the error caused by timing and digital operations. Continue to refer to FIG. 2, which is a waveform diagram of simulation verification of the received sample, the form number A0101 D娓 of the six receiving pastes, 3〇, 40, 50, 60, 70, and the third page in the figure/ A total of 12 pages 0982021946-201039701% [0006] [0007] [0008] [0009] The six signal curves of 098113130 correspond to the signal simulation curves of the receiving end 20, 3〇, 4〇, 50, 6〇, 70, respectively. As can be seen from the figure, some of the signal simulation curves have a serious non-monotonic phenomenon in the 9〇ns-1 〇0ns period, which may affect the integrity of the signal and is more likely to cause timing and digital operations. error. In addition, the normal operating voltage range is 0-3. 3V, but the buckling voltage due to the impedance mismatch is superimposed on each receiving end to make the operating voltage range become -0.8-4V, which may cause wafer damage for long-term use. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a multi-load (four) architecture for reducing impedance mismatch! The rebound signal and the non-monotonic phenomenon of the nickname received by the receiver are used to improve the stability of the system. . The multi-ply architecture includes a signal control terminal for transmitting a sway signal, a plurality of receiving ends for receiving the driving signal, and a plurality of transmission lines. The control terminal No. 1 sequentially connects the receiving terminals through the transmission lines, and the nickname control The width of the transmission line between the end and the adjacent receiving end and the width of the transmission line between the two receiving ends of the farthest distance from the signal (4) end are greater than the width of the other partial transmitting lines. In the multi-load tray, the width of the two transmission lines can be minimized by widening the width of the two transmission lines at the receiving end, so that the rebound signal caused by the impedance mismatch is greatly weakened and improved. The stability of the system work. [Embodiment] Please refer to FIG. 3 'The preferred embodiment of the multi-load topology architecture of the present invention includes a header control terminal (10), six receiving terminals 2GG, 3GG, 4GG, 500, form number A0101, page 4/12 pages, 0982021946 -0 201039701 600, 700, two resistors RSI, RS2 and a plurality of transmission lines, wherein the signal control terminal 100 is connected to the receiving terminals 2, 300, 400, 500, 600, 700 by a daisy chain topology. The signal control terminal 1 is sequentially connected to the receiving terminals 200, 300, 400, 500, 600, 700 through the transmission lines. [0010] Among the transmission lines between the signal control terminal 100 and the receiving terminals 200, 300, 400, 500, 600, 700, the transmission lines at the head and the tail, that is, the signal control terminal 100 and the receiving terminal 200 The transmission line between the transmission line and the transmission line between the receiving end 600 and the receiving end 700 is set as a widened transmission line, that is, the transmission line between the signal control terminal 100 and the receiving end 200, and the receiving end 600 and the receiving end 700. The width of the transmission line between is greater than the width of the other part of the transmission line. Since the transmission lines of the two parts are widened, the impedance values of the two parts of the transmission line are the smallest, so that the rebound signal caused by the impedance mismatch is weakened, and the stability of the system operation is improved. [0011] ο The resistor RS1 is disposed on a transmission line between the receiving terminals 300 and 400, and the resistor RS2 is disposed on a transmission line between the receiving terminals 400 and 500. In this embodiment, the signals received by the receiving ends 300 and 400 are prone to non-monotonic phenomenon, so that the back ends of the two resistors RS1 and RS2 are connected to the two resistors RS1 and RS2 to weaken the receiving end 300 and The non-monotonic phenomenon of the received signals of 400, here the two resistors can be set to 47 and the resistance value of 1^2 is 47 ohms. In other embodiments, the corresponding resistors may be connected after the receiving end that actually generates the non-monotonic phenomenon' is not limited to being disposed after the two receiving ends 300 and 400 in the embodiment, if each receiving end does not generate Non-monotonic phenomenon does not need to set the resistor 'If 098113130 Form No. A0101 Page 5 / Total 12 Page 0982021946-0 201039701 Set the resistance of the 咭, ° For the determination of the resistance value can be obtained through multiple tests to get the best value. [0014] [0014] In the above-described daisy chain topology, the two positions of the transmission line head and tail can also be set as the most important components (such as a functional chip), that is, the two receiving ends and 7 〇〇 are the most Important components 'In the middle position, the relatively unimportant parts (such as test components or joint components), because the signal interference between the two positions at the head and the tail is relatively weaker than the signal interference at other positions, the most important one is The two positions in the head and tail can improve the stability of the system. If the 〇 elements of the receiving ends 200, 300, 400, 500, 600, 700 are equally important, the placement positions of the respective elements can be arbitrarily set. With continued reference to FIG. 4, which is a waveform diagram for simulating the signals received by the six-channel receiving terminals 2〇〇, 300, 仙, 500, 600, and 7〇〇 in FIG. 3, the six signal curves in the figure. Corresponding to the signal simulation curves of the receiving terminals 2〇〇, 3〇〇, 400, 500, 600, 700, we can see from the figure that the non-monotonic phenomenon of all signal simulation curves is basically eliminated, and the voltage range It is also basically between the main and normal operation. The voltage range (0·"3. 3V), so the stability of the system work has been greatly improved. In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a conventional multi-load topology architecture. 098113130 Form No. A0101 Page 6/Total 12 Page 0982021946-0 [0015] FIG. 2 is a waveform diagram for performing simulation verification on the signals received by the multiple loads in FIG. 3 is a schematic architectural diagram of a preferred embodiment of a multiple load topology architecture of the present invention. 4 is a waveform diagram of simulation verification of signals received by multiple loads in FIG. 3. [Main component symbol description] Signal control terminal 100 Resistor RSI, RS2 Receiver 200, 300, 400, 500, 600 ' 700 [0019] 〇 098 098113130 Form No. A0101 Page 7 of 12 0982021946-0