1299245 九、發明說明·· 【發明所屬之技術領域】 ' 本發明涉及一種高速印刷電路板中傳輪線之佈線架 ， 構尤係一種用於南速印刷電路板上北橋晶片與pc'j (Peripheral Component Interconnect，週邊零件連接介面） / 插槽間用來提高訊號傳輸品質之高速印刷電路板中之傳 . 輸線佈線架構。. 【先前技彳衧】 ，電子技術之發展使得1C (積體電路）之工作速度越來 I# 越快，工作頻率越來越高，通常認爲、如果數位邏輯電路之 頻率達到或者超過45MHz〜50MHz，而且工作在這個頻率 之上之電路已經占到了整個電子系統一定之份量（比如說 1/3 )，該電路就稱爲高速電路。1996年之後，高速設計在 : 整個電子設計領域所占之比例越來越大，1〇〇MHz以上之 ， 系統已隨處可見，Bare Die (裸晶片），BGA(球格陣列）， MCM (多晶片組件）這些體積小、引腳數已達數百甚至上 千之封裝形式也已越來越多地應用到各類高速超高速電 子系統中。實際上，訊號邊緣之諧波頻率比訊號本身之頻 率高，係訊號快速變化之上升緣與下降緣（或稱訊號之跳 、變）引發之訊號傳輸之非預期結果。因此，通常約定如果 線傳播延時大於1/2數位訊號驅動端訊號之上升時間，則 忍爲此類訊號是高速訊號並産生傳輸線效應，即連線不再 是顯示集總參數之單純之導線，而是呈現出分佈之參數效 ·' 應，在此情况下，只有透過使用高速電路設計知識，才能 - 實現設計過程之可控性，否則基於傳統方法設計之印刷電 路板將無法工作。 隨著半導體工藝之發展，高速設計已成爲現代電子産 品設計之中一個重要環節，與傳統之設計比較，高速設計 要更多地考慮到訊號完整性問題，其主要表現在過沖 6 1299245 (overshoot)、下沖（undersh〇〇t)、振鈴（ringing)、延遲 (delay)、串擾（crosstalk)和反射（reflecti〇n)等方面。 ' 一般在電路之設計過程中是透過嚴格控制走線長度並合 \ 理規劃走線之拓樸結構來避免或降低傳輸線效應。 _ 北橋晶片是主機板晶片組中起主導作用之最重要組 成部分，負責與CPU之聯繫並控制記憶體、AGP、PCI資 • 料在北橋内部傳輸，提供對CPU之類型和主頻、系統之1299245 IX. OBJECT DESCRIPTION OF THE INVENTION · TECHNICAL FIELD OF THE INVENTION The present invention relates to a wiring frame for a transmission line in a high-speed printed circuit board, and is particularly useful for a north bridge wafer and a pc'j (for a south speed printed circuit board) Peripheral Component Interconnect, the transmission interface in the high-speed printed circuit board used to improve the signal transmission quality between the slots. [Previous technology] The development of electronic technology makes the working speed of 1C (integrated circuit) become faster and the working frequency is higher and higher. It is generally considered that if the frequency of the digital logic circuit reaches or exceeds 45MHz. ~50MHz, and the circuit working above this frequency has already accounted for a certain amount of the entire electronic system (such as 1/3), the circuit is called high-speed circuit. After 1996, high-speed design in: The proportion of the entire electronic design field is growing, more than 1 〇〇MHz, the system has been everywhere, Bare Die (bare die), BGA (ball grid array), MCM (multiple Wafer components) These small form factor packages with hundreds or even thousands of pins are increasingly being used in a variety of high speed ultra high speed electronic systems. In fact, the harmonic frequency of the edge of the signal is higher than the frequency of the signal itself, which is the unintended result of the signal transmission caused by the rising edge and the falling edge of the signal (or the jump or change of the signal). Therefore, it is generally agreed that if the line propagation delay is greater than the rise time of the 1/2 digit signal driver signal, then the signal is forcibly a high speed signal and produces a transmission line effect, that is, the connection is no longer a simple conductor for displaying the lumped parameter. Rather, it presents the parameter effect of the distribution. In this case, only through the use of high-speed circuit design knowledge can the controllability of the design process be realized, otherwise the printed circuit board based on the traditional method will not work. With the development of semiconductor technology, high-speed design has become an important part of modern electronic product design. Compared with traditional design, high-speed design should consider signal integrity more, mainly in overshoot 6 1299245 (overshoot ), undersh〇〇t, ringing, delay, crosstalk, and reflecti〇n. 'In general, in the design process of the circuit, the transmission line effect is avoided or reduced by strictly controlling the length of the trace and the topology of the planned trace. _ Northbridge chip is the most important component of the main board chipset. It is responsible for the connection with the CPU and controls the memory, AGP, and PCI resources to be transmitted inside the North Bridge. It provides the type and frequency of the CPU and the system.
前端匯流排頻率、記憶體之類型和最大容量、pCI /AGp 插槽、ECC ( Error Checking and Correcting，錯誤檢查和 黪鲁 糾正）糾錯等支援。由於電腦匯流排、帶寬之增加，對訊號 傳輸速率之要求逐漸增高，傳統之32位元33MHz之PCI (Peripheral Component Interconnect)插槽已經發展到 64Support for front-end bus frequency, memory type and maximum capacity, pCI /AGp slot, ECC (Error Checking and Correcting) error correction. Due to the increase in computer bus and bandwidth, the requirements for signal transmission rate have gradually increased. The traditional 32-bit 33MHz PCI (Peripheral Component Interconnect) slot has been developed to 64.
位元133MHz之PCI-X插槽。請參考第一圖，係習知之菊 、 花鏈（Daisy Chain)型拓樸佈線架構之北橋晶片與PCI_X ' 插槽互連之示意圖’北橋晶片10透過一主傳輸線16連接 PCI-X插槽12、13及14，所述北橋晶片10、PCI-X插槽 12、13、14分別經由一終端電阻Rl〇、R12、R13、R14 與所述主傳輸線16連接，所述終端電阻RIO、R12、R13、 R14阻值分別與其相連之分支傳輸線（圖未標）之特徵阻 •• 抗相匹配。其中，由於驅動訊號是從北橋晶片1Q出發沿 所述主傳輸線丨6依次到達各PCI-X插槽12、13及14,即 從所述北橋晶片10出發之訊號到達各PCI-X插槽所經過 之線長會有所不同，而高速印刷電路板上訊號每經過一段 距離之傳輸線就會存在一定時間之延遲，因此使得各 pCI-X插槽上之訊號不同步；同時，由於採用菊花鏈佈線 架構，每條分支傳輸線與主傳輸線之間會形成一個T型 結’使得傳輸線不連續，訊號會在此來回反射，即使在每 個分支傳輸線占串接一終端電阻也不可能使每個分支之 透射係數都十分理想。因此，參考第二圖，我們可以看到 7 1299245 ΞΪί IT” 12、13、14 之訊號曲線 122、132 ' M2 ，振鈐、過沖縣嚴重，且各訊號 【發明内容】 鑒於以上内容，有必要提供一種能 ::^邊零件連接介面插槽間訊號之振鈴盥 ‘ 之向速印巧電路板中傳輸線之佈線架構。中象 .·Bit 133MHz PCI-X slot. Please refer to the first figure, which is a schematic diagram of the North Bridge chip and the PCI_X 'slot interconnection of the Daisy Chain type topology structure. The north bridge chip 10 is connected to the PCI-X slot 12 through a main transmission line 16. 13 and 14, the north bridge chip 10, the PCI-X slots 12, 13, 14 are respectively connected to the main transmission line 16 via a terminating resistor R1, R12, R13, R14, and the terminal resistors RIO, R12, The resistance values of R13 and R14 are matched with the characteristic resistance of the branch transmission line (not shown) connected to it. Wherein, since the driving signal is from the north bridge chip 1Q to the PCI-X slots 12, 13 and 14 along the main transmission line 依次6, the signal from the north bridge wafer 10 reaches each PCI-X slot. The length of the line will be different, and there will be a delay in the transmission line of the signal on the high-speed printed circuit board every time, so the signals on the pCI-X slots are not synchronized; at the same time, due to the daisy chain Wiring architecture, a T-junction is formed between each branch transmission line and the main transmission line. The transmission line is discontinuous, and the signal will be reflected back and forth. Even if each branch transmission line occupies a series of termination resistors, it is impossible to make each branch. The transmission coefficient is very good. Therefore, referring to the second figure, we can see the signal curve 122, 132 ' M2 of 7 1299245 ΞΪ IT IT IT 12, 13, 14 , vibrating, overcrowding county is serious, and each signal [invention content] It is necessary to provide a wiring structure for the transmission line in the speed-sensitive printed circuit board that can be connected to the interface between the slots of the interface.
樸芊槿ί:ΐ印路板中傳輸線之佈線架構，將星型拓 ί: f器與複數接收器之連接上，該驅動器 數八φ值&接至一連接點，該連接點再分別經由複 i刀複數接收11，該、主傳輸線上串接一電 傳輸接收器之間可透過該主傳輸線與分支 右所優點在於：本發明採用—種星型拓樸架構並 輸線上串接—阻尼電阻，藉此可以使該連接點 2訊號透射率提高，訊號不會在該連接點處來回反射， 口^的消除或降低了振鈴與過沖等現象，提高了訊號傳輸 口口貝 〇 【實施方式】 。請參閱第三圖，本發明高速印刷電路板中傳輸線之佈 線，構，f採用星型拓樸架構，在一印刷電路板中，一驅 動器，本實施例中該驅動器為一北橋晶片20,該北橋晶片 20經由一主傳輸線28連接至一連接點a，該連接點A分 由分支傳輸線222、242、262連接至複數接收器，本 貫施例中該等接收器為複數PCI_X插槽22、24、26。在該 主傳輸線28上靠近該北橋晶片2〇之一端（<800mil)串 接一阻尼電阻R，該阻尼電阻r之阻值應與主傳輸線28 之特徵阻抗相匹配，在本發明之具體實施例中該主傳輸線 28之特徵阻抗值約爲56歐姆，而北橋晶片20内阻約爲 24歐姆，因而該阻尼電阻r可爲33歐姆。理論上而言， 8 1299245 敢仏之佈線方式係该等分支傳輪線222、242及262之長 度完全相等，但考慮實際之佈線要求，要保留部分設計餘 ^ 裕，故該等分支傳輸線之長度允許有一定之差距，但所述Park 芊槿ί: The wiring structure of the transmission line in the stencil board, the connection between the star topology and the complex receiver, the number of octels of the driver is connected to a connection point, and the connection point is respectively Receiving 11 through the complex i-knife, the main transmission line is connected in series with an electrical transmission receiver. The advantage of the main transmission line and the branch right is that the present invention adopts a star topology and is connected in series on the transmission line. Damping resistor, which can increase the signal transmittance of the connection point 2, the signal will not reflect back and forth at the connection point, the mouth ^ eliminates or reduces the phenomenon of ringing and overshoot, and improves the signal transmission port. Implementation method]. Referring to the third figure, the wiring of the transmission line in the high-speed printed circuit board of the present invention is constructed by using a star topology, a driver in a printed circuit board, and the driver is a north bridge wafer 20 in this embodiment. The north bridge chip 20 is connected to a connection point a via a main transmission line 28, and the connection point A is connected to the plurality of receivers by the branch transmission lines 222, 242, 262. In the present embodiment, the receivers are a plurality of PCI_X slots 22, 24, 26. A damping resistor R is connected in series with one end of the north bridge wafer 2 (<800 mil) on the main transmission line 28, and the resistance of the damping resistor r should match the characteristic impedance of the main transmission line 28, in the specific implementation of the present invention. In the example, the main transmission line 28 has a characteristic impedance value of about 56 ohms, and the north bridge wafer 20 has an internal resistance of about 24 ohms, and thus the damping resistor r can be 33 ohms. In theory, the wiring pattern of the 8 1299245 dare is such that the lengths of the branching lines 222, 242 and 262 are exactly equal, but considering the actual wiring requirements, some of the design allowances are reserved, so the branch transmission lines are Length allows a certain gap, but the
； 差距是越小越好，該等任意兩條分支傳輸線之長度差異L •之允許範圍可根據以下公式計算： • 2T< Tr • 2L/V<Tr L<(Tr*V)/2 即：長度差異< (訊號傳輸速度*訊號傳輸時間）/2 _鲁 其中Tr爲晶片端訊號上升時間，、L爲任一插槽端與其 他插槽端之分支傳輸線長度差，Τ爲所述傳輸線長度差所 造成之訊號傳輸時間差，V爲訊號在傳輸線中之傳輸速 度，本實施例中訊號傳輸速度爲1.8*l〇8m/s，晶片端之訊 : 號上升時間大約爲〇.3ns。因此，在本實施例中，以i〇97mils (lmm=39.37mils)爲最大佈線差距。 在本發明高速印刷電路板中傳輸線之佈線架構之較 佳實施例中，該北橋晶片20發出之驅動訊號沿該主傳輸 線28傳遞，經過該連接點人後又分別沿該等分支傳輸線 222、242及262向該等PCI-X插槽22、24及26傳遞。同 瞻肇 時從該等PCI-X插槽22、24及26輸出之訊號也可分別 經由該等分支傳輸線222、242及262傳遞至該連接點A， 然後再經由该主傳輸線28傳遞至该北橋晶片2〇。由於兮* 北橋晶片20輸出之訊號傳遞至該等PCI-X插槽22、^ 及26所經過之線長相等或該線長相互之間之差異在一允 許之範圍以内，使得該等PCI-X插槽22、24及26上之 訊號之間沒有明顯之延遲。同時由於本發明採用星型拓樸 架構，各傳輸線之間只有一個連接點，只要在該主傳輸^ 2 8上串接該阻尼電阻R與主傳輸線2 8之阻抗四配以提高 該連接點處之訊號透射率，即可避免訊號從晶片端再次反 9 1299245 射，進而提高訊號傳輸品質。 -Φ值ini'!圖，從中可以看到本發明高速印刷電路板 專輸佈線架構之較佳實施例中，PCI_X插槽22、24、 • ϋ，號曲線重合聽號崎3G，振鈴、過沖和訊號 不同y專現象均已消除，訊號品質較好。 拉以上具體實施例中，在北橋晶片與PCI_X插槽之連 • 採用了生型拓樸架構，但本發明並不僅限於此，本印 口: ： η!線架構還可以應用於其它單驅動器多接收 為或夕驅動器多接收器之電路架構中。 _鲁綜上所述，本發明符合發明專禾丨要件，爰依法提出專 請。惟，以上所述者僅為本發明之較佳實施例，舉凡 ?=本案技蟄之人士，在爰依本發明精神所作之等效修飾 或雙化，皆應涵蓋於以下之申請專利範圍内。 :【圖式簡單說明】 不 第一圖係習知北橋晶片與PCI-X插槽間佈線架構之 意圖。 圖係習知拓樸架構下PCI-X插槽上之波形圖。The difference is as small as possible, the length difference of the length of any two branch transmission lines L • The allowable range can be calculated according to the following formula: • 2T< Tr • 2L/V<Tr L<(Tr*V)/2 ie: Length difference < (signal transmission speed * signal transmission time) / 2 _ 鲁 where Tr is the chip end signal rise time, L is the difference between the length of the branch transmission line of any slot end and the other slot end, Τ is the transmission line The difference in signal transmission time caused by the difference in length, V is the transmission speed of the signal in the transmission line. In this embodiment, the signal transmission speed is 1.8*l〇8m/s, and the signal at the chip end: the rise time of the number is about 〇3 ns. Therefore, in the present embodiment, the maximum wiring gap is i 〇 97 mils (lmm = 39.37 mils). In a preferred embodiment of the wiring structure of the transmission line in the high speed printed circuit board of the present invention, the driving signal from the north bridge wafer 20 is transmitted along the main transmission line 28, and the branch transmission lines 222, 242 are respectively passed through the connection point. And 262 are passed to the PCI-X slots 22, 24, and 26. Signals output from the PCI-X slots 22, 24, and 26 at the same time can also be transmitted to the connection point A via the branch transmission lines 222, 242, and 262, respectively, and then transmitted to the connection point A via the main transmission line 28. North Bridge chip 2 〇. Since the signal output from the 兮* Northbridge chip 20 is transmitted to the PCI-X slots 22, 22, and 26, the line lengths are equal or the difference between the line lengths is within an allowable range, so that the PCI- There is no significant delay between the signals on X slots 22, 24 and 26. At the same time, since the present invention adopts a star topology, there is only one connection point between the transmission lines, as long as the impedance of the damping resistor R and the main transmission line 28 are connected in series on the main transmission ^8 to improve the connection point. The signal transmission rate can avoid the signal from the chip end to reverse the 9 1299245, thereby improving the signal transmission quality. -Φ value ini'! Figure, from which it can be seen that in the preferred embodiment of the high-speed printed circuit board dedicated transmission wiring architecture of the present invention, the PCI_X slot 22, 24, • ϋ, the number curve coincides with the singular 3G, ringing, over Different y-specific phenomena have been eliminated, and the signal quality is better. In the above specific embodiment, the connection between the north bridge chip and the PCI_X slot is adopted. • The raw topology is adopted, but the present invention is not limited thereto. The stamp: : η! line architecture can also be applied to other single drives. Received in a circuit architecture that is a multi-receiver for a DAC driver. According to the above, the invention complies with the requirements of the invention, and is specially requested according to law. However, the above description is only a preferred embodiment of the present invention, and those skilled in the art, in the spirit of the present invention, equivalent modifications or double modifications should be included in the following patent claims. . : [Simple description of the diagram] The first diagram is the intent of the conventional wiring structure between the Northbridge chip and the PCI-X slot. The figure is a waveform diagram on the PCI-X slot under the conventional topology.
第二圖係本發明高速印刷電路板中傳輸線之佈線架 卜 構較佳實施例之線路架構示意圖。 第四圖係本發明高速印刷電路板中傳輸線之佈線架 構較佳實施例之PCI-X插槽上之波形圖。 【主要元件符號說明】 [習知] 北橋晶片 10 PCI-X插槽 12、13、14 主傳輸線 16 終端電阻 RIO、R12、R13、R14 訊號曲線 122、132、142 [本發明] 北橋晶片 20 PCI-X插槽 22、24、26 1299245 主傳輸線 28 阻尼電阻 R 連接點 A 分支傳輸線 222、242、262 訊號曲線 30 »· — 11The second drawing is a schematic diagram of the circuit structure of the preferred embodiment of the wiring frame of the transmission line in the high speed printed circuit board of the present invention. The fourth figure is a waveform diagram of the PCI-X socket of the preferred embodiment of the wiring structure of the transmission line in the high speed printed circuit board of the present invention. [Major component symbol description] [Practice] Northbridge chip 10 PCI-X slot 12, 13, 14 Main transmission line 16 Terminating resistor RIO, R12, R13, R14 Signal curve 122, 132, 142 [Invention] Northbridge chip 20 PCI -X slot 22, 24, 26 1299245 Main transmission line 28 Damping resistor R Connection point A Branch transmission line 222, 242, 262 Signal curve 30 »· - 11