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RU2378682C2 - INPUT STRUCTURE FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-)(VERSIONS) - Google Patents

INPUT STRUCTURE FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-)(VERSIONS) Download PDF

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RU2378682C2
RU2378682C2 RU2007146288/09A RU2007146288A RU2378682C2 RU 2378682 C2 RU2378682 C2 RU 2378682C2 RU 2007146288/09 A RU2007146288/09 A RU 2007146288/09A RU 2007146288 A RU2007146288 A RU 2007146288A RU 2378682 C2 RU2378682 C2 RU 2378682C2
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logical functions
functional
output
adder
input
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RU2007146288/09A
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RU2007146288A (en
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Лев Петрович Петренко (UA)
Лев Петрович Петренко
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Лев Петрович Петренко
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Abstract

FIELD: physics; computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations of summation and subtraction in position-sign codes. Each bit of the adder is made in form of structure-equivalent channels - positive and conditionally negative. In one version of implementation, the ith bit of each channel contains two OR logic components, two NAND logic components, two inverter gates and an AND logic component.
EFFECT: simplification of functional structure of the adder and faster operation.
2 cl, 13 dwg

Description

Текст описания приведен в факсимильном виде.

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The text of the description is given in facsimile form.
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Claims (2)

1. Входная структура параллельного сумматора в позиционно-знаковых кодах f(+/-), условно «i» разряд которой выполнен в виде двух эквивалентных по струкгуре логических функций положительного и условно отрицательного каналов суммирования слагаемых и каждый канал «i» разряда включает входные логические функции f1({)-ИЛИ и f1(&)-И-HE, две функциональные входные связи, которые являются функциональными связями приема входных аргументов +ni и +mi или -ni и -mi, в соответствующих каналах, а выходные функциональные связи этих логических функций, которые формируют преобразованные аргументы первой промежуточной суммы
Figure 00000061
или
Figure 00000062
и измененные по уровню аналогового сигнала аргументы
Figure 00000063
или
Figure 00000064
в соответствующих каналах, являются функциональными входными связями выходных логических функций f1(&)-И и f2(&)-И-НЕ, которые формируют преобразованные аргументы выходных промежуточных сумм без изменения уровня аналогового сигнала
Figure 00000065
или
Figure 00000066
и выходных аргументов промежуточных сумм с измененным уровнем аналогового сигнала
Figure 00000067
или
Figure 00000068
выходные функциональные связи которых являются выходными функциональными связями соответствующих по знаку каналов, отличающаяся тем, что дополнительно введены в каждый канал логическая функция f2({)-ИЛИ и инвертирующие функции f1(&)-HE и f2(&)-HE, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000069

«=& 1=» - инвертирующая функция f1(&)-HE или функция изменения активности аналоговых сигналов.1. The input structure of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical functions of positive and conditionally negative summation channels of equivalent terms and each channel of “i” discharge includes input logic functions f 1 ({) -OR and f 1 (&) - AND-HE, two functional input links, which are functional links for receiving input arguments + n i and + m i or -n i and -m i , in the corresponding channels , and the output functional connections of these logical functions, which rmiruyut converted arguments first intermediate sum
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or
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and arguments changed in level of the analog signal
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or
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in the corresponding channels, are the functional input links of the output logical functions f 1 (&) - And and f 2 ( & ) -AND-NOT, which form the converted arguments of the output intermediate sums without changing the level of the analog signal
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or
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and output arguments of intermediate sums with a changed analog signal level
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or
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the output functional links of which are the output functional links of the corresponding sign of the channels, characterized in that the logical function f 2 ({) -OR or inverting functions f 1 ( & ) -HE and f 2 ( & ) -HE are additionally introduced into each channel the functional relationships of logical functions in the adder structure are made in accordance with a mathematical model of the form
Figure 00000069

“= & 1 =” is the inverting function f 1 ( & ) -HE or the function of changing the activity of analog signals. 2. Входная структура параллельного сумматора в позиционно-знаковых кодах f(+/-), условно «i» разряд которой выполнен в виде двух эквивалентных по структуре логических функций положительного и условно отрицательного каналов суммирования слагаемых, и каждый канал «i» разряда включает логические функции f1(})-ИЛИ и f1(&)-И, отличающаяся тем, что дополнительно введены логические функции f1(}&)-ИЛИ-НЕ, f2(}&)-ИЛИ-НЕ и f3(}&)-ИЛИ-НЕ, при этом функциональные связи логических функций выполнены во входной структуре сумматора в соответствии с математической моделью вида
Figure 00000070
2. The input structure of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical functions of positive and conditionally negative summation channels of equivalent components, and each channel “i” of the discharge includes logical functions f 1 (}) - OR and f 1 ( & ) -and, characterized in that the logical functions f 1 (} & ) -OR-NOT, f 2 (} & ) -OR-NOT and f 3 ( } & ) -OR-NOT, while the functional relationships of logical functions are made in the input structure of the adder in accordance with the mathematical model of the species
Figure 00000070
RU2007146288/09A 2007-12-17 2007-12-17 INPUT STRUCTURE FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-)(VERSIONS) RU2378682C2 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2422879C1 (en) * 2010-03-04 2011-06-27 Лев Петрович Петренко FUNCTIONAL STRUCTURE FOR PRE-ADDER OF PARALLEL-SERIAL MULTIPLIER fΣ(Σ) WITH MULTIPLICAND ARGUMENTS [mj]f(2n) AND MULTIPLIER ARGUMENTS [ni]f(2n) IN POSITION FORMAT (VERSIONS)
RU2439658C1 (en) * 2010-11-03 2012-01-10 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PREVIOUS SUMMATOR fΣ([ni]&[ni,0]), CONDITIONALLY "i AND "i+1" DIGITS OF "k" GROUP OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) FOR POSITIONAL ARGUMENTS OF MULTIPLICAND [ni]f(2n) WITH APPLICATION OF ARITHMETICAL AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS OF RUSSIAN LOGIC)
RU2443008C1 (en) * 2010-07-22 2012-02-20 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF A TRANSFORMER OF PRELIMINARY FA fΣ [ni]&[mi](2n) OF PARALLEL-SERIAL MULTIPLICATOR fΣ (Σ) CONDITIONALLY, OF "i" DIGIT TO SUM UP OF POSITIONAL ADDITIVE OF SUMS [ni]f(2n) AND [mi]f(2n) OF PARTIAL PRODUCTS USING ARITHMETICAL AXIOMS OF TERNARY NOTATION f(+1, 0, -1) WITH THE FORMATION OF A RESULTING SUM [SΣ]f(2n) IN A POSITIONAL FORMAT
RU2480815C1 (en) * 2012-04-24 2013-04-27 Лев Петрович Петренко FUNCTIONAL FIRST INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) AND ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM (2Sj)1 d1/dn "LEVEL 2" AND (1Sj)1 d1/dn "LEVEL 1" OF FIRST TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC)
RU2480816C1 (en) * 2012-04-24 2013-04-27 Лев Петрович Петренко FUNCTIONAL SECOND INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) И ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM ±[1,2Sj]1 d1/dn OF SECOND TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC)
RU2480814C1 (en) * 2012-04-24 2013-04-27 Лев Петрович Петренко FUNCTIONAL OUTPUT STRUCTURE OF CONDITIONAL BIT "j" OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS OF INTERMEDIATE ARGUMENTS (2Sj)2 d1/dn "LEVEL 2" AND (1Sj)2 d1/dn "LEVEL 1" OF SECOND TERM AND INTERMEDIATE ARGUMENTS (2Sj)1 d1/dn "LEVEL 2" AND (1Sj)1 d1/dn "LEVEL 1" OF FIRST TERM OF "COMPLENTARY CODE RU" FORMAT WITH GENERATION OF RESULTANT ARGUMENTS OF SUM (2Sj)f(2n) "LEVEL 2" AND (1Sj)f(2n) "LEVEL 1" IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2420868C1 (en) * 2009-10-02 2011-06-10 Лев Петрович Петренко METHOD OF GENERATING TRANSFORMED ARGUMENTS OF ANALOGUE SIGNALS (0j)i AND (0j+1)i; END-TO-END PARALLEL SHIFT f(←←) FOR TRANSFORMING POSITION-SIGN ARGUMENTS OF ANALOGUE SIGNALS ±[nj]f(+/-) IN CONDITIONAL "i" MINIMISATION ZONE AND FUNCTIONAL STRUCTURE FOR IMPLEMENTING SAID METHOD (VERSIONS)
RU2420869C1 (en) * 2009-10-05 2011-06-10 Лев Петрович Петренко METHOD OF GENERATING END-TO-END SUCCESSIVE SHIFT DURING LOGIC DIFFERENTIATION d/dn OF POSITIONAL ARGUMENTS [mj]f(2n) TAKING INTO ACCOUNT SIGN THEREOF IN ORDER TO CREATE POSITION-SIGN STRUCTURE -±[mj]f(+/-)min WITH MINIMUM NUMBER OF ARGUMENTS ACTIVE THEREIN (VERSIONS)
RU2427028C2 (en) * 2009-11-10 2011-08-20 Лев Петрович Петренко FUNCTIONAL INPUT STRUCTURE WITH LOGIC DIFFERENTIATION PROCEDURE d/dn OF FIRST INTERMEDIATE SUM OF MINIMISED ARGUMENTS OF TERMS ±[ni]f(+/-)min AND ±[mi]f(+/-)min (VERSIONS OF RUSSIAN LOGIC)
RU2424548C1 (en) * 2009-11-10 2011-07-20 Лев Петрович Петренко FUNCTIONAL INPUT STRUCTURE OF ADDER WITH SELECTIVE LOGIC DIFFERENTIATION d*/dn OF FIRST INTERMEDIATE SUM ±[S1 i] OF MINIMISED ARGUMENTS OF TERMS ±[ni]f(+/-)min and ±[mi]f(+/-)min (VERSIONS)

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RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device
UA23363U (en) * 2006-11-28 2007-05-25 Admiral Makarov Shipbuilding N Parallel adder

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SU1727120A1 (en) * 1989-12-22 1992-04-15 Курский Политехнический Институт Device for parallel addition of binary signed numbers
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device
UA23363U (en) * 2006-11-28 2007-05-25 Admiral Makarov Shipbuilding N Parallel adder

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2422879C1 (en) * 2010-03-04 2011-06-27 Лев Петрович Петренко FUNCTIONAL STRUCTURE FOR PRE-ADDER OF PARALLEL-SERIAL MULTIPLIER fΣ(Σ) WITH MULTIPLICAND ARGUMENTS [mj]f(2n) AND MULTIPLIER ARGUMENTS [ni]f(2n) IN POSITION FORMAT (VERSIONS)
RU2443008C1 (en) * 2010-07-22 2012-02-20 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF A TRANSFORMER OF PRELIMINARY FA fΣ [ni]&[mi](2n) OF PARALLEL-SERIAL MULTIPLICATOR fΣ (Σ) CONDITIONALLY, OF "i" DIGIT TO SUM UP OF POSITIONAL ADDITIVE OF SUMS [ni]f(2n) AND [mi]f(2n) OF PARTIAL PRODUCTS USING ARITHMETICAL AXIOMS OF TERNARY NOTATION f(+1, 0, -1) WITH THE FORMATION OF A RESULTING SUM [SΣ]f(2n) IN A POSITIONAL FORMAT
RU2439658C1 (en) * 2010-11-03 2012-01-10 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PREVIOUS SUMMATOR fΣ([ni]&[ni,0]), CONDITIONALLY "i AND "i+1" DIGITS OF "k" GROUP OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) FOR POSITIONAL ARGUMENTS OF MULTIPLICAND [ni]f(2n) WITH APPLICATION OF ARITHMETICAL AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS OF RUSSIAN LOGIC)
RU2480815C1 (en) * 2012-04-24 2013-04-27 Лев Петрович Петренко FUNCTIONAL FIRST INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) AND ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM (2Sj)1 d1/dn "LEVEL 2" AND (1Sj)1 d1/dn "LEVEL 1" OF FIRST TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC)
RU2480816C1 (en) * 2012-04-24 2013-04-27 Лев Петрович Петренко FUNCTIONAL SECOND INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) И ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM ±[1,2Sj]1 d1/dn OF SECOND TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC)
RU2480814C1 (en) * 2012-04-24 2013-04-27 Лев Петрович Петренко FUNCTIONAL OUTPUT STRUCTURE OF CONDITIONAL BIT "j" OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS OF INTERMEDIATE ARGUMENTS (2Sj)2 d1/dn "LEVEL 2" AND (1Sj)2 d1/dn "LEVEL 1" OF SECOND TERM AND INTERMEDIATE ARGUMENTS (2Sj)1 d1/dn "LEVEL 2" AND (1Sj)1 d1/dn "LEVEL 1" OF FIRST TERM OF "COMPLENTARY CODE RU" FORMAT WITH GENERATION OF RESULTANT ARGUMENTS OF SUM (2Sj)f(2n) "LEVEL 2" AND (1Sj)f(2n) "LEVEL 1" IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC)

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