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RU2380741C1 - FUNCTIONAL STRUCTURE OF CONDITIONALLY "i" POSITION OF PARALLEL ADDER FOR TERNARY NUMBER SYSTEM f(+1,0,-1) IN ITS POSITION-SIGN FORMAT f(+/-) - Google Patents

FUNCTIONAL STRUCTURE OF CONDITIONALLY "i" POSITION OF PARALLEL ADDER FOR TERNARY NUMBER SYSTEM f(+1,0,-1) IN ITS POSITION-SIGN FORMAT f(+/-) Download PDF

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RU2380741C1
RU2380741C1 RU2008116450/09A RU2008116450A RU2380741C1 RU 2380741 C1 RU2380741 C1 RU 2380741C1 RU 2008116450/09 A RU2008116450/09 A RU 2008116450/09A RU 2008116450 A RU2008116450 A RU 2008116450A RU 2380741 C1 RU2380741 C1 RU 2380741C1
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functional
positive
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conditionally
adder
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RU2008116450A (en
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Лев Петрович Петренко (UA)
Лев Петрович Петренко
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Лев Петрович Петренко
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Abstract

FIELD: information technologies.
SUBSTANCE: invention may be used for building arithmetic units and executing arithmetic operations of summing up and subtracting in position-sign codes. Each adder position is made in the form of two structurally equivalent channels - positive and conditionally negative channels for summing up summands. In one of the implementation versions, each channel includes four OR gates, three OR-NOT gates, six AND gates, AND-NOT gate.
EFFECT: device speedup.
2 cl, 9 dwg, 4 ex

Description

Текст описания приведен в факсимильном виде.

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The text of the description is given in facsimile form.
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Claims (1)

1. Функциональная структура условно «i» разряда параллельного сумматора троичной системы счисления f(+l,0,-l) в ее позиционно-знаковом формате f(+/-), в которой условно «i» разряд выполнен в виде двух эквивалентных по структуре логических функций положительного и условно отрицательного каналов суммирования аргументов слагаемых ±[ni] и ±[mi] позиционно-знакового формата
f(+/-), в которой положительный канал суммирования включает входные логические функции f1(})-ИЛИ и f1(&)-И-HE, в которых функциональные входные связи являются входными связями сумматора для приема положительных входных аргументов +ni; и +mi, а функциональные выходные их связи, которые соответствуют положительному аргументу первой промежуточной сумме
Figure 00000092
и второй промежуточной сумме
Figure 00000093
с измененным уровнем аналогового сигнала, являются функциональными входными связями логической функции f2(&)-И, в которой функциональная выходная связь является функциональной выходной связью сумматора, формирующая преобразованный аргумент
Figure 00000094
при этом условно «i» разряд положительного канала сумматора включает логическую функцию f3(&)-И, функциональные входные связи являются функциональными входными связями канала, и выходную логическую функцию f4(})-ИЛИ, в которой функциональная выходная связь является выходной функциональной связью канала для формирования результирующей суммы +Si, а ее функциональная входная связь является функциональной выходной связью логической функции f4(&)-И, положительный канал сумматора также включает логические функции f1(&)-И, f5(&)-И, f6(&)-И и логическую функцию f3(})-ИЛИ, в которой функциональная выходная связь является функциональной выходной связью канала для формирования преобразованного аргумента
Figure 00000095
отличающаяся тем, что в условно «i» разряд положительного канала суммирования введены логические функции f1(}&)-ИЛИ-НЕ,
f2(}&)-ИЛИ-НЕ, f3(}&)-ИЛИ-НЕ и логическая функция f2(})-ИЛИ, при этом функциональные входные связи в положительном канале функциональной структуре параллельного сумматора выполнены в соответствии с математической моделью вида
Figure 00000096

Figure 00000097
2. Функциональная структура условно «i» разряда параллельного сумматора троичной системы счисления f(+l,0,-l) в ее позиционно-знаковом формате f(+/-), в которой условно «i» разряд выполнен в виде двух эквивалентных по структуре логических функций положительного и условно отрицательного каналов суммирования аргументов слагаемых ±[ni] и ±[mi] позиционно-знакового формата f(+/-), в которой положительный канал суммирования «i» разряда включает логические функции fi(&)-И-HE, в которой две функциональные входные связи являются входными связями канала сумматора для приема положительных входных аргументов +ni и +mi, a функциональная выходная связь формирует положительный аргумент второй промежуточной суммы
Figure 00000098
положительный канал также включает логические функции f1(})-ИЛИ, функциональные входные связи являются функциональными входными связями канала, включает логические функции f2(})-ИЛИ, f4(})-ИЛИ, f5(})-ИЛИ, логическую функцию f1(&)-И, в которой две функциональные входные связи являются входными связями канала сумматора, включает логические функции f2(&)-И, f3(&)-И-НЕ, f4(&)-И-HE, f2(&)-И, отличающаяся тем, что в условно «i» разряд положительного канала суммирования введены логические функции f3(})-ИЛИ, f1(}&)-ИЛИ-НЕ и f2(}&)-ИЛИ-НЕ, при этом функциональные входные связи в положительном канале функциональной структуры параллельного сумматора выполнены в соответствии с математической моделью вида
Figure 00000099
1. The functional structure of the conditionally “i” discharge of the parallel adder of the ternary number system f (+ l, 0, -l) in its position-sign format f (+/-), in which the conditionally “i” digit is made in the form of two equivalent the structure of logical functions of positive and conditionally negative channels for summing the arguments of the terms ± [n i ] and ± [m i ] position-sign format
f (+/-), in which the positive summing channel includes the input logical functions f 1 (}) - OR and f 1 ( & ) -I-HE, in which the functional input links are the input links of the adder to receive positive input arguments + n i ; and + m i , and the functional output of their connection, which correspond to a positive argument to the first intermediate sum
Figure 00000092
and second subtotal
Figure 00000093
with a changed level of the analog signal, are the functional input links of the logical function f 2 (&) - And, in which the functional output link is the functional output link of the adder, forming the converted argument
Figure 00000094
while conditionally “i” the discharge of the positive adder channel includes the logical function f 3 (&) - AND, the functional input links are the functional input links of the channel, and the output logical function f 4 (}) - OR, in which the functional output link is the output functional the channel link to form the resulting sum + S i , and its functional input link is the functional output link of the logical function f 4 (&) - And, the positive adder channel also includes the logical functions f 1 (&) - And, f 5 (&) - And, f 6 (&) - And and logical function f 3 (}) - OR, in which the functional output link is the functional output link of the channel to form the converted argument
Figure 00000095
characterized in that in the conditionally “i” bit of the positive summation channel, logical functions f 1 (} & ) -OR-NOT are introduced,
f 2 (} & ) -OR- NOT, f 3 (} & ) -OR- NOT and the logical function f 2 (}) - OR, while the functional input connections in the positive channel of the functional structure of the parallel adder are made in accordance with the mathematical model kind of
Figure 00000096

Figure 00000097
2. The functional structure of the conditionally “i” discharge of the parallel adder of the ternary number system f (+ l, 0, -l) in its position-sign format f (+/-), in which the conditionally “i” discharge is made in the form of two equivalent the structure of the logical functions of the positive and conditionally negative channels for summing the arguments of the terms ± [n i ] and ± [m i ] of the position-sign format f (+/-), in which the positive channel for summing the “i” discharge includes the logical functions fi ( & ) - AND-HE, in which two functional input links are the input links of the sum channel Ator for receiving a positive input arguments and + n i + m i, a functional output communication generates a positive argument second intermediate sum
Figure 00000098
the positive channel also includes the logical functions f 1 (}) - OR, the functional input links are the functional input links of the channel, includes the logical functions f 2 (}) - OR, f 4 (}) - OR, f 5 (}) - OR, the logical function f 1 (&) - AND, in which two functional input connections are the input links of the adder channel, includes the logical functions f 2 (&) - And, f 3 ( & ) -I-NOT, f 4 ( & ) -I -HE, f 2 (&) - AND, characterized in that the logical functions f 3 (}) - OR, f 1 (} & ) -OR-NOT and f 2 (} are introduced into the conditionally “i” bit of the positive summation channel k) -or-not, at the same time functional in odnye communication channel parallel adder positive functional structure implemented in accordance with the mathematical model of the form
Figure 00000099
RU2008116450/09A 2008-04-29 2008-04-29 FUNCTIONAL STRUCTURE OF CONDITIONALLY "i" POSITION OF PARALLEL ADDER FOR TERNARY NUMBER SYSTEM f(+1,0,-1) IN ITS POSITION-SIGN FORMAT f(+/-) RU2380741C1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2429522C1 (en) * 2010-05-25 2011-09-20 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF ADDER fi(Σ) OF ARBITRARY "i" BIT FOR LOGIC-DYNAMIC PROCESS OF SUMMATION OF POSITIONAL ARGUMENTS OF TERMS [ni]f(2n) and [mi]f(2n) USING ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS OF RUSSIAN LOGIC)
RU2439659C1 (en) * 2010-06-01 2012-01-10 Лев Петрович Петренко METHOD OF LOGIC-DYNAMIC PROCESS OF SUMMATION OF POSITIONAL ARGUMENTS OF ANALOGUE SIGNALS [ni]f(2n) AND [mi]f(2n) WITH APPLICATION OF ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND GENERATION OF RESULTING SUM OF ANALOGUE SIGNALS [Sj]f(2n) IN POSITIONAL FORMAT (RUSSIAN LOGIC)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1727120A1 (en) * 1989-12-22 1992-04-15 Курский Политехнический Институт Device for parallel addition of binary signed numbers
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device
UA23363U (en) * 2006-11-28 2007-05-25 Admiral Makarov Shipbuilding N Parallel adder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1727120A1 (en) * 1989-12-22 1992-04-15 Курский Политехнический Институт Device for parallel addition of binary signed numbers
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device
UA23363U (en) * 2006-11-28 2007-05-25 Admiral Makarov Shipbuilding N Parallel adder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2429522C1 (en) * 2010-05-25 2011-09-20 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF ADDER fi(Σ) OF ARBITRARY "i" BIT FOR LOGIC-DYNAMIC PROCESS OF SUMMATION OF POSITIONAL ARGUMENTS OF TERMS [ni]f(2n) and [mi]f(2n) USING ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS OF RUSSIAN LOGIC)
RU2439659C1 (en) * 2010-06-01 2012-01-10 Лев Петрович Петренко METHOD OF LOGIC-DYNAMIC PROCESS OF SUMMATION OF POSITIONAL ARGUMENTS OF ANALOGUE SIGNALS [ni]f(2n) AND [mi]f(2n) WITH APPLICATION OF ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND GENERATION OF RESULTING SUM OF ANALOGUE SIGNALS [Sj]f(2n) IN POSITIONAL FORMAT (RUSSIAN LOGIC)

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