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RU2378681C2 - FUNCTIONAL STRUCTURE FOR CORRECTING INTERMEDIATE SUM ±[S3i] ARGUMENTS FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-) - Google Patents

FUNCTIONAL STRUCTURE FOR CORRECTING INTERMEDIATE SUM ±[S3i] ARGUMENTS FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-) Download PDF

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RU2378681C2
RU2378681C2 RU2007146286/09A RU2007146286A RU2378681C2 RU 2378681 C2 RU2378681 C2 RU 2378681C2 RU 2007146286/09 A RU2007146286/09 A RU 2007146286/09A RU 2007146286 A RU2007146286 A RU 2007146286A RU 2378681 C2 RU2378681 C2 RU 2378681C2
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conditionally
functional
discharge
argument
logical
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RU2007146286A (en
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Лев Петрович Петренко (UA)
Лев Петрович Петренко
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Лев Петрович Петренко
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Abstract

FIELD: physics; computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations of summation and subtraction in position-sign codes. Each bit of the adder is made in form of two channels of equivalent structure - positive and conditionally negative. In on version of implementation, the ith bit of each channel contains four AND logic components and two NOR logic components.
EFFECT: simplification of the functional structure of the adder.
4 cl, 21 dwg

Description

Текст описания приведен в факсимильном виде.

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The text of the description is given in facsimile form.
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Claims (4)

1. Функциональная структура корректировки аргументов промежуточной суммы ±[S3i] параллельного сумматора в позиционно-знаковых кодах f(+/-), условно «i» разряд которой выполнен в виде двух эквивалентных по структуре логических функций положительного и условно отрицательного каналов корректировки аргументов, и каждый канал «i» разряда включает три логические функции f1(&)-И, f3(&)-И и f4(&)-И, которые формируют преобразованные аргументы
Figure 00000078
или
Figure 00000079
Figure 00000080
или
Figure 00000081
и
Figure 00000082
или
Figure 00000083
при этом две функциональные дополнительные входные связи являются входными связями канала для приема преобразованных аргументов
Figure 00000084
или
Figure 00000085
и
Figure 00000086
или
Figure 00000087
условно «i-1» разряда, а функциональные выходные связи логических функций f1(&)-И и f4(&)-И, которые формируют преобразованный аргумент
Figure 00000088
или
Figure 00000089
и
Figure 00000090
или
Figure 00000091
условно «i» разряда также являются функциональными выходными связями канала для подачи аргумента в «i+1» разряда, при этом функциональные входные связи логической функции f1(&)-И являются функциональными входными связями канала для приема аргумента промежуточной суммы
Figure 00000092
или
Figure 00000093
условно «i» разряда и аргумента промежуточной суммы
Figure 00000094
или
Figure 00000095
условно «i-1» разряда, при этом функциональные входные связи логической функции f4(&)-И являются функциональными входными связями канала для приема аргументов промежуточной суммы
Figure 00000096
или
Figure 00000097
условно «i» разряда, для приема аргументов промежуточной суммы с измененным уровнем аналогового сигнала
Figure 00000098
или
Figure 00000099
условно «i-1» разряда и аргументов промежуточной суммы
Figure 00000100
или
Figure 00000101
условно «i-2» разряда, а функциональные входные связи логической функции f3(&)-И являются функциональными входными связями канала для приема аргументов промежуточной суммы
Figure 00000102
или
Figure 00000103
условно «i» разряда и аргументов промежуточной суммы с измененным уровнем аналогового сигнала
Figure 00000104
или
Figure 00000105
условно «i-1» разряда, отличающаяся тем, что в условно «i» разряда каждого канала введена логическая функция f2(&)-И, которая формирует преобразованный аргумент
Figure 00000106
или
Figure 00000107
логическая функция f1(}&)-ИЛИ-НЕ и логическая функция f2(}&)-ИЛИ-НЕ, которая формирует выходной аргумент результирующей суммы +Si или -Si, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000108
1. Functional structure of the argument correction of the intermediate sum ± [S 3 i] of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical structure of the positive and conditionally negative argument correction channels equivalent in structure , and each channel of the “i” category includes three logical functions f 1 (&) - And, f 3 (&) - And and f 4 (&) - And, which form the converted arguments
Figure 00000078
or
Figure 00000079
Figure 00000080
or
Figure 00000081
and
Figure 00000082
or
Figure 00000083
in this case, two functional additional input links are input channel links for receiving converted arguments
Figure 00000084
or
Figure 00000085
and
Figure 00000086
or
Figure 00000087
conditionally “i-1” discharge, and the functional output connections of the logical functions f 1 (&) - And and f 4 (&) - And, which form the converted argument
Figure 00000088
or
Figure 00000089
and
Figure 00000090
or
Figure 00000091
conditionally, “i” discharges are also functional output links of the channel for supplying an argument to the “i + 1” discharges, while the functional input relations of the logical function f 1 (&) - And are functional input relations of the channel for receiving the intermediate sum argument
Figure 00000092
or
Figure 00000093
conditionally “i” of the discharge and the intermediate sum argument
Figure 00000094
or
Figure 00000095
conditionally "i-1" discharge, while the functional input links of the logical function f 4 (&) - And are the functional input links of the channel for receiving the arguments of the intermediate sum
Figure 00000096
or
Figure 00000097
conditionally "i" discharge, to receive the arguments of the intermediate sum with a changed level of the analog signal
Figure 00000098
or
Figure 00000099
conditionally “i-1” discharge and intermediate sum arguments
Figure 00000100
or
Figure 00000101
conditionally "i-2" category, and the functional input links of the logical function f 3 (&) - And are the functional input links of the channel for receiving arguments of the intermediate sum
Figure 00000102
or
Figure 00000103
conditionally “i” of the discharge and arguments of the intermediate sum with a changed level of the analog signal
Figure 00000104
or
Figure 00000105
conditionally “i-1” discharge, characterized in that the logical function f 2 (&) - And, which forms the converted argument, is introduced into the conditionally “i” discharge of each channel
Figure 00000106
or
Figure 00000107
the logical function f 1 (} & ) -OR-NOT and the logical function f 2 (} & ) -OR-NOT, which forms the output argument of the resulting sum + S i or -S i , while the functional relationships of the logical functions in the adder structure are made in accordance with the mathematical model of the form
Figure 00000108
 2. Функциональная структура корректировки аргументов промежуточной суммы ±[S3i] параллельного сумматора в позиционно-знаковых кодах f(+/-), условно «i» разряд которой выполнен в виде двух эквивалентных по структуре логических функций положительного и условно отрицательного каналов корректировки аргументов и каждый канал «i» разряда включает логическую функцию f1(&)-И, первая функциональная входная связь которой является выходной функциональной связью логической функции f5(&)-И-НЕ, которая формирует преобразованный аргумент
Figure 00000109
или
Figure 00000110
отличающаяся тем, что в условно «i» разряда каждого канала введены логические функции f1(&)-И-НЕ, f2(&)-И-НЕ, f3(&)-И-НЕ и f4(&)-И-НЕ, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000111
2. The functional structure of the arguments correction of the intermediate sum ± [S 3 i] of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical structure of the positive and conditionally negative argument correction channels equivalent in structure and each channel “i” of the discharge includes a logical function f 1 (&) - AND, the first functional input of which is the output functional connection of the logical function f 5 ( & ) -AND-NOT, which forms the converted argument
Figure 00000109
or
Figure 00000110
characterized in that in the conditionally “i” discharge of each channel the logical functions f 1 ( & ) -I-NOT, f 2 ( & ) -I-NOT, f 3 ( & ) -I-NOT and f 4 ( & ) are introduced -AND NOT, while the functional relationships of logical functions in the adder structure are made in accordance with a mathematical model of the form
Figure 00000111
 3. Функциональная структура корректировки аргументов промежуточной суммы ±[S3i] параллельного сумматора в позиционно-знаковых кодах f(+/-), условно «i» разряд которой выполнен в виде двух эквивалентных по структуре логических функций положительного и условно отрицательного каналов корректировки аргументов, и каждый канал «i» разряда включает логическую функцию f1(&)-И, первая функциональная входная связь которой является выходной функциональной связью логической функции f1(&)-И-HE, которая формирует преобразованный аргумент
Figure 00000112
или
Figure 00000113
отличающаяся тем, что в условно «i» разряда каждого канала введены логические функции f1(})-ИЛИ, f2(})-ИЛИ, f3(})-ИЛИ и f4(})-ИЛИ, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000114
3. Functional structure of the argument correction of the intermediate sum ± [S 3 i] of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical structure of the positive and conditionally negative argument correction channels equivalent in structure , and each channel “i” of the discharge includes a logical function f 1 (&) - AND, the first functional input of which is the output functional connection of the logical function f 1 ( & ) -I-HE, which forms the converted argument
Figure 00000112
or
Figure 00000113
characterized in that the logical functions f 1 (}) - OR, f 2 (}) - OR, f 3 (}) - OR and f 4 (}) - OR, while functional communications of logical functions in the adder structure are made in accordance with a mathematical model of the form
Figure 00000114
 4. Функциональная структура корректировки аргументов промежуточной суммы ±[S3i] параллельного сумматора в позиционно-знаковых кодах f(+/-), условно «i» разряд которой выполнен в виде двух эквивалентных по структуре логических функций положительного и условно отрицательного каналов корректировки аргументов, отличающаяся тем, что в условно «i» разряда каждого канала введены логические функции f1(}&)-ИЛИ-НЕ, f2(}&)-ИЛИ-HE, f3(}&)-ИЛИ-HE, f4(}&)-ИЛИ-НЕ, f5(}&)-ИЛИ-НЕ и f6(}&)-ИЛИ-НЕ, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000115
4. Functional structure of the argument correction of the intermediate sum ± [S 3 i] of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical structure of the positive and conditionally negative argument correction channels equivalent in structure , characterized in that in the conditionally “i” discharge of each channel the logical functions f 1 (} & ) -OR-NOT, f 2 (} & ) -OR-HE, f 3 (} & ) -OR-HE, f 4 (} & ) -OR- NOT, f 5 (} & ) -OR- NOT and f 6 (} & ) -OR- NOT, while the functional relationships of logical functions in the structure of the adder made in accordance with a mathematical model of the form
Figure 00000115
RU2007146286/09A 2007-12-17 2007-12-17 FUNCTIONAL STRUCTURE FOR CORRECTING INTERMEDIATE SUM ±[S3i] ARGUMENTS FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-) RU2378681C2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1727120A1 (en) * 1989-12-22 1992-04-15 Курский Политехнический Институт Device for parallel addition of binary signed numbers
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device
UA23363U (en) * 2006-11-28 2007-05-25 Admiral Makarov Shipbuilding N Parallel adder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1727120A1 (en) * 1989-12-22 1992-04-15 Курский Политехнический Институт Device for parallel addition of binary signed numbers
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device
UA23363U (en) * 2006-11-28 2007-05-25 Admiral Makarov Shipbuilding N Parallel adder

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