JPH07169950A - MOSFET device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a high-power MOSFET device more competitive with a bipolar transistor. A wafer (120) of semiconductor material having a first surface and a second surface parallel to each other has a first conductivity type main body portion (121). The main body part (121) has a second conductivity type opposite to the first conductivity type, and has polygonal base regions (122, 123) symmetrically spaced from the first surface within the main body part. And extending from the first surface toward the second surface between the base regions adjacent to each other, 1 × 1
A common conductive region (128) having a conductivity corresponding to the implantation amount of phosphorus atoms of 0 ^{12 to} 1 × 10 ¹⁴ atoms / cm ² and from the first surface inside the periphery of the first surface of the base region. A first conductive type polygonal ring-shaped source region (126, 127) disposed in the base region, and a channel region (160 to 127) between an outer peripheral edge of the source region and the peripheral edge of the base region. 164) are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET device, and more particularly to a MOSFET device which can be used in a high power application with a considerably high reverse voltage and a very low conduction resistance.

[0002]

2. Description of the Related Art The main characteristic of a bipolar transistor with respect to a MOSFET is that the resistance per unit conductive area of the bipolar transistor when conducting is very low. M
OSFETs have many advantages over bipolar transistors, which are extremely fast switching speeds,
It has a very high gain and no secondary breakdown characteristics represented by minority carrier devices. But MOSFE
Since T has a high resistance during conduction, its use in high power switching applications is limited.

[0003]

It has a low forward resistance that can be used in high power switching applications in MOSFETs that could not be solved by such prior art and retains all of the many advantages over bipolar transistors. High power MOSFET which is more competitive with bipolar transistors in switching type applications
Providing an element, in particular, the forward resistance per unit area of the element is halved as compared with the limiting resistance per unit area conventionally existing in the MOSFET element, and M suitable for high power is provided.
It is a problem to be solved by the present invention to provide an OSFET device.

[0004]

[Means for Solving the Problems] The specific means for solving the above problems comprises the following constitutions as described in the claims.

That is, it has a first surface and a second surface parallel to the first surface, and also has a main body portion of a first conductivity type, and the surface of the main body portion has the first surface. And a second wafer of a semiconductor material having a second conductivity type opposite to the first conductivity type and symmetrically spaced from the first surface of the wafer in the main body portion. Extending from the first surface to the second surface between the base regions having a polygonal shape and adjacent base regions, 1
A common conductive region having a conductivity corresponding to the implantation amount of phosphorus atoms of × 10 ^{12 to} 1 × 10 ¹⁴ atoms / cm ² and from the first surface inside the peripheral edge of the first surface of the base region. Formed in the base region, the source region having a polygonal ring shape made of the material having the first conductivity type, and formed between the outer peripheral edge of the source region and the peripheral edge of the base region, A channel region in which the channel of the first conductivity type is formed, a gate insulating layer extending on the common conductive region and the channel region on the first surface, and a gate electrode formed on the gate insulating layer. And a source electrode connected to each of the source regions and their base regions, and a drain electrode coupled to the common conductive region.

[0006]

In the MOSFET device of the present invention, the common conductive region extends from the first surface to the second surface of the wafer between the base regions adjacent to each other, and is 1 × 10 ¹² pieces. It has a conductivity corresponding to the implantation amount of phosphorus atoms of 1 × 10 ¹⁴ atoms / cm ² .

Since the common conductive region has the above-described conductivity, the common conductive region is formed to have a high conductivity n ( ⁺ ), and the resistance of the MOSFET element when conducting is lowered. Further, due to the high conductivity n ( ⁺ ), a depletion layer formed by the junction between the main body portion of the wafer having the first conductivity type and the base region having the second conductivity type opposite to the first conductivity type is formed. It is possible to suppress the spread in the common conductive region. Thus, the current flowing in the common conductive region can flow in the common conductive region relatively unimpeded by the depletion layer.

This halves the conductive resistance per unit area of the MOSFET device. In addition, the geometrical array formed by forming the base region and the source region into a polygon,
The high packing density created by this compartmentalized structure is M
The packing of the device on the chip surface can be improved and the forward resistance of the device can be made smaller in order to produce a larger channel width per unit area than any of the heretofore known geometries of OSFETs. .

The MOS of the present invention constructed as a result
The FET device has become comparable to the conventional high power bipolar transistor device. It is the MO of the present invention
This is because the SFET device can retain all of the advantages of the MOSFET device over the bipolar device while also having a considerably low forward resistance, which is the main advantage of the bipolar device.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, FIGS. 1 and 2 showing a reference example of a MOSFET device relating to the present invention will be described. These figures show a silicon single crystal chip 20 (or some other suitable material) with a device electrode with the serpentine passages 21 best shown in FIG. 1 for increasing the current passing area of the device. ing. The passage 21 may have another geometric shape. The element shown is approximately 400
A device was formed having a reverse voltage of V and a reverse voltage of 90V to 400V with a conduction resistance of less than about 0.4Ω at a channel width of 50 cm. 400V element is 30A
The pulse current of. The 90 V element has a resistance of about 0.1 Ω in the forward direction at a channel length of 50 cm, and has a resistance of about 10 Ω.
A pulse current of up to 0 A is passed. A high voltage or constant voltage device is formed by changing the channel width.

Presently known MOSFET devices have a higher resistance in conduction than the above. For example, a 40 formed according to the prior art that can be compared to those described below.
A 0V MOSFET has a resistance in conduction greater than about 1.5Ω, whereas the conduction resistance of a device formed according to the present invention is less than about 0.4Ω. Moreover, the MOSFET of the present invention as a high power switching device has all of the advantages desired for a MOSFET device since it operates as a majority carrier device. These advantages include high switching speed, high gain and elimination of secondary breakdown properties present in minority carrier devices.

The device shown in FIGS. 1 and 2 has a metal gate electrode 2
With two source electrodes 22 and 23 divided by 4, the metal gate electrode 24 is fixed to the semiconductor device surface by a silicon dioxide layer 25, but spaced from it. The tortuous path of the gate oxide 24 actually has a length of 50 cm and has a number of 667 undulations, which is shown in simplified form in FIG. Other channel widths may be used. Source electrodes 22 and 23
Acts as a field plate to extend laterally as shown and to help expand the depletion region formed under reverse voltage conditions. Each of the source electrodes 22 and 23 supplies current to a common drain electrode 26 fixed to the bottom of the wafer. The relative dimensions of the elements, and in particular their thickness, have been greatly expanded in FIG. 2 for convenience of explanation. The silicon chip or wafer 20 is formed on an n ( ⁺ ) substrate having a thickness of about 0.36 mm. The n ( ⁻ ) epitaxial layer is provided on the chip (substrate) 20 and has a thickness and a resistivity according to a desired reverse voltage. All junctions formed in this epitaxial layer have a fairly high resistivity. In the illustrated embodiment, the epitaxial layer has a thickness of about 35 microns and a resistivity of about 20 Ω-cm. Epitaxial layer 20 for 90V device
Is 10 microns thick and has a resistivity of about 2.5 Ω-cm. A channel width of 50 cm is also used to provide the device with the desired current carrying capacity.

In the MOSFET device shown in FIGS. 1 and 2, there is an elongated serpentine p ( ⁺ ) region below each of the source electrodes 22 and 23, which region surrounds the serpentine passage shown in FIG. Extend to. These p ( ⁺ ) conductive regions are shown in FIG. 2 as p ( ⁺ ) regions 30 and 31, respectively, and the maximum p ( ⁺ ) region depth is greatly exaggerated to form a large diameter curvature. It is similar to those of the prior art except that it is present. This allows the device to withstand higher reverse voltages. For example, region 3
The depth of 0 and 31 is about 4 microns in the dimension x of FIG.
It is desirable that the dimension y is about 3 microns.

By using the D-MOS manufacturing technique,
Two n ( ⁺ ) regions 32 and 33 are formed below the source electrodes 22 and 23, respectively, and together with the p ( ⁺ ) regions 30 and 31, define n-type channel regions 34 and 35, respectively. The channel regions 34 and 35 are located below the gate oxide 25 and conduct conductivity from the sources 22 and 23 through the inversion layers 34 and 35 to the central region 40 below the gate 24 and then to the drain electrode 26. To do so, it can be inverted by applying a suitable bias signal to gate 24. Channels 34 and 35 have a length of about 1 micron.

According to conventional thinking, channels 34 and 3
Center n between 5 (and between p ( ⁺ ) regions 30 and 31)
It was said that the ( ^- ) region should have high resistivity in order for the device to withstand high reverse voltage. However, the fairly high resistivity n ( ⁻ ) material is also a critical factor in increasing the forward conduction resistance of the device.

In accordance with a feature of the present invention, a significant portion of this common conductive region consists of an n ( ⁺ ) region 40 formed beneath the gate oxide 25, which is made highly conductive. The n ( ⁺ ) regions 40 are about 4 microns deep, but can range in depth from about 3 microns to about 6 microns. Its exact conductivity is not known, but varies with depth and is high compared to the lower n ( ^- ) region. In particular, the n ( ⁺ ) region 40 is 1 × 10 ^{12 to} 1 × 10 ¹⁴ phosphorus atoms / 50 KV at a temperature of 1150 ° C. to 1250 ° C. with a diffusion condition of 30 minutes to 240 minutes.
It has a high conductivity determined by the total ion implantation dose of cm ² . It has been found that by making this region 40 a fairly highly conductive n ( ⁺ ) material by diffusion or other manipulation, the device characteristics are significantly improved and the resistance of the device in forward conduction is halved. Further, it has been found that providing the n ( ⁺ ) region 40 having high conductivity does not impair the reverse voltage characteristic of the MOSFET device. Therefore, the gate oxide 2
By making the region 40 between channels 34 and 35 below 5 more highly conductive, the resistance of the desired high power switching element during forward conduction is significantly reduced, and the MOSF
ET devices outperform comparable junction devices while retaining all of the advantages of MOSFET majority carrier operation.

In the above description of FIGS. 1 and 2, the conductive channels 34 and 35 are p ( ⁺ ) materials, so that they are, by application of a suitable gate voltage,
It can be seen that it is inverted to n-type conductivity to provide a majority carrier conductive channel from sources 22 and 23 to central region 40. However, obviously all of these conductivity types may be inverted so that the device may act as a p-channel device rather than as an n-channel device as described above.

One method of forming the device of FIGS. 1 and 2 is shown in FIGS. 3 to 6 as a reference example. According to FIG. 3, the base wafer 20 is shown as an n ( ⁺ ) material with an n ( ⁻ ) epitaxial layer on top of it. A thick oxide layer 50 is formed on the wafer 20 with windows 51 and 52 provided therein. These windows 51 and 52 have p (
⁺ ) Exposed to a boron atom beam in an ion implanter to form a region. Then the implanted boron atoms are
Deeply diffused into the wafer, forming a semi-circular p ( ⁺ ) concentrated region with a depth of about 4 microns as shown in FIG. During this diffusion operation, shallow oxide layers 53 and 54 are grown on the windows 51 and 52.

Next, as shown in FIG. 4, windows 61 and 62 are cut in oxide layer 50 and an n ( ⁺ ) implant is performed to produce n ( ^- ).
N ( ⁺ ) regions 63 and 64 are implanted in the epitaxial layer. This n ( ⁺ ) implantation is performed by phosphor beam. The implanted region is then transferred to the diffusion process, 115
By operating at 0 ° C. to 1250 ° C. for 30 minutes to 4 hours, the region 63 is formed at a concentration determined by the implantation amount of phosphorus atoms / cm ² of 1 × 10 ^{12 to} 1 × 10 ¹⁴ until a depth of about 3.5 μm is reached. And 64 are expanded and deepened. As will be described below, regions 63 and 64 form a new n ( ⁺ ) region that reduces the resistance of the device when it is conducting.

The n ( ⁺ ) regions 63 and 64 may be provided epitaxially if desired and may not be diffused. Similarly, a device constructed as described above may be manufactured by any desired process apparent to those skilled in the art.

A specific step in the manufacturing method is the channel injection and diffusion step shown in FIG. 5, in which p ( ⁺ ) regions 71 and 72 are formed in regions 63 and 64.
Identical windows 61 and 62 used for ( ⁺ ) injection
Is formed through. p ( ⁺ ) regions 71 and 72 are 1
It is formed by implantation with a boron beam of about 5 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² with a diffusion step of 150 to 1250 ° C. for 30 to 120 minutes.

Next, as shown in FIG. 6, a source pretreatment and a diffusion process of the source regions 32 and 33 are performed. This is done by a conventional non-critical phosphorus diffusion process, in which the diffusion is done through windows 61 and 62, and the source regions 32 and 33 automatically with respect to other preformed regions. Be aligned. Thus, the wafers are placed in a furnace and exposed to POCl ₃ in carrier gas at 850 ° C. to 1000 ° C. for 10 to 50 minutes.

When this step is completed, the basic junction structure required in FIG. 2 is constructed below the oxide, which junction structure acts as a conductive channel for the desired device and is connected to channel 34. Between 35 and p (
An n ( ⁺ ) region filled in a portion between the ⁺ ) regions 30 and 31 is formed. The manufacturing process is continued from the process of FIG. 6 to the device shown in FIG. 2, the oxide surface on the top of the chip is removed by an appropriate method, and the metal pattern to be the source electrodes 22 and 23 and the gate electrode 24 is removed. Once formed, the electrodes to the device are completed. Then, the drain electrode 26 is provided on the element by the next metallization operation. The entire device is then covered with a suitable coating and the source electrode 22
And 23 and the gate electrode 24 are connected to lead wires. This element is then mounted in a protective enclosure with some conductive support or drain electrode secured to the enclosure, which acts as a drain connector.

In the MOSFET device shown in FIGS. 1 and 2, each of the source region, the gate region and the drain on the surface of the wafer opposite to the source electrode is formed in a meandering and serpentine maze shape as shown. is there.
Such a shape may be another shape. For example, in FIG.
And as shown in FIG. 8, it may be a simple rectangular shape,
In this structure, a simple rectangular structure is formed in which a ring-shaped gate 80 and a ring-shaped first source electrode 81 are surrounded by a central source 82, and a peripheral surface is surrounded by a drain electrode 85 in a planar shape. . The device shown in FIG. 8 is contained in a base wafer of p ( ⁻ ) silicon single crystal 83, which has a buried n ( ⁺ ) region 84, and in the presence of this region the source 81 is formed. It is intended to reduce the lateral resistance of the various current paths leading to the surrounding drain electrode 85.

The ring-shaped n ( ⁺ ) region 86 is formed in the device as shown in FIG. 8 as a reference example, and according to the present invention, the ring-shaped region 86 includes all junctions of the device. It has a much higher conductivity than the n ( ⁻ ) epitaxial region 87. The region 86 extends downward from the region directly below the gate oxide 88 and is the end of two conductive channels formed between a ring-shaped p ( ⁺ ) region 89 and a central p ( ⁺ ) region 91. Combine with. The regions 89 and 91 are
Each is located below the ring-shaped source region 81 and the central source region 82.

FIG. 8 also shows that the outer peripheral edge of the p ( ⁺ ) region 89 has a large diameter so that the device can withstand a high reverse voltage.

The n ( ⁺ ) region 95 in FIG. 8 is provided to make good contact with the drain electrode 85.
The drain electrode 85 is considerably distant from the source 81 located inside in the horizontal direction. For example, the distance between them is about 9
It is over 0 micron. A p ( ⁺ ) insulating diffusion portion 96 is provided outside the drain electrode 85 to insulate the element from other elements on the same chip or the wafer.

In the configuration of FIG. 8, sources 81 and 82
Through the region 86 so that the current from the through the epitaxial region 87. The current then flows laterally outward and further to the drain electrode 85. As in the embodiment of FIG. 2, the device resistance is greatly reduced by the highly conductive region 86.

In practicing the configuration of FIG. 8, it should be noted that any contact material can be used to form the source and gate electrodes. For example, aluminum can be used for the source electrode and polysilicon material can be used for conductive gate 80 in FIG. 8 or conductive gate 24 in FIG.

Many other geometries may be used to fabricate the device of the present invention, one of which is a plurality of linear and parallel source elements with a gate disposed therebetween.

Although the source electrodes 22 and 23 have been described as separate electrodes connected to separate conductors in the above description, the source electrodes 22 and 23 are shown in FIG. Polysilicon layer 101 (replaces aluminum) on top of gate oxide 25. This gate electrode is covered by an oxide layer 102, and a conductive layer 103 connects the two sources 22 and 23 together, forming a single source conductor insulated from the gate electrode 101. Connections to the gate electrodes are made at any suitable edge of the wafer.

10 and 11 show the shape of the measurement curve showing that the forward resistance decreases when the MOSFET region 40 is constructed as a highly conductive n ( ⁺ ). In FIG. 10, the device tested has a region 40 having the n ( ⁻ ) resistivity of the epitaxial region. Thus, the forward resistance is higher at different gate biases as shown in FIG.

MOSFET in which region 40 has n ( ⁺ ) conductivity
In the device, the resistance in conduction decreases dramatically as shown in FIG. 11 for all gate voltages before the velocity saturation of electrons occurs.

The polygon structure of the source region of the present invention is shown in FIG.
16 to 16 are best shown.

14 and 15 show the device before the gate, source and drain electrodes are provided. The manufacturing method may be of any type including the above-mentioned method for performing the best formation of the junction and the installation of the electrodes such as the D-MOS manufacturing technology and the ion implantation technology.

Although the device of the present invention is described as an n-channel enhancement type device, the present invention is also applicable to p-channel devices and depletion mode devices.

In FIGS. 14 and 15, hexagonal source regions are formed in the base semiconductor body or wafer. The illustrated base semiconductor or wafer is shown as a silicon single crystal N-type wafer 120 provided with a thin N-epitaxial region 121 as shown in FIG.
All junctions are formed in epitaxial region 121. 14 and 1 by using a suitable mask.
A plurality of P-type regions, such as regions 122 and 123 of 5, are formed on one surface of semiconductor wafer region 121, and these regions are generally polygonal, preferably hexagonal in shape.

A large number of polygonal areas are formed. For example, in an element having a surface dimension of 2.54 mm × 3.556 mm, about 6600 polygonal regions are formed,
The total channel width is about 558.8 mm. The distance dimension between two opposite sides of each of the polygonal regions is about 0.0254 mm or less. In addition, the distance between the linear measuring portions of adjacent polygonal regions is about 0.015 mm. The above dimensions are examples.

The p ( ⁺ ) regions 122 and 123 have a depth d of about 5 microns which is desirable for producing high and reliable field characteristics. Each of the p regions has a p region 122.
And 123 respectively have outer step regions, shown as step regions 124 and 25, respectively, which are about 1.
It has a depth s of 5 microns. This distance should be as small as possible to reduce the capacitance of the device.

Each of the polygonal regions, including polygonal regions 122 and 123, receives N ⁺ polygonal ring regions 126 and 127, respectively. Steps 124 and 125 are located below regions 126 and 127, respectively. N ⁺ area 12
6 and 127 cooperate with the relatively conductive N ⁺ region 128. The region 128 is an N region arranged between adjacent p-type polygons and defines various channels between the source region and a drain electrode described later.

Highly conductive N ⁺ region 128 is described in US Pat.
Formed by the method described in U.S. Pat. No. 376,286, yet this region 128 is the subject of the patent and has a very low forward resistance characteristic of the device.

In FIGS. 14 and 15, the entire surface of the wafer is covered with an oxide layer or combined conventional oxide and nitride layers, which are formed to form various bonds. It This layer is shown as insulating layer 130. The insulating layer 130 includes polygonal regions 122 and 12
Polygonal openings such as three directly above openings 131 and 132 are provided. Openings 131 and 132 partially overlap N ⁺ source rings 126 and 127 for regions 122 and 123, respectively. The insulating layer 130 as an oxide strip that remains after the formation of the polygonal opening becomes the gate oxide of the device.

Then, electrodes are provided as shown in FIG. These are polysilicon electrodes 140, 141, and 14 that overlap the insulating layer (oxide portion) 130 in a grid pattern.
It is 2.

Subsequently, a silicon dioxide film is provided on the polysilicon electrodes 140, 141, 142 of FIG. 16 to provide film parts 145, 146, 147, which are the polysilicon control electrodes and subsequently the entire wafer. It is provided on the upper surface and insulates the source electrode and the like. In FIG. 16, the source electrode is shown as a conductive coating 150 made of a desired material such as aluminum. Drain electrode 151
Is also provided in the element.

The device shown in FIG. 16 has an N-channel type in which a channel region is formed between each independent source and the body of the semiconductor material that finally leads to the drain electrode 151. It is an element. In this way, the channel region 160 is formed between the source region 126 on the ring connected to the source electrode 150 and the N ⁺ region 128 leading to the drain electrode 151. Channel 160 can be converted to N-type conductivity by applying a suitable control voltage to gate 140. Similarly,
The channels 161 and 162 are formed between the source region 126 connected to the source electrode 150 and the surrounding N ⁺ region 128 leading to the drain electrode 151. In this way, when an appropriate control voltage is applied to the gate electrode of polysilicon including the electrode 141 of FIG.
And 162 become conductive, allowing majority carrier conduction from the source electrode 150 to the drain electrode 151.

Each of the sources forms a parallel conductive path, eg, channels 163 and 1 below gate electrode 142.
64 enables conduction from the ring-shaped source region 127 and the N-type source region 170 to the N ⁺ region 128 and the drain electrode 151.

FIGS. 15 and 16 show a p-type edge region 171 that wraps around the edge of the wafer.

The electrode 150 in FIG. 16 is preferably an aluminum electrode. The contact region of the electrode 150 entirely covers and deepens the deeper depth of the p-type region 122. This is done because it was found that the aluminum used for electrode 150 stamped out very thin regions of p-type material (spike through). Thus, one feature of the present invention is that the electrode 150 includes the p regions 122 and 12
3 is a point where the deep portion of the p region is covered with certainty. This allows the active channel region formed by the steps 124 and 125 to have a desired thinness in order to reduce device capacitance.

FIG. 12 shows a multi-completed MOSFET device using the polygonal source pattern of FIG. The device shown in FIG. 12 has an engraved four-sided region 18
It is surrounded by 0, 181, 182, 183. If cut along these areas, 0.25 from the wafer body
A unit element having a size of mm × 0.3556 mm is cut out and separated.

The polygonal region is formed on one wafer in a plurality of rows and columns. For example, the range indicated by the symbol A includes 65 rows of polygons of about 0.210 mm, and the range indicated by the symbol B is about 0.376 m.
In this example, 100 rows of m polygons are included, and 82 rows of the polygonal regions are formed in a range indicated by a symbol C between the source connection pad 190 and the gate connection pad 191. The source pad 190 is made of heavy metal,
It is directly connected to the aluminum source electrode 150, and the conductive wire is connected thereto.

The gate connection pad 191 is electrically connected to a plurality of fingers 192, 193, 194 and 195, which fingers are symmetrically formed on the outer surface having the polygonal area, and are shown in FIG. Electrically connected to the polysilicon gate as described in connection.

At the final stage of the manufacturing process, the outer edge 2 of the device is
A ring-shaped deep P ⁺ diffusion portion 171 connected to the electric field plate 201 shown in FIG. 12 is provided.

FIG. 13 shows a portion of the gate pad 191 and gate fingers 194 and 195 in cross section. To reduce the RC delay constant of the device, it is desirable to form multiple electrodes on the polysilicon gate. The polysilicon gate has a plurality of regions 210, 211, 21.
Has a number of areas, including two, which extend outwards,
In addition, the extension of the gate pad and the gate finger 19
Accept 4 and 195. The polysilicon gate region is exposed during the formation of oxide coating 145-146-147 in FIG. 16 and is not covered by source electrode 50. In FIG. 13, axis 220 is the axis of symmetry 220 shown in FIG.

Although the present invention has been described in relation to the preferred embodiment, it will be apparent to those skilled in the art that numerous variations and modifications can be made. Therefore, the present invention should not be limited solely to the description, drawings, and claims.

[Brief description of drawings]

FIG. 1 is a plan view showing a reference example of a MOSFET device related to the present invention, showing two metal patterns of a source and a gate.

FIG. 2 is a sectional view taken along line 2-2 of FIG.

3 is a cross-sectional view similar to FIG. 2 showing the initial stage of the wafer fabrication of FIGS. 1 and 2, showing in particular the P ⁺ contact implantation and diffusion steps.

FIG. 4 is an explanatory diagram of a second step of the manufacturing process showing the n ( ⁺ ) injection and diffusion steps.

FIG. 5 is an explanatory diagram of a manufacturing process of a channel injection and diffusion process.

FIG. 6 illustrates a source predeposition and diffusion process that is performed prior to the final step in which the gate oxide is cut for the metallization step that forms the device of FIG.

FIG. 7 is a plan view similar to FIG.

8 is a sectional view taken along line 8-8 of FIG.

9 is a sectional view similar to FIG. 2, showing another example of the source contact structure.

FIG. 10 is a forward current characteristic diagram of a device similar to the structure of FIG. 2 in which the region under the oxide is n ( ⁻ ) as a MOSFET device.

11 is a characteristic diagram of the same device as the structure of FIG. 2 in which region 40 has a high n ( ⁺ ) conductivity.

FIG. 12 is a plan view of one MOSFET device formed on a wafer according to the present invention.

FIG. 13 is an enlarged detailed view of the gate pad showing the relationship between the gate electrode and the source region in the gate pad region.

FIG. 14 is a detailed plan view of a small portion of the source region in one step of the device manufacturing process.

15 is a cross-sectional view taken along the line 14-14 of FIG.

16 is a view similar to FIG. 15 in which a polysilicon gate, a source electrode and a drain electrode are attached to a wafer.

[Explanation of symbols]

120 wafer 121 epitaxial region 122 p ( ⁺ ) region (base region) 123 p ( ⁺ ) region (base region) 126 source region 127 source region 128 N ⁺ region (common conductive region) 130 gate oxide layer 140 gate electrode 141 gate Electrode 142 Gate electrode 150 Source electrode 151 Drain electrode 161 Channel 162 channel

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Thomas Harman, Helin Drive, Redondo Beach, California, USA 1622 (72) Inventor Vladimir Lumenic, El Segand, Indiana Court, California, USA 717

Claims (1)

[Claims] 1. A main body portion of a first conductivity type having a first surface and a second surface parallel to the first surface,
A wafer of a semiconductor material, the surface of the main body portion of which constitutes the first surface, and a second conductivity type which is opposite to the first conductivity type. A base region having a polygonal shape and arranged symmetrically at intervals in the main body portion, and extending from the first surface toward the second surface between the base regions adjacent to each other, 1 × 10 A common conductive region having a conductivity corresponding to a phosphorus atom implantation amount of ^{12 to} 1 × 10 ¹⁴ atoms / cm ² ; and the base from the first surface inside the peripheral edge of the first surface of the base region. A source region having a polygonal ring shape made of a material having the first conductivity type and formed between an outer peripheral edge of the source region and the peripheral edge of the base region; Channel in which a 1-conductivity type channel is formed Region, a gate insulating layer extending on the common conductive region and the channel region on the first surface, a gate electrode formed on the gate insulating layer, the source regions and their base regions. A MOSFET device comprising: a connected source electrode; and a drain electrode coupled to the common conductive region.