DE2940699A1 - MOSFET ARRANGEMENT, IN PARTICULAR POWER MOSFET ARRANGEMENT - Google Patents

Description

Patent attorneys Dipl.-Ing. Curt Wallach

α Dipl.-Ing. Günther Koch

2 q / η e ο g Dipl.-Phys. Dr Tino Haibach

Dipl.-Ing. Rainer Feldkamp

D -8000 Munich 2 Kaufingerstraße 8 Telephone (0 89) 24 02 75 Telex 5 29 513 wakai d

ο ,, ™: _t & OCT. 1979

Our reference: 16? 21 H / Nu

International Rectifier Corporation, Los Angeles, CaI., USA

MOSFET arrangement, especially power MOSFET

arrangement

The invention relates generally to MOSFET arrangements and more specifically aims to provide a novel structure for such a device MOSFET device, which its use for power applications with a relatively high reverse voltage and with an extremely low one On resistance permitted. The main advantage of the bipolar transistor compared to the MOSFET transistor is known in that the bipolar transistor has a very low on-resistance per unit conductor area owns. Conversely, the MOSFET transistor has numerous advantages over the bipolar transistor, in particular a very high switching speed, high gain and lack of the appearance of the second breakthrough associated with a minority carrier assembly (secondary breakdown). However, so far was the use

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of the MOSFET transistor for application purposes as a power switch because of its high turn-on voltage limited.

The present invention provides a power MOSPET device created, which has a low on-resistance, whereby the invention MOSFET arrangement will also be more competitive with bipolar arrangements for switch applications while maintaining all of the numerous advantages of the MOSPET over a bipolar arrangement. More specifically, the present invention makes the on-state resistance of the device per unit area µm is reduced by at least a factor of 2 compared to the previously given resistance which limits the applicability per unit area in a conventional MOSFET arrangement.

According to a preferred embodiment of the invention, two sources are on the same surface a semiconductor wafer arranged at a lateral distance from one another. Between the two sources resp. Sources is a gate or gate electrode deposited on a conventional gate or gate oxide. Below the gate or gate, two are spaced apart from one another by an n-type semiconductor body region p-conductor channels arranged. The current flow from each source takes place through the associated channel (after generation the inversion layer defining the channel), such that a majority charge carrier conduction current through the semiconductor base body area and via the plate or the chip to the sink or. Drain electrode flow

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can. The drain or drain electrode can be on the opposite Surface of the plate or on a side opposite the source or source electrodes be arranged offset surface area of the same surface. The manufacture of such a configuration takes place by means of the advantageous manufacturing techniques for D-MOS arrangements, which means precise alignment of the various electrodes and channels and the use of extremely small channel lengths. The above The aforementioned arrangement configuration may already be proposed as such for a MOSFET signal arrangement have been, however, the structure according to the invention does not match the conventionally used signal MOSFET.

The arrangement is essentially produced in an n (-) substrate which has the relatively high specific resistance required to achieve the reverse voltage desired for the arrangement. For example, for a 400 V arrangement, the n (-) region can have a specific resistance of about 20 ohm-cm . However, it is precisely this required high specific resistance that has hitherto caused the MOSFET arrangement to have a relatively high switch-on resistance when used as a power switch.

The invention is based on the fundamental knowledge that in the upper part of the central bulk area, to which the two inversion layers supply current on the way to the drain or drain electrode, the central area immediately below the gate or gate oxide a material with a relatively low specificity

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Resistance can be formed, for example, by an n (+) diffusion in this channel area, without thereby affecting the reverse voltage properties of the arrangement.

According to the basic concept of the invention, this common channel has an upper part below that Gate or gate oxide and a lower bulk part, which is extends in the direction of the drain electrode. The lower part has the to achieve the high resistivity and has a thickness depending on the reverse voltage desired for the arrangement. For example for a 400 V arrangement this lower n (-) range is one About 35 microns deep, while for a 90v arrangement they would be about 8 microns deep can. Depending on the desired reverse voltage of the arrangement, other depths can be selected in order to achieve the Avoid a breakdown under reverse voltage conditions to ensure the required thicker depletion area. The upper part of the common canal will up to a depth of about 3 to about 6 microns, designed to be highly conductive as (η +). It has been found that this does not impair the reverse voltage capability of the arrangement. On the other hand, by this measure the Switch-on resistance of the arrangement per unit area reduced by a factor of more than 2. The arrangement thus obtained becomes competitive with conventional bipolar power switch arrangements as it continues to do so has all the advantages of the MOSFET arrangement over bipolar arrangements, but now more than that also has the relatively low forward resistance,

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which was the main advantage of the bipolar arrangement.

The line MOSgEf arrangement according to the invention is low Forward resistance also enables a very high packing density and can be relatively simple to get old Masks are made. Furthermore, the arrangement has a relatively low capacitive resistance.

According to a preferred embodiment of the invention, the individual can be arranged at a distance from one another Source or source areas have a polygonal or polygonal configuration, preferably a hexagonal configuration, by a constant distance along the main length of those arranged on the semiconductor body surface To ensure source or source areas. There can be an extraordinarily large number of such small hexagonal ones Source elements on the same surface of the semiconductor body for a given arrangement are provided. For example, 6600 hexagonal source regions can be used be formed on a platelet or chip area measuring about 100 χ 140 thousandths of an inch, for generation an effective channel width of about 22,000 inches, which ensures a very high current capacity of the arrangement will.

The space between adjacent source elements can be a polycrystalline silicon gate or gate or any other gate or gate structure, wherein the gate structure over the surface the semiconductor arrangement by means of elongated gate

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or gate X contact finger is contacted, which one ensure good contact over the entire surface of the assembly.

The individual polygonal source or source areas are contacted by a uniform conductor layer, which with the individual polygonal Quellebzw. Source elements through openings in a source or Source areas covering insulating layer in contact stands; the openings can be produced by means of conventional D-MOS light printing processes. Then becomes a pillow-shaped source or source connection area for the source or source connection conductor and a pillow-shaped gate terminal area for the elongated gate fingers, as well a drain connection area on the opposite surface of the semiconductor device.

A variety of such arrangements can be formed in a single die, and the individual ones Elements can be separated from one another by scribe or scratch lines or by any other method be separated.

According to a further feature of the invention, the p-region defining the channel has below the gate oxide or gate oxide a relatively deeply diffused part below the source or Sojrce, in such a way that the p-diffusion region has a large radius of curvature in the n (-) epitaxial layer forming the main body of the device owns. It has been found that this deeper diffused area or this diffused deeper

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Barrier layer brings about an improvement in the voltage gradient at the edge of the arrangement and so the use of the arrangement with higher blocking voltages.

In the following, exemplary embodiments of the invention are described with reference to the drawing; in this show

Fig. 1 is a plan view of a power MOSFET chip or Platelets according to the invention with particular illustration of the metallization patterns for the two source or source areas and the gate or gate area,

Fig. 2 is a sectional view taken along section line 2-2 in Fig. 1,

FIG. 3 in a sectional view corresponding to FIG. 2 an initial process step in the production of the chip according to FIGS. 1 and 2, more precisely the production of the p (+) - contact by implantation and diffusion,

Fig. 4- a second step in the manufacturing process, namely the n (+) - implantation and -Diffusion,

5 shows a further step in the manufacturing process of the chip from FIGS. 1 and 2, namely the canal implantation and diffusion,

6 shows a further step in the production process, namely the pre-separation and diffusion of the

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Source or source area, as the penultimate Step before cutting out the gate or gate oxide for the arrangement according to FIG Metallization,

7 shows the metallization pattern according to FIG a second embodiment of the invention,

Fig. 8 is a sectional view taken along the line 8-8 from Fig. 7 »

8a shows a modified source or source contact configuration in a view corresponding to FIG. 2,

9 shows the course of the forward current characteristics of an arrangement according to FIG. 2, but with the area 40 below the oxide consists of n (-) - material,

10 shows the characteristic curve of an arrangement identical to FIG. 2, the area 40 has high n (+) conductivity,

11 shows a top view of a completed according to the invention Element on a semiconductor die prior to separation of the element from the remainder of the Plattchens,

12 shows an enlarged detailed view of the gate or gate cushion to illustrate the relationship between the gate or gate contact and the source or source polygons in the region of the

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Gate or gate cushions,

Pig. 13 shows a small part of the Source areas in a procedural stage during the creation of the arrangement,

FIG. 14 shows a sectional view of FIG. 13 in a longitudinal section the line 14-14 in Fig. 13,

15 shows a view corresponding to FIG. 14 with an additional view Attachment of a gate made of polycrystalline silicon, a source or Source electrode device and a Senkebzw. Drain electrode on the wafer.

The in Figs. 1 and 2 illustrated MOSFET arrangement according to a first embodiment of the invention has a chip 20 made of monocrystalline silicon (or another suitable material); As best seen in FIG. 1, the electrodes of the array follow a serpentine path 21 to increase the current-carrying area of the array. Other geometries could also be used. The arrangement shown has a reverse voltage of approximately 400 V and an on-resistance of less than 0.4 ohms, with a channel width of 50 cm. Arrangements with blocking voltages of 90 to 400 volts have been made. The 400 V arrangements carried current pulses of 30 A. The 90 V arrangements had on-resistance of about 0.1 ohms with a channel width of 30 cm and carried current

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impulses up to about 100 A. By varying the channel widths accordingly, arrangements with higher and lower voltage.

The currently known MOSFET arrangements have far higher switch-on resistances than those specified above Values. For example, a comparable to that described below according to the invention, However 400 V MOSPET manufactured using conventional methods normally have an on-resistance of substantial greater than about 1.5 ohms compared to the on-resistance of less than about 0.4 ohms in an arrangement produced according to the invention. In addition, a MOSPET switch according to the invention has all the advantageous ones Properties of the MOSFET arrangement, since it works as a majority charge carrier arrangement. With these Advantages include high switching speed, high gain and avoidance of the Minority carrier arrangements given secondary Breakthrough properties.

The arrangement according to Figs. 1 and 2 has two source or source electrodes 22 and 23 which are connected by a metallized gate or gate electrode 24 separated from one another which are attached to the surface of the semiconductor device, but from this through a silicon dioxide layer 25 is separated. The serpentine path formed by gate oxide 24 has a length of 50 cm with 667 turns; it is shown in FIG. 1 only in a simplified form. Other channel widths can be used Find application. The source or source electrodes 22 and 23 can be in the manner shown

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-><- * \ 29A0699

continue laterally and thus serve as field plates, which support the expansion of the depletion area generated under reverse voltage conditions. Either of the two Source electrodes 22 and 23 respectively Current to a common sink or drain electrode 26, which is fixedly arranged on the underside of the plate is. In Fig. 2, the relative dimensions of the assembly, particularly in terms of thickness, are for reasons greatly exaggerated for clarity. The silicon chip or the silicon wafer 20 is on an n (+) substrate which can be about 14 thousandths of an inch thick. An n (-) epitaxial layer is deposited on the substrate 20, the thickness and specific resistance of which depend on the desired reverse voltage. All barrier layers are produced in this epitaxial layer, which can have a relatively high specific resistance. In the embodiment described, the epitaxial layer has a thickness of approximately 35 microns and a resistivity of about 20 ohm-cm. For a 90 volt arrangement, the epitaxial layer 20 would be about 10 microns thick and about 2.5 ohm-cm resistivity. A channel width of 30 cm is also used to achieve the desired current-carrying capacity of the arrangement.

According to a preferred embodiment of the invention, an elongated serpentine p (+) conductivity region is located below each of the source electrodes 22 and 23, which is thus along the line in FIG. 1 The serpentine path shown extends. These p (+) regions are shown in FIG. 2 in the form of p (+) regions 30 and 31, respectively; they correspond to the areas according to the state

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the technique, with the difference that the maximum depth of the p (+) - region is greatly exaggerated, by a large To achieve radius of curvature. This enables the arrangement to withstand higher blocking voltages. For example, areas 30 and 31, respectively, have a depth of preferably about 4 microns at point Σ in FIG. 2 and from about 3 microns at location Y in FIG. 2.

Using D-MOS manufacturing processes below the source or source electrodes 22 and 23, two n (+) - regions 32 and 33 are generated, which together with the p (+) regions 30 and 31, n-channel regions 34 and 35, respectively define. The channel areas 34 and 35 are below the gate or gate oxide 25 and can by suitably applying a bias signal to the gate or Gate 24 can be inverted to conduct current from source 23 and source 22 through the inversion layers in the central area located below the gate 24 and from there to the drain or drain electrode 26. The channels 34 and 35 can each have a length of about 1 micron.

Heretofore it has been considered necessary that the central n (-) region between channels 34 and 35 (and between the ρ (+) regions 30 and 31) have a high specific Must have resistance so that the arrangement can withstand high reverse voltages. However, such an n (-) - material of relatively high resistivity contributes as a decisive factor to the high on-state switch-on distance of the arrangement.

According to the essential basic idea of the invention

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a significant part of this central governance area made relatively highly conductive and for this purpose consists of a "directly under the gate" or Gate oxide 25 arranged n (+) - area 40 «The n (+) - area 40 has a depth of about 4 microns; the depth could range from about 3 microns to about 6 microns lie. Although the exact conductivity is not known and the depth is variable, it is anyway large relative to the underlying n (-) range. Specifically, the area 40 has a high one Conductivity as determined by an ion implantation

12 14

total dose of about 1 χ 10 to 1 χ 10 phosphorus atoms /

ρ
cm at 50 kV and a subsequent diffusion shock at temperatures from II50 to 1250 ° C for 30 minutes to 240 minutes. The invention is based on the knowledge that the implementation of this area 40 as a relatively highly conductive n (+) - material by means of a diffusion or other work process significantly improves the characteristics of the arrangement and the on-state resistance of the arrangement by a factor of more than 2 is decreased. It has also been found that such a highly conductive region 40 does not impair the blocking voltage characteristics of the arrangement. By making the area below the gate or gate oxide 25 and between the channels 34 and 35 more conductive, a considerable reduction in the on-state resistance of the finished device serving as a circuit breaker was achieved, such that the MOSFET Arrangement can compete to a far greater extent with an equivalent barrier arrangement while maintaining all the advantages of the majority carrier mode of operation of the

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MOSFET.

In the previous description of Pigg. 1 and 2 it was assumed that the conduction channels 34 and 35 are made of p (+) material and are therefore inverted to an n conductivity type to provide a majority carrier conduction channel from the sources 22 and 23 to the central region 40 upon application to generate a suitable gate or gate voltage. Of course, however, all of these conductivity types could be reversed such that the arrangement would operate as a p-channel arrangement rather than an η-channel arrangement as described above.

In the Pigg. 3 to 6 is a method for producing the arrangement according to FIGS. 1 and 2 shown. Fig. shows a base plate 20 made of an n (+) material with an n (-) region formed on the top thereof by epitaxial deposition. On the plate 20 a thick oxide layer 50 and in this window openings 5 * 1 and 52 provided. The window openings 51 and are used to create p (+) regions in an ion implanter irradiated with a boron atom S, beam. After that, the implanted boron atoms become too caused deeper diffusion into the platelet, to form the rounded illustrated in FIG p (+) - concentration ranges that can be about 4 microns deep. During this diffusion process Shallow layers of oxide grow over the pensters 51 and 52 53 and 54.

Then, as can be seen from Fig. 4-, in the oxide

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layer 50 window openings 61 and 62 cut and an n (+) implant performed to the n (+) areas

63 and 64 in the n (-) epitaxial layer. This n (+) - implantation can be done with a phosphor beam are executed. The implanted areas are then subjected to a diffusion step such that the areas 63 and 64 extend and to a depth of deepen about 3 1/2 microns, with a concentration

12 which by an implantation dose of 1 χ 10 to

14 2

1 × 10 phosphorus atoms / cm with a subsequent diffusion shock of 30 minutes to 4 hours at temperatures of 1150 to 125O ⁰ CfJ As will be seen below, the areas 63 and 64 form the n (+) area according to the invention, which is the switch-on resistance the arrangement is significantly reduced.

It should be noted that the n (+) regions 63 and

64 can optionally be produced by epitaxial deposition and do not need to be diffused in. Likewise, the finished arrangement described here can be produced by any other desired method with which the person skilled in the art is familiar.

The next process step is illustrated in Figure 5 and is channel implantation and diffusion; In this method step, the ρ (+) regions 71 and 72 are generated, specifically through the same windows 61 and 62 that were used for the n (+) implantation of the regions 63 and 64. The p (+) - regions 71 and 72 are determined by implantation with a boron beam with a dose of 5 × 10 ¹ ^ to 5 × 10 ^ atoms / cm ² with a subsequent diffusion shock over 30 to 120 minutes at *)

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1150 to 125O ⁰ C generated.

Then, as shown in FIG. 6, method steps for source pre-deposition and for diffusing in the source regions 32 and 33 are carried out. This is done by a conventional, non-critical phosphorus diffusion step, with the diffusion occurring through windows 61 and 16 such that the source areas 13 and 33 are automatically aligned relative to the other preformed areas. For this purpose, the platelet is placed in an oven and, for a time of 10 minutes to 50 minutes, at a temperature of 850 to 1000 ^° C. ei:
Exposed to carrier gas.

from 850 to 1000 ⁰ C of a suspension of POCl ₃ . in one

After completion of this process step, the basic barrier layer configuration required according to FIG. 2 is formed, with short p (+) regions arranged below the oxide 50, which serve as the conductive channel for the final finished arrangement, and with one the area between the channels 34 and 35 and between the p (+) areas 30 and 31 filling n (+) area. The manufacturing process is then continued from the state shown in FIG. 6 to the arrangement shown in FIG. 2, in which the oxide surfaces on the top of the chip are removed in a suitable manner in strips and the metallization patterns for contacts 22, 23 and 24 for electrical contacting of the Arrangement are formed. In a subsequent metallization process, the sink or drain contact 26 is applied to the arrangement. Then the entire arrangement can be provided with a suitable passivation coating and feed line

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-yf-

and connecting wires to the source electrodes 22 and 23, respectively as well as being connected to the gate electrode 24. Then the arrangement is in a suitable Protective housing mounted, with the sink or drain electrode on the housing or another, as a sink connection serving conductive support part is attached.

In the arrangement shown in FIGS for the two source areas and the gate or gate areas a serpentine path application and the sink or. Drain electrode is provided on the surface of the wafer opposite the source electrodes. However, other configurations can also be used. The Figg. 7 and 8 illustrate a planar configuration in the form of a simple rectangular order with an annular gate 80 interposed between a first, annular source electrode 81 and a central or middle source electrode 82 is. The arrangement shown in FIG. 8 is contained in a base plate 83 made of monocrystalline p (-) silicon, which may have a hidden, recessed n (+) region 84 to reduce the lateral resistance of the various Current paths of the arrangement, which lead to the laterally offset sink or drainage path surrounding the source 81. Drain electrode 85 lead to decrease.

As illustrated in FIG. 8, an annular n (+) - region 86 is formed in this arrangement, the region 86 according to the invention has a significantly higher conductivity than the n (-) region produced by epitaxial deposition 87, which contains all of the barrier layers of the arrangement. The annular region 86 extends from the

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Area below the gate or gate oxide 88 and adjoins the ends of the two conductor channels, which between the annular p (+) - area 89 and the central p (+) arranged below the annular source 81 and the central source 82 Area 91 are formed.

From Fig. 8 it can also be seen that the outer circumference 90 of the p (+) - Hing 89 has a large radius in order to increase the resistance to support the arrangement against high reverse voltages.

To ensure good contact with the sink or Drain electrode 85 is an n (+) region 95 in FIG. intended. The drain electrode 85 is through separated from the source 81 by a wide lateral distance (greater than about 90 microns). The sink or drain contact 85 is to isolate the assembly from other assemblies provided on the same chip, die, or die surrounded by a p (+) - insulating diffusion region 96.

In the arrangement according to FIG. 8, as in the arrangement according to FIG. 2, the current flow from the sources 81 and across the width of epitaxial region 87 through the region 86. From there the current flows laterally outwards and then upwards to the sink or drain contact 85. As in the embodiment of FIG. 2, the resistance is the arrangement by the relatively highly conductive area 86 is greatly reduced.

For the practical implementation of the invention it should be pointed out that for the production of the source and gate

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Contacts any contact material can be used. For example, the source could be electrodes Aluminum and for the conductive gate 80 in Fig. 8 and the conductive gate 24 in Fig. 2, respectively, polycrystalline silicon material be used.

Numerous other geometries can be used to manufacture the assembly of the present invention, including a plurality of pairs of rectilinear, parallel source elements with respective ones disposed therebetween Gates and the like.

The source electrodes 22 and 23 were used as separate Electrodes shown, which can be connected to separate leads. Of course they could Sources 22 and 23, however, can also be connected directly to one another, as illustrated in FIG. 8a, in which corresponding Components are denoted by the same reference numerals as in FIG. However, in Fig. 8a is the gate electrode a polycrystalline deposited on the gate oxide 25 Silicon layer 101 (instead of aluminum). The gate or gate 25 is then covered with an oxide layer 102 and a conductor layer 103 connects the two Sources 22 and 23 together to form a single source conductor isolated from port 101. The connection connection to the goal can be done on a suitable hand area of the flap.

In Figs. 9 and 10 the course of measurement curves is shown, which is the achievable reduction in forward resistance illustrate when region 40 is made of highly conductive (n +) according to the invention.

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In Pig. 9, the arrangement examined had a region 40 with the specific resistance of the n (-) - material of the Epitaxial area. The forward resistance therefore has a characteristically high value, as in Fig. 9 for various Gate biases shown.

In the arrangement according to the invention, in which the region 40 is formed with n (+) conductivity, occurs shows a dramatic decrease in on-resistance, as in Figure 10, for all gate voltages prior to occurrence a velocity saturation of the electrons.

An embodiment of the invention with a polygonal configuration of the source areas is best shown in FIGS. 13th to 15 can be seen, which will now be described first.

The Figg. 13 and 14- show the arrangement before application the gate, source and drain electrodes. Manufacture can be by any method, including the previously described D-MOS fabrication process and ion implantation processes for most conveniently creating the barrier layer and attaching the electrodes.

The arrangement is called an N-channel enhancement type arrangement described. Of course, however, the invention is also suitable for P-channel arrangements and those of the impoverishment type.

The arrangement according to Figs. 13 and 14 has a

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Plurality of polygonal source regions on one surface of the device, and although these polygonal regions are preferably seclmeckfoxmig. Other Itoragebungen, vie for example, rectangular or square, could be applied, however, the Hexa ensured gonalf oru uniform distances between the embrace of neighboring source regions.

According to the Figg. 13 and 14, the hexagonal source regions are formed in a semiconductor body or wafers, which may be a H-plate 120 made of monocrystalline silicon, on which a thin N Expitaxialbereich is deposited 121, as best - (-) can be seen from FIG. 14. All of the barrier layers are formed in the epitaxial region 121. By means of suitable masks, a large number of P-regions in the manner of regions 122 and 123 in FIGS. 13 and 14, these regions having a generally polygonal, and preferably hexagonal, configuration.

A very large number of such polygonal areas are generated. For example, in an arrangement with surface dimensions of 100 χ 140 thousandths of an inch, approximately 6600 polygonal areas formed, creating a total channel width of about 22,000 thousandths of an inch. Each of these polygonal areas can each have one in Direction measured perpendicular to two opposite sides of the polygon - width of about 1 thousandth Own inches or less. The areas are about 0.6 thousandths of an inch apart, measured in the direction perpendicular between neighboring

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straight sides of neighboring polygonal areas.

The P (+) regions 122 and 123 have a depth d of preferably about 5 microns for high, reliable field strength characteristics. Each of the P areas each has an outer shelf area, i. H. an area of shallower depth, in the form of the shelf areas 124 and 125 for P-regions 122 and 123, respectively, with a depth s of about 1.5 microns. This depth should be as possible be small in order to reduce the capacitive resistance of the arrangement.

The individual polygonal areas including the polygonal areas 122 and 123 are each given N (+) polygonal ring areas 126 and 127. The shelf areas 124 and 125 are located below these areas 126 and 127 · These N (+) regions 126 and 127 act with a relatively conductive N (+) region 128; H. that between neighboring P-polygons arranged N (+) - area, together in the sense that they are the different channels between define the source areas and a sink or drain contact described below.

The highly conductive N (+) regions 128 are described above for the previous exemplary embodiments Manner and result in a very low on-resistance for the device.

From the Pigg. 13 and 14 it can be seen that the entire Surface of the platelet with an oxide layer or a combination of conventional oxide and nitride layers is coated leading to the formation of the various

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Barriers are generated. This layer is shown in the form of the insulating layer 130. The insulating layer 130 has polygonal openings in the manner of the openings 131 and 132 immediately above the polygonal areas 122 and 123. The limits of the openings I31 and 132 overlie the N (+) source ring regions 126 and 127 for the areas 122 and 123, respectively. The remaining after the production of the polygonal openings Oxide strips 130 define the gate oxide for the array.

Then, as illustrated in FIG. 15, electrodes be applied to the arrangement. These electrodes comprise a mesh or grid made of polycrystalline silicon, with sections overlying the oxide sections 130 140, 141 and 142 made of polycrystalline silicon.

A silicon oxide coating is then deposited on the polysilicon grid 140; this coating is represented in Figure 15 by coating portions 145, 146 and 147 which isolate the polysilicon control electrode and the subsequently deposited source electrode over the entire top surface of the die. This source electrode is illustrated in FIG. 15 in the form of a conductive coating 150 which can be made of any material such as aluminum . Furthermore, a drain electrode 151 is also applied to the arrangement.

The arrangement thus obtained as shown in FIG. 15 is an arrangement of the N-channel type in which each channel region

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between the individual sources and the main body are formed from the semiconductor material, which eventually becomes the drain electrode 151 leads. In detail is a channel area 160 between the source and Source electrode I50 connected ring-shaped source or. Source area 126 and ultimately with the Senkebzw. N (+) region 128 connected to drain electrode I51. The channel 160 is when a suitable Control voltage to the gate or gate 140 in N conductivity inverted. Correspondingly, there are channels 161 and 162 between the source or source region 126 connected to the conductor I50 and that to the drain or drain electrode 151 leading surrounding N (+) region 128 is formed. When applying a suitable control voltage to the gate or Polycrystalline silicon gates (including pinger 141 in FIG. 15) become channels 161 and 162 conductive and allow a majority charge carrier line from the source or source electrode 150 to Senkebzw. Drain electrode I51.

The individual source regions form parallel conductor paths, with channels 163 and 164 under the gate or gate element 142, for example, a charge carrier line from the source or source ring 127 and an N source or source strip 170 to the N (+) region 128 and from there to the sink or drain electrode I5I ensure

In the representation of Fig. 14 and 15, an end-side F region 171 is illustrated, which extends the edge of the Enclosing plate.

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- S3

Contact 150 in Figure 15 is preferably an aluminum contact. As can be seen, the contact area for contact 150 lies entirely over the deeper part of P-region 122 and in alignment with this lower region. This arrangement was made as it surrendered has that aluminum used for electrode I50 very thin areas of the P-material could penetrate like spikes. An essential feature of the invention is therefore to ensure that the contact 150 is basically over the deeper parts of the P-regions, according to the type of P-areas 122 and 123 ». This measure then allows that by the annular Shallower shelf areas 124 and 125 defined active channel areas can be as thin as essential Reducing the capacitance of the arrangement is desirable.

Pig. Figure 11 illustrates a fully completed assembly using the polygonal or polygonal pattern for the source or source areas according to Pig. 15 · The complete arrangement illustrated in FIG lies within the tear or scratch areas 180, 181, 182 and 183, by means of which a plurality of such one-piece assemblies, each 100-140 thousandths of an inch in size, from the body of the semiconductor wafer can be broken out.

The described polygonal or polygonal areas are arranged in a large number of rows and columns. For example the dimension A of about 83 thousandths of an inch accounts for 65 columns of such polygonal or Polygonal areas. The dimension B of about 148 thousandths

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can contain, for example, 100 lines of such polygonal or polygonal areas. On the dimension C between source pad 190 and gate pad 191 may be 82 rows of Polygon or polygon elements are omitted.

The source- or source terminal pad 190 is a relatively heavy metal section which directly with the aluminum source-or -source electrode 150 is connected and enables convenient connection link to the source or source.

Gate pad 191 is electrical with a plurality of elongated fingers 192, 193, 194 and 195 connected, which is symmetrical over the outer surface of the polygonal or polygonal areas containing Extend the surface area and establish the electrical connection to the polysilicon gate or gate, as will be described with reference to FIG.

Finally, the outer circumference of the arrangement contains the deep P (+) diffusion ring 171, which is marked with one shown in FIG. 11 illustrated field plate 201 can be connected.

In Fig. 12, portions of the gate pad 191 and the gate fingers 194 and 195 are shown. To the Reducing the RC delay constant of the arrangement, it is desirable to have a plurality of contacts to the Manufacture polysilicon gate or gates. The polysilicon gate or gate has several areas of the type Areas 210, 211, 212, etc., which extend outward and extensions of the gate cushion and the

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Record gate or gate cushion members 194 and 195. the Polysilicon gate areas can be used in the manufacture of the oxide coating 145-146-147 in Pig. 15 remain exposed and are not used with the source or Source electrode 50 covered. It should be noted that there is located at axis 220 in Pig. 12 to those in Pig. The axis of symmetry 220 shown in FIG. 11 acts.

The invention has been described above on the basis of preferred exemplary embodiments, which, however, are self-evident can be modified in manifold Veise without thereby departing from the scope of the invention.

Patent claims:

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Claims (1)

Patent attorneys Dipl .-! Ng. Curl gelding Dipl .-! Ng. Qür.ther Koch Dipl.-Phys. Dr Tino Haibach Dipl.-Ing. Rainer Feldkamp D-8000 Munich 2 ■ KaufingerstraBe 8 - Telephone (0 89) 24 02 75 · Telex 5 29 513 wakai d Date: * OCT. 1979 Our reference: 16721 H / Bu Patent claims: MOSFET arrangement, in particular a power MOSFET arrangement, comprising a plate made of semiconductor material with two parallel surfaces, which has two source electrodes at a distance from one another on one surface, one between the two source electrodes Has a gate or gate insulating layer and a gate or gate electrode arranged on this insulating layer and a drain or drain electrode on the second surface; two directly under the gate or Gate insulating layer spaced apart channels of a first conductivity type, which at their opposite ends are electrically connected to the two source or. Source electrodes are connected, the adjacent ends of the two channels each being connected to a common area of the second conductivity type arranged centrally below the insulating layer and below the two channels and the common area a continuously connected area of a relatively high specific resistance of the second Conductivity type is provided, characterized in that to achieve a relatively low switch-on resistance with a relatively high breakdown voltage, the common area ( ¹ ^ O, Fig. 1 to 6) has a significantly higher conductivity (n (+)) than the said below the two Channels (3 ^, 35) and the common area (40) underneath- 030017 / 076B area (n (-)), and that the common area (40, n (+)) and the area below (n (-)) in series with each other in the current path from the two source or Source electrodes (22,32 or 23,33) to the Senkebzw. Drain electrode (26) lie. 2. Arrangement according to claim 1, characterized in that that from the drain or drain electrode (26) to the one under the two conductivity channels and the common A semiconductor body region (20) of the second conductivity type, which has a significantly higher conductivity (n (+)) than that Area (n (-)) below the channels and the common area. 3. Arrangement according to claim 2, characterized in that that the area (n (-)) under the two channels (3 * 1.35) and the common area (* J0) has one the semiconductor body region (20) grown epitaxial layer. 4. Arrangement according to one or more of the preceding claims, characterized in that in the semiconductor wafer below the two source or Source electrodes (22,23) have two terminal connection regions (32,33) of relatively high conductivity (n (+)) from the second Conductivity type are provided, which extend under the gate or gate insulating layer (25) and a connection with the adjacent ends (3 * 1.35) of the two channels. 5. Arrangement according to one or more of the preceding claims, characterized in that the gate insulating layer (25) is made of silicon dioxide consists. 030017/0765 COPY P 29 ¹ JO 699.3 AFTERCERCICHT 6. Arrangement according to one or more of the preceding claims, characterized in that the two source or source electrodes (22,23) and the gate or Oate electrode (2 ² O with an elongated configuration along a path ( 21) are formed on the first surface of the semiconductor die. 7. Arrangement according to one or more of the preceding claims, characterized in that the two channels (3 ^, 35) correspond to the surface parts relatively deep regions (30,31) of the first conductivity type (p (+)) are and that each of these are relative deep areas (30,31), each with a rounded profile has, which is below and laterally offset from the outer edge of the relevant deep area (30 or 3D aligned source or source area (22 or 23) extends. 8. MOSFET arrangement, in particular MOSFET power arrangement, with low switch-on resistance, pe characterized by an inversion channel, which at its one End with a source electrode and at its other end with an area of high conductivity from en tr er en r, e set ge conductivity type as connected to the inversion channel this region of high conductivity with a semiconductor body region of the same conductivity type, but of lower conductivity, and ultimately one with this semiconductor body region Sink or drain electrode is electrically connected. 9. MOSPET arrangement, in particular MOSFET power arrangement, for production in D-MOS technology, consisting of a semiconductor chip bew.-platelets, daa on its one upper 030017/0785 COPY surface two elongated source or source electrodes (22, 23, Fig. 1 to 6, 8a; 81,82, Fig. 7,8) as well as one between the two source or source electrodes on one on the Semiconductor chip or wafer provided insulating layer (25; 88) arranged gate or gate electrode (24; 101); two channels (3 ^, 35; 89j91) which can be inverted by a gate or gate bias voltage with one another spaced ends that extend into a common semiconductor area (^ 0; 86) below the gate or Gate insulating layer (25; 88) extend while the opposite Ends of the two channels are connected to the two source or source electrodes, wherein the two channels (30.3 * 1 and 31.35; 89.91) are of a first conductivity type and a second conductivity type are invertible and wherein the common semiconductor region has a current path across the thickness of the semiconductor chip or chip, characterized in that the semiconductor chip or the semiconductor chip in its near-surface area (4θ; 86) has a high conductivity and in one Depth greater than about 1 micron below the surface to provide reverse voltage strength required low conductivity, so that by the highly conductive area (40j86) of the common Semiconductor region, the switch-on resistance of the arrangement is significantly reduced. 10. Arrangement according to claim 9, characterized in that that the sink or drain electrode (26) is connected to the underside of the semiconductor die or chip is. 11. Arrangement according to claim 9 or 10, characterized in that - 030017/07 * 8 indicates that the two channels (3 ¹ I, 35) are the end parts of corresponding relatively deep regions (30,31; 89,91) which extend away from one another and have large radii of curvature (X, Fig. 2) on their outer sides. 12. MOSFET arrangement, in particular a power MOSFET arrangement made of a plate made of semiconductor material with two surfaces parallel to one another, characterized in that on the first plate surface a plurality of equally spaced symmetrically arranged polygonal or polygonal source areas (126, 127, Fig 12 to 15) as well as a gate or gate insulating layer (130) between the source or source regions and on this a gate or gate electrode (140, 141, 142) and on the second plate or. A drain electrode (151) are arranged on the chip surface; that with the polygonal or polygonal source or source regions (126,127) Quellebzw. Source electrode devices (150, Figs. 15 and 11) are connected; that in each case around the outer circumference of each of the polygonal or polygonal source or source regions (126,127) and below the Gate insulating layer (130) an annular channel device (160, 16, 162, 163, 164) from a first Conductivity type is provided, the Kanalvorrich-. at one end each electrically with the Source electrode device (150) and the opposite end with corresponding centrally below the gate or gate insulating layer (130) arranged regions (128) of the second conductivity type connected are; that below the common area (128) and continuously contiguous with this one area (121) of relatively high resistivity 030017 / 07ΘΒ RECEIVED j _ c _ centrally below the Tor-IsoliJ ^ Often arranged of the second conductivity type (N (-)), the common area (128) having a significantly higher conductivity (N (O) than the area below (121) and the common area (128) and the area below (121) in series with one another in the current path from the source electrode devices (150) su the sink or drain electrode (151). 13. Arrangement according to claim 12, characterized in that the source or source regions 126,127) are hexagonal. 14 · Arrangement according to claim 12 or 13 »thereby g e - from the k β η η ζ ei cch net that the / polygonal resp. , _, _,. _A. _ delimited Beneicha angular source or source BerelcneVjeweiiS a have a deep central region (122,123) and a relatively flat-shallow outer region (124,125), wherein the relatively deep central region lies below the source or source electrode devices (150). 15 MOSFET arrangement, especially power MOSFET arrangement, for production in D-NOS technology, consisting of a Semiconductor chip or wafer (120, Fig. 11 to 15), which on its one surface a plurality of symmetrical arranged, polygonal or polygonal source or. Source areas (126,127) and with source or source electrode regions (150) connected to them, as well as one in each case in the distances between the Has source or source regions arranged on an insulating layer (130) provided on the upper side of the plate, gate or oate electrode (140,141,142); furthermore two in each case between the adjacent sides of the individual source or source regions (126, 127), which can be inverted by a gate or gate bias voltage. 030 01 77.0 * 706 ORIGINAL INSPECTED stood ends, each in common semiconductor body areas (128) extend below the gate or gate insulating layer (I30), while the opposite Ends of the two channels are connected to the respective source or source electrode devices (150), wherein these respective two channels are of a first conductivity type and into a second conductivity type are invertible and wherein the common semiconductor region has a current path across the thickness of the semiconductor die or chips, characterized in that the semiconductor wafer or the Semiconductor chip (120) has high conductivity (N (+)) in its near-surface area (128) and at a depth greater than about 1 micron below the surface, that required to ensure reverse voltage strength low conductivity (n (-)) (121), so that by the highly conductive area (128) of the common Semiconductor region, the switch-on resistance of the arrangement is significantly reduced. 16. The arrangement according to claim 15 j, characterized in that the sink or D ^ ain electrode (151, Fig. 15) is connected to the underside of the semiconductor die or chip (120). 17. Arrangement according to claim 15 or 16, characterized in that the two channels (16O, 161} 162, 163,164) are the end parts of corresponding relatively deep regions (122,123) which extend away from one another and have large outer radii of curvature. 18. The arrangement according to one or more of claims 15 to 17, characterized in that the 030017/0711 Source regions (126,127) are hexagonal . 19. Arrangement according to one or more of the preceding claims 12 to 18, characterized in that they are more than about 1000 polygonal or polygonal Has source regions, each of which is approximately one-thousandth of an inch wide. 030017 / 07Θ6