CN111816694B - Superjunction semiconductor device and method for manufacturing superjunction semiconductor device - Google Patents
Superjunction semiconductor device and method for manufacturing superjunction semiconductor device Download PDFInfo
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- CN111816694B CN111816694B CN202010107098.6A CN202010107098A CN111816694B CN 111816694 B CN111816694 B CN 111816694B CN 202010107098 A CN202010107098 A CN 202010107098A CN 111816694 B CN111816694 B CN 111816694B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/63—Vertical IGFETs
- H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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Description
Technical Field
The present invention relates to a superjunction semiconductor device and a method for manufacturing the superjunction semiconductor device.
Background
In a normal n-channel vertical MOSFET (Metal Oxide Semiconductor FIELD EFFECT Transistor: insulated gate field effect Transistor), an n-type conductive layer (drift layer) is a semiconductor layer having the highest resistance among a plurality of semiconductor layers formed in a semiconductor substrate. The resistance of the n-type drift layer has a great influence on the on-state resistance of the entire vertical MOSFET. The on-resistance of the entire vertical MOSFET can be reduced by thinning the thickness of the n-type drift layer and shortening the current path.
However, the vertical MOSFET has a function of maintaining withstand voltage by expanding a depletion layer to an n-type drift layer of high resistance in an off state. Therefore, when the n-type drift layer is thinned to reduce on-resistance, the extension distance of the depletion layer in the off-state is shortened, and thus the breakdown field strength is easily achieved at a low applied voltage, and the breakdown voltage is reduced. On the other hand, in order to improve the withstand voltage of the vertical MOSFET, it is necessary to increase the thickness of the n-type drift layer and increase the on-resistance. Such a relationship between on-resistance and withstand voltage is referred to as a trade-off relationship, and it is generally difficult to improve both of them in the trade-off relationship. The trade-off relationship between on-state resistance and withstand voltage is known to be similarly true in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistor: insulated gate bipolar transistors), bipolar transistors, and diodes.
As a structure of a semiconductor device that solves the above-described problems, a Super Junction (SJ) structure is known. For example, a MOSFET having a superjunction structure (hereinafter, referred to as SJ-MOSFET) is known. Fig. 19 is a sectional view showing the structure of a conventional SJ-MOSFET.
As shown in fig. 19, the SJ-MOSFET150 is made of a wafer obtained by growing an n-type drift layer 102 on an n + -type semiconductor substrate 101 having a high impurity concentration. A p-type column region 104 extending from the wafer surface through the n-type drift layer 102 to the n + -type semiconductor substrate 101 is provided.
The n-type drift layer 102 has a parallel structure (hereinafter referred to as a parallel pn region) in which p-type regions (p-type column regions 104) and n-type regions (portions of the n-type drift layer 102 sandwiched between adjacent p-type column regions 104) extending in a direction perpendicular to the substrate main surface and having a narrow width in a plane parallel to the substrate main surface are alternately and repeatedly arranged in a plane parallel to the substrate main surface. The p-type column region 104 and the n-type column region 103 constituting the parallel pn region are regions in which the impurity concentration is increased corresponding to the n-type drift layer 102. By making the impurity concentrations included in the p-type column region 104 and the n-type column region 103 substantially equal in the parallel pn region, an undoped layer can be similarly generated in the off state, and a high withstand voltage can be achieved.
A p-type base region 105 is provided on the parallel pn region of the SJ-MOSFET150 on the side of the active region 130 where the element is formed and current flows in the on state. An n + -type source region 106 is provided inside the p-type base region 105. Further, a gate insulating film 107 is provided so as to cover the surfaces of the p-type base region 105 and the n-type column region 103. On the surface of the gate insulating film 107, a gate electrode 108 is provided, and an insulating film 113 is provided so as to cover the gate electrode 108. In addition, an active electrode 110 is provided on the n + -type source region 106, and a drain electrode 114 is provided on the back surface of the n + -type semiconductor substrate 101.
In the edge termination region 140 surrounding the active region 130 of the SJ-MOSFET150, a parallel pn region and an insulating film 113 are provided in the n-type drift layer 102 in the same manner as the active region 130, and a drain electrode 114 is provided on the back surface of the n + -type semiconductor substrate 101.
In the power semiconductor element, the edge termination region 140 must also be kept voltage-resistant, as in the active region 130. In the edge termination region 140, a field plate, a reduced surface electric field (RESURF), a guard ring, and the like are formed in order to obtain a high withstand voltage, as a known technique. Fig. 19 shows a SJ-MOSFET150 with a reduced surface electric field structure. In the SJ-MOSFET150, the electric field concentration in the edge termination region 140 can be relaxed by partially or completely depleting the reduced surface electric field region 117 while maintaining the withstand voltage. In addition, the reduced surface electric field region 117 may be connected to the parallel pn region. In this case, the depletion layer spreads from the junction of the parallel pn regions connected to the reduced surface electric field region 117, and the drift layer is completely depleted at a low voltage. As the voltage increases, the parallel pn regions act as guard rings, the depletion layers further spread from the adjacent parallel pn regions, and the depletion layers combine with each other to form a depletion layer at the time of complete depletion, thereby ensuring high withstand voltage.
For example, a semiconductor device is known in which an n-type pillar layer 2 and a p-type pillar layer 3 are provided in an element portion, an n-type pillar layer 10 and a p-type pillar layer 11 are provided in an element terminal portion, a high-resistance n - -type layer 12 is provided on upper surfaces of the n-type pillar layer 10 and the p-type pillar layer 11 in the element terminal portion, an outermost p-type pillar layer 14 is provided between the n-type pillar layer 2 and the high-resistance n-type layer 12 in the element portion, a p-type base layer 4 is provided at a boundary between the element portion and the element terminal portion, and a RESURF layer 13 is provided adjacent to the p-type base layer 4 (see patent document 1 below).
In an SJ-MOSFET having a repetition pitch P2 of the second parallel pn layer 15 at the peripheral edge portion 3 of the element smaller than a repetition pitch P1 of the first parallel pn layer 12 at the central portion of the element active portion 1, a P-base region 5 is provided so as to extend over the boundary between the first parallel pn layer 12 and the second parallel pn layer 15, a n - surface region 19 surrounding the first parallel pn layer 12 is provided between the second parallel pn layer 15 and the first main surface, and two or more P-type guard ring regions 20 are provided separately from each other on the first main surface side of the n - surface region 19, in a semiconductor device (for example, refer to patent document 2 below).
In addition, a semiconductor device is known in which the p-type column region 6 of the peripheral region 120 is in contact with the p-type connection region 17, the p-type connection region 17 is in ohmic contact with the source electrode 10 via the body region 5', an n-type depletion semiconductor region 18 is provided between the p-type connection region 17 and the first main surface 101, and the doping concentration of the n-type depletion semiconductor region 18 is higher than the doping concentration of the low-doped semiconductor region 2 between the terminal end of the pn column and the field stop region 8 provided at the outermost periphery (see, for example, patent document 3 below).
Prior art literature
Patent literature
Patent document 1 Japanese patent laid-open No. 2006-5275
Patent document 2 Japanese patent application laid-open No. 2013-149761
Patent document 3 U.S. Pat. No. 9281392
Disclosure of Invention
Technical problem
In the parallel pn region, when the impurity amount of the n-type column region 103 is substantially equal to the impurity amount of the p-type column region 104 (a state where the charge balance is "1"), the breakdown voltage of the SJ-MOSFET150 is the maximum. However, the impurity amount of the parallel pn region is liable to vary due to manufacturing variations of the semiconductor device. This causes unbalance of charge balance, and the breakdown voltage is liable to decrease. Further, the breakdown voltage is more likely to be lowered due to the addition of the deviation of the impurity amount and the diffusion depth of the impurities which lower the surface electric field region 117. This causes a problem that a monomer having a low element withstand voltage is likely to be generated.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a superjunction semiconductor device and a method for manufacturing the superjunction semiconductor device capable of suppressing a decrease in withstand voltage due to manufacturing variations.
Technical proposal
In order to solve the above problems and achieve the object of the present invention, a superjunction semiconductor device of the present invention has the following features. The super junction semiconductor device has a terminal structure portion and an active region through which a current flows, wherein the terminal structure portion is disposed outside the active region and has a voltage-resistant structure surrounding the periphery of the active region. A first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of the semiconductor substrate of the first conductivity type. A first parallel pn structure in which first pillars of a first conductivity type and second pillars of a second conductivity type are alternately arranged repeatedly in a plane parallel to the front surface of the first semiconductor layer is provided in the active region. On the upper surface of the first semiconductor layer, a second parallel pn structure in which a third column of the first conductivity type and a fourth column of the second conductivity type are alternately arranged in a plane parallel to the front surface is provided in the terminal structure portion. A first semiconductor region of a second conductivity type including a plurality of regions separated from each other is provided on a surface of the second parallel pn structure of the terminal structure portion. A second semiconductor region of a second conductivity type is provided on a surface of a second column of the second conductivity type of the first parallel pn structure of the active region. A third semiconductor region of the first conductivity type is selectively provided on a surface layer of the second semiconductor region on the opposite side of the semiconductor substrate side. A gate insulating film is provided in contact with the second semiconductor region. A gate electrode is provided on a surface of the gate insulating film opposite to a surface of the gate insulating film in contact with the second semiconductor region.
In the super junction semiconductor device according to the present invention, the first semiconductor region includes a first region on the active region side and a second region separated from the first region.
In the super junction semiconductor device according to the present invention, in the above-described invention, a ratio of a width of the first region to a width of the second region in the first region and the second region of the first semiconductor region is 3:7 to 5:5.
In the super junction semiconductor device according to the present invention, the first region and the second region of the first semiconductor region have a ring-like planar shape.
In the super junction semiconductor device according to the present invention, the width of the first column of the first parallel pn structure of the active region is larger than the width of the third column of the second parallel pn structure of the terminal structure, and the width of the second column of the first parallel pn structure of the active region is larger than the width of the fourth column of the second parallel pn structure of the terminal structure.
In the super junction semiconductor device according to the present invention, the first semiconductor region includes a third semiconductor region of the first conductivity type on a surface of the first semiconductor region opposite to the semiconductor substrate.
In order to solve the above-described problems, an object of the present invention is to provide a method for manufacturing a superjunction semiconductor device having a terminal structure portion and an active region through which a current flows, wherein the terminal structure portion is disposed outside the active region and has a pressure-resistant structure surrounding the periphery of the active region. First, a first step of forming a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate on the front surface of the semiconductor substrate of the first conductivity type is performed. Next, a second step of forming a first parallel pn structure in the active region of the first semiconductor layer, and forming a second parallel pn structure in the terminal structure portion of the first semiconductor layer, wherein the first parallel pn structure is a structure in which first pillars of a first conductivity type and second pillars of a second conductivity type are alternately arranged repeatedly in a plane parallel to the front surface, and the second parallel pn structure is a structure in which third pillars of the first conductivity type and fourth pillars of the second conductivity type are alternately arranged repeatedly in a plane parallel to the front surface. Next, a third step of forming the first parallel pn structure on the surface of the first parallel pn structure in the active region, and forming a second conductive type first semiconductor region including a plurality of regions separated from each other on the surface of the second parallel pn structure in the terminal structure portion. Then, a fourth step of forming a second semiconductor region of a second conductivity type on a surface of the second column of the first parallel pn structure of the active region is performed. Next, a fifth step of selectively forming a third semiconductor region of the first conductivity type on a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate side is performed. Next, a sixth step of forming a gate insulating film in contact with the second semiconductor region is performed. Next, a seventh step of forming a gate electrode on a surface of the gate insulating film opposite to a surface of the gate insulating film in contact with the second semiconductor region is performed.
In the method for manufacturing a superjunction semiconductor device according to the present invention, in the third step, the first parallel pn structure and the first semiconductor region are simultaneously formed by epitaxial growth and ion implantation.
In the method for manufacturing a superjunction semiconductor device according to the present invention, the opening width of the ion-implanted photoresist in forming the second parallel pn structure is larger than the opening width of the ion-implanted photoresist in forming the first semiconductor region.
In the method for manufacturing a superjunction semiconductor device according to the present invention, in the third step, an impurity is implanted into a plurality of portions by ion implantation, and the implanted impurity is thermally diffused, thereby forming the first semiconductor region.
In the super junction semiconductor device according to the present invention, the first semiconductor region includes a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region.
In the super junction semiconductor device according to the present invention, the width w1 of the first region, the width w2 of the second region, the width w3 of the third region, and the width w4 of the fourth region satisfy w 1. Ltoreq.w2. Ltoreq.w3.ltoreq.w4.
In the super junction semiconductor device according to the present invention, the first region, the second region, the third region, and the fourth region are connected to an electrode provided in the terminal structure portion via the second semiconductor region.
In the super junction semiconductor device according to the present invention, the second parallel pn structure has an inner structure on the active region side and an outer structure farther from the active region than the inner structure, and a length of the fourth pillar of the outer structure from the upper surface of the first semiconductor layer is equal to or shorter than a length of the fourth pillar of the inner structure from the upper surface of the first semiconductor layer.
In the super junction semiconductor device according to the present invention, in the above-described invention, the impurity concentration is higher as one of the first region, the second region, the third region, and the fourth region approaches the active region.
In the super junction semiconductor device according to the present invention, one of the first region, the second region, the third region, and the fourth region includes a first portion close to the active region, a second portion further from the active region than the first portion, and a third portion further from the active region than the second portion, and the impurity concentration D1 of the first portion, the impurity concentration D2 of the second portion, and the impurity concentration D3 of the third portion satisfy d1:d2=1.5:1 to 1.2:1, and d2:d3=1:0.75 to 1:0.5.
In the super junction semiconductor device according to the present invention, the distance d1 from the depth to the surface of the first portion, the distance d2 from the depth to the surface of the second portion, and the distance d3 from the depth to the surface of the third portion satisfy d1> d2> d3, starting from the depth from the upper surface of the first semiconductor layer to the center of the first semiconductor region.
According to the above invention, the reduced surface electric field region (first semiconductor region of the second conductivity type) is divided into two or more. This can buffer the reduced surface electric field region near the cut-off electrode, and alleviate the rapid decrease in withstand voltage. Therefore, the pressure resistance caused by manufacturing variation can be suppressed from decreasing. In addition, when charges are accumulated on the protective film, the movement of the equipotential lines is stopped at a position where the surface electric field region is divided, and the influence of the charges is localized. Therefore, voltage withstand variation in the case where charges are accumulated on the protective film of the semiconductor device can be suppressed.
Further, since the movement of the equipotential lines is stopped at the position where the reduced surface electric field region is divided, the reduced surface electric field region is divided into four regions, so that the influence of the electric charges can be localized more than the case where the reduced surface electric field region is divided into two regions, and the withstand voltage fluctuation in the case where the electric charges are accumulated on the protective film of the semiconductor device can be suppressed more. Further, by providing the reduced surface electric field region in such a shape that the width thereof decreases and the impurity concentration thereof decreases as it goes outside the element, it is possible to further suppress withstand voltage fluctuation in the case where charges are accumulated on the protective film of the semiconductor device.
Technical effects
According to the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device of the present invention, the effect of suppressing the reduction of withstand voltage due to manufacturing variations can be obtained.
Drawings
Fig. 1 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 1.
Fig. 2 is a top view of the portion A-A' of fig. 1 showing the structure of the SJ-MOSFET of embodiment 1.
Fig. 3 is a top view of a portion B-B' of fig. 1 showing the structure of the SJ-MOSFET of embodiment 1.
Fig. 4 is another top view of the B-B' portion of fig. 1 showing the structure of the SJ-MOSFET of embodiment 1.
Fig. 5 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 2.
Fig. 6 is a sectional view showing an internal state of the potential distribution of the SJ-MOSFET of the comparative example.
Fig. 7A is a sectional view showing an internal state of the potential distribution of the SJ-MOSFET of embodiment 1.
Fig. 7B is a sectional view showing an internal state of the potential distribution of the SJ-MOSFET of embodiment 2.
Fig. 8 is a cross-sectional view (one of them) showing a state in the manufacturing process of the SJ-MOSFET of embodiment 1 and embodiment 2.
Fig. 9 is a cross-sectional view (second) showing a state in the manufacturing process of the SJ-MOSFET of embodiment 1 and embodiment 2.
Fig. 10 is a cross-sectional view (third) showing a state in the manufacturing process of the SJ-MOSFET of embodiment 1 and embodiment 2.
Fig. 11 is a cross-sectional view (fourth) showing a state in the manufacturing process of the SJ-MOSFET of embodiment 1 and embodiment 2.
Fig. 12 is a cross-sectional view (fifth) showing a state in the manufacturing process of the SJ-MOSFET of embodiment 1 and embodiment 2.
Fig. 13 is a cross-sectional view (sixth) showing a state in the manufacturing process of the SJ-MOSFET of embodiment 1 and embodiment 2.
Fig. 14 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 3.
Fig. 15 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 4.
Fig. 16 is a cross-sectional view showing a detailed structure of a surface electric field reduction layer of the SJ-MOSFET of embodiment 4.
Fig. 17 is a graph showing the relationship between charge balance and withstand voltage in the SJ-MOSFETs of embodiment 1, embodiment 3, and embodiment 4 and the SJ-MOSFET of the comparative example.
Fig. 18 is a graph showing the relationship between the surface charge and the breakdown voltage in the SJ-MOSFETs of embodiment 1, embodiment 3, and embodiment 4 and the SJ-MOSFET of the comparative example.
Fig. 19 is a sectional view showing the structure of a conventional SJ-MOSFET.
Symbol description
1. 101 N + type semiconductor substrate
2. 102 N drift layer
2 A-2 f n type layer
3A, 3b, 103 n column regions
4A, 4b, 4c, 4d, 104 p column regions
5. 105 P base regions
6. 106 N + source regions
7. 107 Gate insulating film
8. 108 Gate electrode
10. 110 Source electrode
13. 113 Insulating film
14. 114 Drain electrode
15. Field plate electrode
15A field plate electrode
15B field plate electrode
15C field plate electrode
15D field plate electrode
16. Cut-off electrode
17. 117 Lowering surface electric field region
17A first reduced surface electric field region
17B second reduced surface electric field region
17C third reduced surface electric field region
17D fourth reduced surface electric field region
18 N-type region
19 P-type region
20A, 20b mask for ion implantation
21. Ion implantation
25. The end of the first reduced surface electric field region
30. 130 Active region
40. 140 Edge termination region
50、150 SJ-MOSFET
60. Equipotential lines
70. Surface protective film
W1 first decreasing width of surface electric field region
W2 second reduction of width of surface electric field region
W3 third reduction of width of surface electric field region
W4 fourth reduction of width of surface electric field region
Width of opening of w11 active region
Width of opening of w12 edge termination region
Width of opening of w13 edge termination region
Photoresist width at w14 edge termination region
W15 is divided into photoresist width at the portions of the first reduced surface electric field region 17a and the second reduced surface electric field region 17b
Pitch of P1 opening (active region)
Pitch of P2 opening (edge termination region)
Pitch of P3 opening (edge termination region)
Detailed Description
Hereinafter, preferred embodiments of the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the drawings, in a layer or region prefixed with n or p, it means that electrons or holes are majority carriers, respectively. In addition, the + and-labeled n or p represent higher and lower doping concentrations, respectively, than the unlabeled + and-labeled layer or region. The concentration is not limited to the same concentration, and the labeling of n or p containing +and-is similar. In the following description of the embodiments and the drawings, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.
(Embodiment 1)
The super junction semiconductor device of the present invention will be described by taking an SJ-MOSFET as an example. Fig. 1 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 1. Fig. 2 is a top view of the portion A-A' of fig. 1 showing the structure of the SJ-MOSFET of embodiment 1. Fig. 3 is a plan view of a portion B-B' of fig. 1 showing the structure of the SJ-MOSFET of embodiment 1. In addition, fig. 4 is another plan view of the B-B' portion of fig. 1 showing the structure of the SJ-MOSFET of embodiment 1. FIG. 1 is a cross-sectional view of the portion A-A' of FIGS. 2-4.
The SJ-MOSFET50 shown in fig. 1 is a SJ-MOSFET50 including a MOS (Metal Oxide Semiconductor: metal oxide semiconductor) gate on the front surface (surface on the p-type base region 5 side described later) side of a semiconductor substrate (silicon substrate: semiconductor chip) including silicon (Si). The SJ-MOSFET50 has an active area 30, and an edge termination area 40 surrounding the active area 30. The active region 30 is a region through which current flows in the on state. The edge termination region 40 is a region that moderates an electric field on the substrate front side of the drift region and maintains a withstand voltage. In the active region 30 of fig. 1, only one unit cell (functional unit of the element) is shown, and other unit cells adjacent thereto are not shown. The boundary between the active region 30 and the edge termination region 40 is the end of the p-type base region 5.
The n + type semiconductor substrate (semiconductor substrate of the first conductivity type) 1 is a silicon single crystal substrate doped with, for example, phosphorus (P). The n-type drift layer (first semiconductor layer of the first conductivity type) 2 is a low-concentration n-type drift layer doped with, for example, phosphorus at an impurity concentration lower than that of the n + -type semiconductor substrate. Hereinafter, the n + -type semiconductor substrate 1 and the n-type drift layer 2 are used together as a semiconductor base. On the front surface side of the semiconductor substrate, a MOS gate structure (element structure) is formed. Further, a drain electrode 14 is provided on the back surface of the semiconductor substrate.
On the active region 30 side of the SJ-MOSFET50, a first parallel pn region is provided. The first parallel pn-regions are alternately and repeatedly arranged with n-type column regions 3a and p-type column regions 4a. The p-type column region 4a is provided so as not to reach the surface of the n + -type semiconductor substrate 1 from the surface of the n-type drift layer 2. As shown in fig. 2 to 4, the planar shapes of the n-type pillar regions 3a and the p-type pillar regions 4a in the active region 30 are stripe shapes.
In addition, a p-type base region (second semiconductor region of the second conductivity type) 5 is selectively provided in the surface layer of the n-type drift layer 2 so as to be in contact with the p-type column region 4a, and an n + -type source region (third semiconductor region of the first conductivity type) 6 is selectively provided in the surface layer of the p-type base region 5. A gate electrode 8 is provided on the surface of the p-type base region 5 at a portion sandwiched between the n + -type source region 6 and the n-type column region 3a via a gate insulating film 7. The gate electrode 8 may be provided on the surface of the n-type column region 3a with the gate insulating film 7 interposed therebetween.
The insulating film 13 is provided on the front surface side of the semiconductor substrate so as to cover the gate electrode 8. The source electrode 10 is in contact with the n + -type source region 6 and the p-type base region 5 via a contact hole formed by opening an interlayer insulating film (not shown), and is electrically connected to the n + -type source region 6 and the p-type base region 5.
The source electrode 10 is electrically insulated from the gate electrode 8 by an insulating film 13. A protective film (not shown) including, for example, a passivation film of polyimide is selectively provided on the source electrode 10.
The field plate electrode 15 is disposed apart from the source electrode 10 at a position further outward (edge termination region 40 side) than the source electrode 10. In addition, the field plate electrode 15 is provided in a substantially annular shape along the boundary between the active region 30 and the edge termination region 40. The field plate electrode 15 may also function as a gate wiring electrically connected to the gate electrode 8.
A second parallel pn-region is also provided on the edge termination region 40 side of the SJ-MOSFET 50. As shown in fig. 3, the planar shapes of the n-type pillar regions 3b and the p-type pillar regions 4b in the edge termination region 40 may be stripe shapes, and as shown in fig. 4, the planar shapes of the n-type pillar regions 3b and the p-type pillar regions 4b in the edge termination region 40 may also be rectangular shapes.
In addition, as shown in fig. 1 to 4, the width of the n-type pillar region 3a in the active region 30 is larger than the width of the n-type pillar region 3b in the edge termination region 40, and the width of the p-type pillar region 4a in the active region 30 is larger than the width of the p-type pillar region 4b in the edge termination region 40. Thereby, the impurity concentration of the second parallel pn structure in the edge termination region 40 can be made lower than the impurity concentration of the first parallel pn structure in the active region 30. Therefore, the withstand voltage of the edge termination region 40 can be made higher than that of the active region 30.
An n-type drift layer 2 may be provided outside the second parallel pn region so as to surround the second parallel pn region, and an n + -type region (not shown) functioning as a channel stopper may be provided on the surface of the n-type drift layer 2. A reduced surface electric field region (first semiconductor region of the second conductivity type) 17 is provided on the surface of the second parallel pn region. An insulating film 13 is provided on the surface of the reduced surface electric field region 17 and the n-type drift layer 2. In addition, a cut-off electrode 16 is provided on the surface of the n + -type region.
As shown in fig. 1 and 2, in embodiment 1, the reduced surface electric field region 17 extends in the direction of the cutting electrode 16 so as to overlap the outer end portion of the field plate electrode 15 in a plan view, and is divided into two or more. In the example of fig. 1, the reduced surface electric field region 17 is divided into two reduced surface electric field regions, a first reduced surface electric field region 17a close to the active region 30 and a second reduced surface electric field region 17b distant to the active region 30.
As shown in fig. 2, the planar shapes of the first reduced surface electric field region 17a and the second reduced surface electric field region 17b are set in a ring shape. In addition, the first reduced surface electric field region 17a and the second reduced surface electric field region 17b are electrically connected to the p-type column region 4b of the second parallel pn region. Further, as shown in fig. 1, a p-type column region 4b which is not connected to the first reduced surface electric field region 17a and the second reduced surface electric field region 17b may be disposed between the first reduced surface electric field region 17a and the second reduced surface electric field region 17 b.
In addition, between the first and second reduced surface electric field regions 17a and 17b and the insulating film 13 thereabove, an n-type region 18 is provided. The end 25 of the first reduced surface electric field region 17a on the active region 30 side may be in contact with the insulating film 13. In addition, the end 25 of the first resurf region 17a may be electrically connected to the field plate electrode 15. The end 25 of the first reduced surface electric field region 17a may be disposed in a ring shape.
As described above, when the withstand voltage is maintained, the electric field concentration in the edge termination region 40 can be relaxed by partially or completely depleting the reduced surface electric field region 17. By dividing the reduced surface electric field region 17, the electric potential in the reduced surface electric field region 17 can be shared with each other, and the electric field strength can be partially increased. Therefore, even when the charge balance of the second parallel pn region is high in p-type impurity due to manufacturing variations, or when the p-type impurity concentration of the reduced surface electric field region 17 increases, the reduced surface electric field region 17b on the side close to the cut electrode 16 can be buffered, and the rapid decrease in withstand voltage can be alleviated. Therefore, the pressure resistance caused by manufacturing variation can be suppressed from decreasing.
(Embodiment 2)
Fig. 5 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 2. The portions A-A' of fig. 5 are the same portions as the top view of fig. 2 showing the structure of the SJ-MOSFET of embodiment 1. The portion B-B' of fig. 5 showing the structure of the SJ-MOSFET of embodiment 2 is the same portion as the top view of fig. 3 showing the structure of the SJ-MOSFET of embodiment 1. Other plan views of the portion B-B' of fig. 5 showing the structure of the SJ-MOSFET of embodiment 2 are the same as the plan view of fig. 4.
Embodiment 2 is different in that the p-type column region 4b which is not connected to the first reduced surface electric field region 17a and the second reduced surface electric field region 17b is not arranged between the first reduced surface electric field region 17a and the second reduced surface electric field region 17 b.
Embodiment 2 can obtain the same effects as embodiment 1 even if the p-type column region 4b which is not connected to the first reduced surface electric field region 17a and the second reduced surface electric field region 17b is not arranged between the first reduced surface electric field region 17a and the second reduced surface electric field region 17 b.
In addition, in one SJ-MOSFET50, a portion in which the p-type pillar region 4b not connected to the first reduced surface electric field region 17a and the second reduced surface electric field region 17b is arranged between the first reduced surface electric field region 17a and the second reduced surface electric field region 17b as shown in fig. 1, and a portion in which the p-type pillar region 4b not connected to the first reduced surface electric field region 17a and the second reduced surface electric field region 17b is not arranged between the first reduced surface electric field region 17a and the second reduced surface electric field region 17b as shown in fig. 5 may be mixed.
However, in the case of the mixed existence, the first reduced surface electric field region 17a is separated from the second reduced surface electric field region 17 b. In addition, the width w1 of the first reduced surface electric field region 17a and the width w2 of the second reduced surface electric field region 17b distant from the active region 30 satisfy the relationship described later.
The SJ-MOSFET50 shown in fig. 1 is used in a state of being sealed with a sealing resin such as a molding resin. If the adhesion between the sealing resin and the SJ-MOSFET50 is insufficient, a moisture plasma substance may enter between the sealing resin and the SJ-MOSFET 50. In this case, charges are accumulated in the protective film of the SJ-MOSFET 50.
Fig. 6 is a sectional view showing an internal state of the potential distribution of the SJ-MOSFET of the comparative example. The SJ-MOSFET of the comparative example is different from the SJ-MOSFET of embodiment 1 in that the reduced surface electric field region 117 is not divided into the first reduced surface electric field region 17a and the second reduced surface electric field region 17b. As shown in fig. 6, if the reduced surface electric field region 117 is not divided, the equipotential lines 60 are substantially uniformly arranged on the reduced surface electric field region 117. In this state, if charges are accumulated on the surface protective film 70, the equipotential lines 60 move to the inside (the active region 30 side) or the outside (the cut-off electrode 16 side). For example, if positive charge is accumulated, the movement is inward, and if negative charge is accumulated, the movement is outward. In this case, the equipotential lines 60 are densely formed at the end of the reduced surface electric field region 117, and the withstand voltage varies.
Fig. 7A is a sectional view showing an internal state of the potential distribution of the SJ-MOSFET of embodiment 1. As shown in fig. 7A, if the reduced surface electric field region 17 is divided, the interval of the equipotential lines 60 becomes wider at the divided position. If charges are accumulated in the surface protective film 70 in such a state, even if the equipotential lines 60 move inward or outward, the movement of the equipotential lines 60 is stopped at the divided positions. This can localize the influence due to the electric charges. Therefore, voltage withstand variation in the case where charges are accumulated on the protective film of the semiconductor device can be suppressed. Further, since the movement of the equipotential lines 60 is stopped at the divided positions, the more the surface electric field region 17 is divided, the more the withstand voltage fluctuation in the case where electric charges are stored can be suppressed.
Fig. 7B is a diagram showing an internal state of the potential distribution of the SJ-MOSFET of embodiment 2. Fig. 7B can obtain the same effect as fig. 7A.
In addition, in the case where the reduced surface electric field region 17 is divided into two as shown in fig. 1 and 5, the ratio of the width w1 of the first reduced surface electric field region 17a close to the active region 30 to the width w2 of the second reduced surface electric field region 17b far from the active region 30 is preferably in the range of 3:7 to 5:5. Here, the width w1 of the first reduced surface electric field region 17a refers to the length of the first reduced surface electric field region 17a from the inside to the outside. The same is true for the width w2 of the second reduced surface electric field region 17 b. That is, it is preferable to range from the case where the width w1 of the first reduced surface electric field region 17a is 3 and the width w2 of the second reduced surface electric field region 17b is 7 to the case where the width w1 of the first reduced surface electric field region 17a is 5 and the width w2 of the second reduced surface electric field region 17b is 5.
In order to maintain the withstand voltage, it is preferable to reduce the surface electric field region to be completely depleted, but the withstand voltage can also be maintained by partially depleting the surface electric field region. In the case where the first reduced surface electric field region 17A on the active region 30 side is partially depleted as shown in fig. 7A and 7B, there is a tendency that the interval of the equipotential lines 60 becomes wider as a whole, as compared with the case where the reduced surface electric field region 117 is fully depleted as shown in fig. 6. In addition, in the region sandwiched between the first reduced surface electric field region 17a and the second reduced surface electric field region 17b, the interval of the equipotential lines 60 becomes narrow (becomes dense). Thereby, the interval of equipotential lines 60 of the second reduced surface electric field region 17b becomes wider, and thus the electric field is relaxed. By relaxing the electric field on the side close to the cutoff electrode 16, the reduction of the withstand voltage due to the surface charge can be suppressed.
Further, in the case of dividing the reduced surface electric field region 17 into two, in order to reduce the reduction of the withstand voltage due to the surface charge, it is preferable that the width w1 of the first reduced surface electric field region 17a close to the active region 30 is shorter than the width w2 of the second reduced surface electric field region 17b distant from the active region 30. In addition, in the case where the reduced surface electric field region 17 is divided into three or more, in order to reduce the reduction of the withstand voltage due to the surface charge, it is preferable to maximize the width of the reduced surface electric field region on the side close to the cut-off electrode 16.
Further, by providing the n-type region 18 between the reduced surface electric field region 17 and the insulating film 13, the fluctuation of the withstand voltage of the edge termination region 40 due to the surface charge can be stabilized. In addition, the n-type region 18 can reduce the entry of holes (holes) into the insulating film 13.
(Methods for manufacturing superjunction semiconductor devices according to embodiment 1 and embodiment 2)
Next, a method for manufacturing the superjunction semiconductor device according to embodiment 1 and embodiment 2 will be described. Fig. 8 to 13 are sectional views showing states in the manufacturing process of the SJ-MOSFET50 of embodiment 1 and embodiment 2. First, an n + type semiconductor substrate 1 including silicon and serving as an n + type drain layer is prepared. Next, on the front surface of the n + -type semiconductor substrate 1, an n-type layer 2a having an impurity concentration lower than that of the n + -type semiconductor substrate 1 is epitaxially grown. The state up to this point is shown in fig. 8.
The epitaxial growth may be performed by doping the n-type impurity so that the impurity concentration of the n-type layer 2a becomes, for example, 1.0x10 14/cm3 or more and 1.0x10 17/cm3 or less.
Next, on the surface of the n-type layer 2a, an ion implantation mask 20a having a predetermined opening width is formed by a photolithography technique using, for example, a photoresist. At this time, the opening width w11 of the active region is set larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening of the active region is set larger than the pitch P2 of the opening of the edge termination region. Ion implantation 21 of a p-type impurity such as boron (B) is performed using the ion implantation mask 20a as a mask, and a p-type region 19 is formed in the surface layer of the n-type layer 2 a. The state up to this point is shown in fig. 9. Next, the ion implantation mask 20a is removed.
Next, on the front side of the n-type layer 2a, an n-type layer 2b having the same impurity concentration as the n-type layer 2a is epitaxially grown. Next, on the surface of the n-type layer 2b, an ion implantation mask 20a having a predetermined opening width is formed by a photolithography technique using, for example, a photoresist. At this time, the opening width w11 of the active region is set larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening of the active region is set larger than the pitch P2 of the opening of the edge termination region. Ion implantation 21 of a p-type impurity such as boron (B) is performed using the ion implantation mask 20a as a mask, and a p-type region 19 is formed in the surface layer of the n-type layer 2B. Next, the ion implantation mask 20a is removed.
Next, on the front side of the n-type layer 2b, an n-type layer 2c having the same impurity concentration as the n-type layer 2b is epitaxially grown. Next, on the surface of the n-type layer 2c, an ion implantation mask 20a having a predetermined opening width is formed by a photolithography technique using, for example, a photoresist. At this time, the opening width w11 of the active region is set larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening of the active region is set larger than the pitch P2 of the opening of the edge termination region. Ion implantation 21 of a p-type impurity such as boron (B) is performed using the ion implantation mask 20a as a mask, and a p-type region 19 is formed in the surface layer of the n-type layer 2c. Next, the ion implantation mask 20a is removed.
Next, on the front side of the n-type layer 2c, an n-type layer 2d having the same impurity concentration as the n-type layer 2c is epitaxially grown. Next, on the surface of the n-type layer 2d, an ion implantation mask 20a having a predetermined opening width is formed by a photolithography technique using, for example, a photoresist. At this time, the opening width w11 of the active region is set larger than the opening width w12 of the edge termination region, and the pitch P1 of the opening of the active region is set larger than the pitch P2 of the opening of the edge termination region. Ion implantation 21 of a p-type impurity such as boron (B) is performed using the ion implantation mask 20a as a mask, and a p-type region 19 is formed in the surface layer of the n-type layer 2d. Thereby, a first parallel pn region and a second parallel pn region including the n-type layers 2a to 2d and the lower portion of the p-type region 19 are formed. The state up to this point is shown in fig. 10.
In the example of fig. 10, an example in which ion implantation and epitaxial growth are repeated four times is shown, but not limited thereto, the number of times of ion implantation and epitaxial growth can be appropriately changed according to the target characteristics such as withstand voltage.
Next, the ion implantation mask 20a is removed. Next, on the front side of the n-type layer 2d, an n-type layer 2e having the same impurity concentration as that of the n-type layer 2d is epitaxially grown. Next, on the surface of the n-type layer 2e, an ion implantation mask 20b having a predetermined opening width is formed by a photolithography technique using, for example, a photoresist. At this time, the opening width w13 of the edge termination region is set smaller than the opening width w12 of the edge termination region of the mask formed on the n-type layers 2a to 2d, and the pitch P3 of the opening portions of the edge termination region is set smaller than the pitch P2 of the opening portions of the edge termination region of the mask formed on the n-type layers 2a to 2 d. In addition, the photoresist width w15 of the portion of the reduced surface electric field region 17 divided into the first reduced surface electric field region 17a and the second reduced surface electric field region 17b is larger than the photoresist width w14 (=p3—w13) of the edge termination region. Ion implantation 21 of p-type impurities such as boron (B) is performed using the ion implantation mask 20B as a mask, and a p-type region 19 is formed in the surface layer of the n-type layer 2e. Thereby, a first parallel pn region including the upper portions of the n-type layer 2e and the p-type region 19 is formed in the active region 30, and the reduced surface electric field region 17 is formed in the edge termination region 40. The state up to this point is shown in fig. 11. Next, the ion implantation mask 20b is removed.
Next, on the front side of the n-type layer 2e, an n-type layer 2f having the same impurity concentration as that of the n-type layer 2e is epitaxially grown. The state up to this point is shown in fig. 12.
Next, a heat treatment (annealing) for activating the p-type region 19 is performed. The implanted impurities are diffused by this heat treatment, and the diffused impurities are connected in the longitudinal direction, thereby forming p-type column regions 4a, 4b. In addition, since the p-type regions 19 formed in the n-type layer 2e are spaced apart from each other at a narrow interval, the diffused impurities are connected in the lateral direction, forming the reduced surface electric field region 17.
Here, in the edge termination region 40, the opening width of the mask is smaller than that of the mask of the active region 30, and therefore the amount of impurity implanted into one portion is small and the diffusion amount is small. Therefore, the impurity does not reach the surface of the n-type region 2f at the time of heat treatment. Accordingly, the n-type region 18 is formed on the upper portion of the reduced surface electric field region 17. On the other hand, in the active region 30, since the impurity amount is large and the diffusion amount is large, the impurity reaches the surface of the n-type region 2f, and the p-type column region 4a is exposed at the surface. Although the impurity does not reach the surface of the n-type region 2f in the active region 30 due to the impurity amount, the p-type column region 4a is connected to the p-type base region 5 in the active region 30 and the p-type region is exposed on the surface because ion implantation is performed at the time of forming the p-type base region 5. The state up to this point is shown in fig. 13.
Next, a mask having a desired opening is formed on the surfaces of the n-type pillar regions 3a and the p-type pillar regions 4a on the active region 30 side by a photolithography technique using, for example, a resist. Then, p-type impurities are ion-implanted by an ion implantation method using the resist mask as a mask. Thereby, the p-type base region 5 is formed in the entire surface region of the p-type column region 4a and a part of the surface region of the n-type column region 3 a. Next, a mask used for ion implantation for forming the p-type base region 5 is removed.
Next, a mask having a desired opening is formed on the surface of the p-type base region 5 by a photolithography technique using, for example, a resist. Then, n-type impurities are ion-implanted by an ion implantation method using the resist mask as a mask. Thereby, n + type source region 6 is formed in a part of the surface region of p type base region 5. Next, the mask used for ion implantation to form n + -type source region 6 is removed.
Next, a heat treatment (annealing) for activating the p-type base region 5 and the n + -type source region 6 is performed. In addition, the order in which the p-type base region 5 and the n + -type source region 6 are formed may be variously changed.
Next, the front surface side of the semiconductor substrate is thermally oxidized to form a gate insulating film 7. Next, a polysilicon layer doped with, for example, phosphorus is formed as the gate electrode 8 on the gate insulating film 7. Next, the polysilicon layer is patterned to selectively remove the polysilicon layer so that the polysilicon layer remains on the portion of the p-type base region 5 sandwiched between the n + -type source region 6 and the n-type column region 3 a. At this time, the polysilicon layer may be left on the n-type column region 3 a.
Next, for example, a phosphor glass (PSG: phosphor SILICATE GLASS, phosphor silicate glass) is formed as an insulating film 13 so as to cover the gate electrode 8. Next, the insulating film 13 and the gate insulating film 7 are patterned and selectively removed. For example, the insulating film 13 and the gate insulating film 7 on the n + -type source region 6 are removed to form a contact hole, thereby exposing the n + -type source region 6. Next, in order to planarize the interlayer insulating film 9, heat treatment (reflow) is performed.
Next, source electrode 10, field plate electrode 15, and cut-off electrode 16 films are formed by sputtering, and source electrode 10, field plate electrode 15, and cut-off electrode 16 are patterned by photolithography and etching. At this time, the source electrode 10 is buried in the contact hole, and the n + -type source region 6 is electrically connected to the source electrode 10. In the contact hole, a tungsten plug or the like may be buried with a barrier metal interposed therebetween.
Next, a nickel film, for example, is formed on the surface (back surface of the semiconductor base) of the n + -type semiconductor substrate 1 as the drain electrode 14. Then, heat treatment is performed to form an ohmic contact between the n + -type semiconductor substrate 1 and the drain electrode 14. Thereby, the SJ-MOSFET50 shown in fig. 1 is completed.
As described above, according to embodiment 1 and embodiment 2, the reduced surface electric field region is divided into two or more. This can buffer the reduced surface electric field region on the side closer to the cut-off electrode, and alleviate the rapid decrease in withstand voltage. Therefore, the pressure resistance caused by manufacturing variation can be suppressed from decreasing. In addition, when charges are accumulated on the protective film, the movement of the equipotential lines is stopped at a position where the surface electric field region is divided, and the influence of the charges is localized. Therefore, voltage withstand variation in the case where charges are accumulated on the protective film of the semiconductor device can be suppressed.
Embodiment 3
Fig. 14 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 3. Embodiment 3 differs from embodiments 1 and 2 in that the reduced surface electric field region 17 is divided into four of a first reduced surface electric field region 17a, a second reduced surface electric field region 17b, a third reduced surface electric field region 17c, and a fourth reduced surface electric field region 17 d.
In embodiment 3, the width w1 of the first reduced surface electric field region 17a, the width w2 of the second reduced surface electric field region 17b, the width w3 of the third reduced surface electric field region 17c, and the width w4 of the fourth reduced surface electric field region 17d preferably have a relationship of w1.ltoreq.w2.ltoreq.w3.ltoreq.w4. In fig. 14, an end portion 25 of the first reduced surface electric field region 17a is a portion of the p-type base region 5, and the first reduced surface electric field region 17a may be connected to the field plate electrode 15a via the p-type base region 5. Similarly, the second reduced surface electric field region 17b, the third reduced surface electric field region 17c, and the fourth reduced surface electric field region 17d may be connected to the field plate electrode 15b, the field plate electrode 15c, and the field plate electrode 15d through the p-type base region 5, respectively.
The field plate electrode 15a may also function as a gate electrode electrically connected to the gate electrode 8. However, if the field plate electrodes 15b, 15c, 15d are electrically connected to the gate electrode 8, the same potential as the gate electrode 8 is applied, and the withstand voltage cannot be maintained. Therefore, the field plate electrodes 15b, 15c, 15d are not electrically connected to the gate electrode 8.
The p-type column regions 4c and 4d disposed at both ends of the third reduced surface electric field region 17c may or may not be in contact with the third reduced surface electric field region 17 c.
As described above, in embodiment 3, the reduced surface electric field region is divided into four. As a result, the rapid decrease in withstand voltage can be alleviated, and the decrease in withstand voltage due to manufacturing variations can be suppressed, as in embodiment 1 and embodiment 2. Further, since the movement of the equipotential lines is stopped at the position where the reduced surface electric field region is divided, embodiment 3 can localize the influence of the electric charges more than embodiments 1 and 2 where the reduced surface electric field region is divided into two. Therefore, compared with embodiment modes 1 and 2, embodiment mode 3 can further suppress voltage withstand fluctuations in the case where charges are accumulated on the protective film of the semiconductor device.
Embodiment 4
Fig. 15 is a cross-sectional view showing the structure of the SJ-MOSFET of embodiment 4. The impurity concentration of the fourth reduced surface electric field region 17d and the length of the outer p-type column region 4b of embodiment 4 are different from those of embodiment 3. As in embodiment 3, in embodiment 4 as well, it is preferable that the width w1 of the first reduced surface electric field region 17a, the width w2 of the second reduced surface electric field region 17b, the width w3 of the third reduced surface electric field region 17c, and the width w4 of the fourth reduced surface electric field region 17d have a relationship of w1+.w2+.w3+.w4.
As shown in fig. 15, in embodiment 4, the second parallel pn structure in the edge termination region 40 is composed of an inner structure S1 on the element inner side (active region 30 side) and an outer structure S2 on the element outer side (cut electrode 16 side) which is farther from the active region 30 than the inner structure S1. The length t2 of the p-type column region 4b of the outer structure S2 from the surface of the n-type drift layer may be shorter than the length t1 of the p-type column region 4b of the inner structure S1 from the surface of the n-type drift layer, or the same length (the length t2 may be equal to or less than the length t1 (t 2. Ltoreq.t1)). The p-type column regions 4c and 4d disposed at both ends of the third reduced surface electric field region 17c may or may not be in contact with the third reduced surface electric field region 17 c.
Fig. 16 is a cross-sectional view showing a detailed structure of a surface electric field reduction layer of the SJ-MOSFET of embodiment 4. Fig. 16 is an enlarged view of the fourth reduced surface electric field region 17 d. As shown in fig. 16, the width of the fourth reduced surface electric field region 17d becomes narrower toward the outside of the element. In addition, the impurity concentration of the fourth reduced surface electric field region 17d becomes lower toward the outside of the element. The fourth reduced surface electric field region 17d has a first portion 17d1 inside the element (on the side closer to the active region 30), a second portion 17d2 farther from the active region 30 than the first portion 17d1, and a third portion 17d3 outside the element farther from the active region 30 than the second portion 17d 2. The (diffusion) distance from the center depth t3 of the resurf region to the surface of the first portion 17D1 is D1 and the impurity concentration thereof is D1, the (diffusion) distance from the center depth t3 of the resurf region to the surface of the second portion 17D2 is D2 and the impurity concentration thereof is D2, and the (diffusion) distance from the center depth t3 of the resurf region to the surface of the third portion 17D3 is D3 and the impurity concentration thereof is D3. In this case, d1> D2> D3, d1:d2=1.5:1 to 1.2:1, d2:d3=1:0.75 to 1:0.5 are preferable.
In embodiment 4, only the fourth reduced surface electric field region 17d is formed in a shape in which the width thereof is narrower as it goes to the outside of the element and the impurity concentration thereof is lower, but the first reduced surface electric field region 17a, the second reduced surface electric field region 17b, and the third reduced surface electric field region 17c on the inside may be formed in the same shape.
As described above, in embodiment 4, the fourth reduced surface electric field region is formed in a shape such that the width thereof is narrower as it goes to the outside of the element and the impurity concentration thereof is lower. As a result, embodiment 4 can suppress voltage withstand fluctuations even more when charges are accumulated in the protective film of the semiconductor device than embodiments 1 to 3.
Fig. 17 is a graph showing the relationship between charge balance and withstand voltage in the SJ-MOSFETs of embodiment 1, embodiment 3, and embodiment 4 and the SJ-MOSFET of the comparative example. As shown in fig. 6, the SJ-MOSFET of the comparative example is different from the SJ-MOSFET of embodiment 1 in that the reduced surface electric field region 117 is not divided into the first reduced surface electric field region 17a and the second reduced surface electric field region 17b. In FIG. 17, the vertical axis represents the breakdown voltage of the SJ-MOSFET in V. The horizontal axis represents charge balance, and a charge balance of "1" represents a state in which the impurity amount of the n-type column regions 3a and 3b is substantially equal to the impurity amount of the p-type column regions 4a and 4b in the first parallel pn region and the second parallel pn region, and a state in which the impurity amount of the n-type is larger than the charge balance of "1" on the side closer to the origin (the n-rich side) and the impurity amount of the p-type is larger than the charge balance of "1" on the side farther from the origin (the p-rich side).
As shown in fig. 17, when the charge balance is "1", the breakdown voltage of the SJ-MOSFETs according to embodiment 1, embodiment 3, and embodiment 4 is equal to that of the SJ-MOSFET of the comparative example. In addition, the SJ-MOSFETs according to embodiments 1, 3, and 4 have a lower breakdown voltage than the SJ-MOSFETs according to the comparative examples even in a state where the charge balance is biased to one side (a state where one of the n-type/p-type impurity amounts is larger). In addition, the SJ-MOSFETs of embodiment 3 and embodiment 4 have a smaller decrease in withstand voltage than the SJ-MOSFET of embodiment 1 in a state where the charge balance is biased to one side.
The same effect can be obtained also in the SJ-MOSFET of embodiment 2. The same effect can be obtained by mixing the cross-sectional shape shown in fig. 1 of embodiment 1 and the cross-sectional shape shown in fig. 5 of embodiment 2 in one SJ-MOSFET.
Fig. 18 is a graph showing the relationship between the surface charge and the withstand voltage in the SJ-MOSFETs of embodiment 1, embodiment 3, and embodiment 4 and the comparative example SJ-MOSFET. In FIG. 18, the vertical axis represents the breakdown voltage of the SJ-MOSFET in V. The horizontal axis represents surface charge. On the horizontal axis, the position of 0 represents a state where the surface charge is zero, the one closer to the origin (negative (-) side) than the position of 0 represents a state where the negative charge is more, and the one farther from the origin (positive (+) side) than the position of 0 represents a state where the positive charge is more. Fig. 18 shows the relationship between the surface charge and the withstand voltage in the case where the charge balance is "1". The surface charge is a charge accumulated in a surface protection film (for example, the surface protection film 70 shown in fig. 6, 7A, and 7B) disposed on the outermost surface of the superjunction semiconductor device (SJ-MOSFET).
As shown in fig. 18, in the case where the surface charge is zero, the breakdown voltage of the SJ-MOSFETs according to embodiment 1, embodiment 3, and embodiment 4 is equal to that of the SJ-MOSFET of the comparative example. The SJ-MOSFET of embodiment 1 has a withstand voltage equivalent to that of the SJ-MOSFET of the comparative example even in a state where negative charges are more. On the other hand, the SJ-MOSFET of embodiment 1 has a smaller decrease in withstand voltage than the SJ-MOSFET of the comparative example in a state where positive charges are more.
The SJ-MOSFETs of embodiment 3 and embodiment 4 have less reduction in withstand voltage than the SJ-MOSFETs of the comparative examples, both in the more negatively charged state and in the more positively charged state. In addition, the SJ-MOSFET of embodiment 3 has a smaller decrease in withstand voltage in a state where positive charges are more. The SJ-MOSFET of embodiment 4 has a least decrease in withstand voltage in a state where negative charges are more.
The same effect can be obtained also in the SJ-MOSFET of embodiment 2. The same effect can be obtained by mixing the cross-sectional shape shown in fig. 1 of embodiment 1 and the cross-sectional shape shown in fig. 5 of embodiment 2 in one SJ-MOSFET.
In the above, the case where the MOS gate structure is formed on the first main surface of the silicon substrate has been described as an example in the present invention, but the present invention is not limited thereto, and various changes may be made in the type of semiconductor (for example, silicon carbide (SiC) or the like), the plane orientation of the main surface of the substrate, and the like. In the present invention, the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, but the same is true for the present invention that the first conductivity type is p-type and the second conductivity type is n-type.
Industrial applicability
As described above, the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device according to the present invention are useful for high-voltage semiconductor devices used in power conversion devices, power supply devices for various industrial facilities, and the like.
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| JP2023139378A (en) * | 2022-03-22 | 2023-10-04 | 国立研究開発法人産業技術総合研究所 | Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device |
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| CN102194882A (en) * | 2010-03-15 | 2011-09-21 | 瑞萨电子株式会社 | Semiconductor device |
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| JP5358963B2 (en) * | 2008-02-04 | 2013-12-04 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
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| CN103066125A (en) * | 2011-10-21 | 2013-04-24 | 富士电机株式会社 | Superjunction semiconductor device |
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