JP2010019894A - Plasma display device - Google Patents

Abstract

A voltage obtained by a bootstrap circuit of a plasma display device is stabilized.
A scan electrode driving circuit has a first node N61 on which a sustain pulse is superimposed and a second node N62 connected to the first node N61 via a first resistor R61. The other terminal is connected to the output node of the predetermined power supply E61 via the first diode D61, the other terminal is connected to the second node N62, and the predetermined power supply E61 is connected via the second diode D62. A bootstrap circuit 61 having a first capacitor C61 connected to a terminal on the reference potential side, and charged from the first capacitor C61 of the bootstrap circuit 61 via the second resistor R62 and superimposed on the first node N61. And a second capacitor C62 that operates as a floating power source 62.
[Selection] Figure 8

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate which are arranged to face each other. A plurality of scan electrodes and sustain electrodes constituting a display electrode pair are formed in parallel with each other on the front substrate, and a plurality of parallel data electrodes are formed on the back substrate. The front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, color display is performed by generating a gas discharge in each discharge cell and exciting and emitting phosphors.

  As a method of driving the panel, a subfield method is generally used in which one field period is divided into a plurality of subfields and gradation display is performed by a combination of subfields that emit light. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to form wall charges. In the sustain period, a sustain pulse is alternately applied to the scan electrode and the sustain electrode, a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor of the corresponding discharge cell emits light to display an image.

  In order to drive the panel in this way, a driving voltage waveform is applied to each electrode from the driving circuit of the plasma display device. Among the drive circuits, the scan electrode drive circuit has various voltage waveforms such as an initialization waveform voltage for generating an initialization discharge, a scan pulse for generating an address discharge, and a sustain pulse for generating a sustain discharge. Need to be generated. Therefore, many switching elements and transistors are used in the scan electrode driving circuit.

In order to control these switching elements and transistors, a control circuit and a floating power source for operating the control circuit are required. As a typical method for producing a floating power supply, a so-called bootstrap circuit that can be configured simply and inexpensively using a diode and a capacitor is often used. An example of such a plasma display device is described in Patent Document 1.
JP 2007-233223 A

  However, when a sustain pulse is applied to the display electrode pair, a large current exceeding several tens of amperes flows instantaneously, and the voltage obtained by the bootstrap circuit changes due to the influence of ringing or the like generated at this time. In recent years, the screen of the panel has been enlarged, and the current accompanying the charge / discharge and sustain discharge of the electrode capacity tends to be further increased. Along with this, an excessive voltage exceeding an allowable value is generated in the bootstrap circuit, the control circuit is not operated, and there is a possibility that an image cannot be displayed.

  The ringing described above greatly depends on the image to be displayed, and the voltage obtained by the bootstrap circuit fluctuates accordingly. For this reason, when a specific image is displayed, the switching element and the transistor cannot be accurately controlled, and there is a problem that the image display quality is deteriorated.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a plasma display device having excellent image display quality by stabilizing a voltage obtained by a bootstrap circuit even in a large screen panel. And

  To achieve the above object, the present invention provides a plasma display apparatus comprising a panel having a plurality of discharge cells each having a scan electrode, and a scan electrode driving circuit for generating a sustain pulse to be applied to the scan electrode. The electrode driving circuit has one terminal via the first diode with respect to the first node on which the sustain pulse is superimposed and the second node connected to the first node via the first resistor. A first capacitor connected to a terminal on the reference potential side of the predetermined power source via the second diode, and connected to the output node of the predetermined power source and the other terminal to the second node. A bootstrap circuit, and a second capacitor that is charged from the first capacitor of the bootstrap circuit via a second resistor and operates as a floating power source superimposed on the first node. It is characterized in. With this configuration, it is possible to provide a plasma display device with excellent image display quality by stabilizing the voltage obtained by the bootstrap circuit even for a large screen panel.

  Further, the second capacitor of the scan electrode driving circuit of the present invention may be configured to supply power to a transistor control circuit that constitutes the scan electrode driving circuit.

  According to the present invention, it is possible to provide a plasma display device with excellent image display quality by stabilizing the voltage obtained by the bootstrap circuit even for a large screen panel.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. A plurality of scan electrodes 12 and sustain electrodes 13 are formed on a glass front substrate 11. A pair of scan electrodes 12 and sustain electrodes 13 form a display electrode pair 14. A dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. For example, a discharge gas containing xenon is enclosed in the discharge space. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. In panel 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) that are long in the row direction are arranged and long in the column direction. m data electrodes D1 to Dm (data electrode 22 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIG. 1 and FIG. 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, the configuration and operation of the plasma display device in the present embodiment will be described.

  FIG. 3 is a circuit block diagram of plasma display device 30 in accordance with the exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. 36.

  The image signal processing circuit 31 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and further, the light emission / non-light emission in each of the subfields is set to “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 32 converts the image data into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm.

  The timing generation circuit 35 generates various timing signals (including control signals for each transistor described later) for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and sends them to each circuit block. Supply. Scan electrode drive circuit 33 and sustain electrode drive circuit 34 generate drive voltage waveforms based on the respective timing signals and apply them to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.

  The power supply circuit 36 includes various power supplies to be supplied to each circuit block. In particular, as a power supply to be supplied to the scan electrode drive circuit 33, a predetermined power supply E61 described later is provided.

  FIG. 4 is a circuit diagram showing details of scan electrode drive circuit 33 of plasma display device 30 in the embodiment of the present invention. Scan electrode driving circuit 33 generates scan pulse generating circuit 40 for generating a scan pulse, and sustain pulses applied to scan electrodes SC1 to SCn, and at the voltage of node N0 of scan pulse generating circuit 40 shown in FIG. A sustain pulse generating circuit 42 for superimposing the sustain pulse, a waveform generating circuit 44 for generating a drive voltage waveform equal to or higher than the voltage on the low voltage side of the sustain pulse, and a drive voltage waveform below the voltage on the high voltage side of the sustain pulse are generated. Waveform generating circuit 46. In the present embodiment, the voltage on the high voltage side of the sustain power supply is the sustain pulse voltage Vsus, and the voltage on the low voltage side of the sustain power supply is GND, that is, 0 (V).

  Scan pulse generation circuit 40 includes power supply E41 of voltage Vsc superimposed on the voltage of node N0, and switch units OUT1 to OUTn that output scan pulse voltages to scan electrodes SC1 to SCn, respectively. The power supply E41 may be configured using a DC-DC converter, but may also be configured using a bootstrap circuit. Each of the switch units OUT1 to OUTn includes transistors QL1 to QLn for outputting the voltage at the node N0 and transistors QH1 to QHn for outputting a voltage obtained by superimposing the voltage Vsc on the voltage at the node N0. .

  The sustain pulse generation circuit 42 includes a clamp unit 50 and a power recovery unit 55. The clamp unit 50 serves as a first clamp switch that connects the scan electrodes SC1 to SCn to the high-voltage side voltage Vsus of the sustain power source for generating the sustain pulse, and applies the voltage Vsus to the scan electrodes SC1 to SCn. The transistor Q51, the transistor Q52 as a separation switch connected in series with the transistor Q51 in back-to-back, and the scan electrodes SC1 to SCn are connected to the low voltage side voltage of the sustain power supply, and the scan electrodes SC1 to SCn are set to 0. A transistor Q54 as a second clamp switch for applying (V) and a transistor Q53 as a separation switch connected in series to the transistor Q54 in a back-to-back manner. That is, the transistor Q51 and the transistor Q52 are connected in series and between the sustaining power source of the voltage Vsus and the node N0 so that the directions of currents to be controlled are opposite to each other. Further, the transistor Q54 and the transistor Q53 are connected in series between the GND and the node N0 so that the directions of currents to be controlled are opposite to each other.

  As the clamp switch and the separation switch, an insulated gate bipolar transistor or a field effect transistor can be used, respectively. In this embodiment, insulated gate bipolar transistors are used as the transistors Q51 to Q54, the emitter of the transistor Q51 and the emitter of the transistor Q52 are connected, and the collector of the transistor Q53 and the collector of the transistor Q54 are connected. Hereinafter, the node connecting the emitter of the transistor Q51 and the emitter of the transistor Q52 is referred to as “node N1”, and the node connecting the collector of the transistor Q53 and the collector of the transistor Q54 is referred to as “node N2”.

  In addition, a diode D51, a diode D52, a diode D53, and a diode D54 for bypassing a current from the emitter to the collector are connected in parallel to each of the transistor Q51, the transistor Q52, the transistor Q53, and the transistor Q54. Therefore, by turning on the transistor Q51, a current can flow from the sustain power supply of the voltage Vsus to the node N0 via the transistor Q51 and the diode D52. By turning on the transistor Q52, the transistor Q52 and the diode D51 are turned on. A current can flow from the node N0 toward the maintenance power source. Further, when the transistor Q54 is turned on, a current can flow from the node N0 toward the GND via the diode D53 and the transistor Q54. When the transistor Q53 is turned on, the current flows from the GND via the diode D54 and the transistor Q53. A current can flow toward the node N0.

  When a field effect transistor is used as the switch, the body diode of the field effect transistor bypasses the current in the reverse direction, so that the corresponding diode may be omitted.

  The power recovery unit 55 forms a recovery capacitor C56 for recovering power and a first current path for flowing current from the recovery capacitor C56 to the scan electrodes SC1 to SCn in order to increase the voltage of the scan electrodes SC1 to SCn. A recovery switch and a second recovery switch that forms a current path through which a current flows from the scan electrodes SC1 to SCn to the recovery capacitor C56 in order to reduce the voltage of the scan electrodes SC1 to SCn. A current path through which a current flows from the recovery capacitor C56 to the scan electrodes SC1 to SCn is configured by connecting a transistor Q57 as a first recovery switch, a diode D57, and an inductor L57 in series. The current path through which current flows from the scan electrodes SC1 to SCn to the recovery capacitor C56 is configured by connecting a transistor Q58 as a second recovery switch, a diode D58, and an inductor L58 in series. Then, the inter-electrode capacitance Cp and the inductor L57 or the inductor L58 are LC-resonated so that the sustain pulse rises or falls. The recovery capacitor C56 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vsus / 2, which is half the voltage Vsus, so as to serve as a power source for the power recovery unit 55.

  The waveform generating circuit 44 includes a Miller integrating circuit having a field effect transistor Q44, a capacitor C44, a resistor R44, and a Zener diode D44 and connected to the power supply of the voltage Vset, and an upward ramp waveform that gently increases the voltage at the node N2. Generate voltage. The drain of the transistor Q44 is connected to the power source of the voltage Vset, and the source of the transistor Q44 is connected to the connection point between the transistor Q53 and the transistor Q54, that is, the node N2. FIG. 4 also shows a control circuit 60 for controlling the transistor Q44 for the purpose of later explanation.

  The waveform generation circuit 46 includes a Miller integration circuit composed of a field effect transistor Q46, a capacitor C46, and a resistor R46 and connected to the power supply of the voltage Vad, and generates a downward ramp waveform voltage that gently decreases the voltage at the node N1. Let The source of the transistor Q46 is connected to the power supply of the voltage Vad, and the drain of the transistor Q46 is connected to the connection point between the transistor Q51 and the transistor Q52, that is, the node N1. The waveform generation circuit 46 includes a transistor Q48 and a diode D48 connected to the power source of the voltage Vad, and clamps the voltage at the node N1 to the negative voltage Vad. The emitter of the transistor Q48 is connected to the power source of the voltage Vad, and the collector of the transistor Q48 is connected to the node N1 between the transistors Q51 and Q52.

  In this way, the output of the waveform generation circuit 46 is connected to the node N1, and the output of the waveform generation circuit 44 is connected to the node N2, so that the voltage at the node N0 is changed to an up-slope waveform voltage, a down-slope waveform voltage, The voltage can be set to a voltage such as a voltage Vsus, a negative voltage Vad, or 0 (V).

  Next, the operation of the scan electrode drive circuit 33 will be described together with the method for driving the panel 10. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. In the address period, a scan pulse is applied to the scan electrodes SC1 to SCn as an address voltage and an address pulse is selectively applied to the data electrodes D1 to Dm to selectively generate an address discharge in the discharge cells to emit light. Form a charge. In the sustain period, a number of sustain pulses corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a sustain discharge is generated in the discharge cells that have generated the address discharge to emit light.

  FIG. 5 is a drive voltage waveform diagram applied to each electrode of panel 10 of plasma display device 30 in accordance with the exemplary embodiment of the present invention, and shows drive voltage waveforms of two subfields. FIG. 6 is a diagram showing voltage waveforms at the nodes N0, N1, and N2 of the scan electrode driving circuit 33 of the plasma display device 30 according to the embodiment of the present invention. Details of the operation of one subfield will be described below.

  In the first half of the initialization period, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and an upward ramp waveform voltage that gradually increases is applied to the scan electrodes SC1 to SCn.

  In order to apply an upward ramp waveform voltage to scan electrodes SC1 to SCn, transistors Q53 and Q54 are turned on, voltage VN0 at node N0 is set to 0 (V), and transistors QH1 to QHn of switch units OUT1 to OUTn are turned on. Then, voltage Vsc is applied to scan electrodes SC1 to SCn. Next, the transistor Q54 is turned off and a current is supplied to the transistor Q44 to operate the Miller integrating circuit. Then, the voltage VN2 at the node N2 rises gradually toward the voltage Vset after the voltage rises by the Zener voltage Vz of the Zener diode D44. Since the transistor Q53, which is a separation switch, is on, the voltage VN0 at the node N0 also rises gradually toward the voltage Vset similarly to the voltage VN2 at the node N2. Thus, each of the switch sections OUT1 to OUTn outputs a voltage obtained by superimposing the voltage Vsc on the voltage VN0 of the node N0, so that a ramp waveform voltage that gradually increases toward the voltage (Vsc + Vset) is applied to the scan electrodes SC1 to SCn. .

  While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, and wall voltages are accumulated on the respective electrodes. The Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a downward ramp waveform voltage that gently falls is applied to scan electrodes SC1 to SCn.

  In order to apply a downward ramp waveform voltage to scan electrodes SC1 to SCn, transistor Q44 is first turned off. Then, the transistors Q51 and Q52 are turned on to change the voltage VN0 at the node N0 to the voltage Vsus. Thereafter, the transistors QH1 to QHn of the switch units OUT1 to OUTn are turned off and the transistors QL1 to QLn are turned on to apply the voltage Vsus to the scan electrodes SC1 to SCn. Thereafter, the transistor Q51 and the transistor Q53 are turned off and a current is supplied to the transistor Q46 to operate the Miller integrating circuit. Then, the voltage VN1 at the node N1 gradually decreases toward the voltage Vad. Since the transistor Q52, which is a separation switch, is on, the voltage VN0 at the node N0 gradually decreases toward the voltage Vad similarly to the voltage VN1 at the node N1. In this way, a ramp waveform voltage that gently falls toward voltage Vad is applied to scan electrodes SC1 to SCn.

  Then, a weak initializing discharge occurs again between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm while the ramp waveform voltage decreases, and the wall voltage on each electrode is written. It is adjusted to a value suitable for operation. In the present embodiment, in order to finely adjust the wall voltage, the voltage drop is stopped immediately before the voltage applied to scan electrodes SC1 to SCn reaches voltage Vad.

  In this way, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. Note that, as shown in the initialization period of the second subfield in FIG. 5, the first half of the initialization period may be omitted. In this case, an initializing discharge is selectively generated in a discharge cell that has undergone a sustain discharge in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Ve2 is first applied to sustain electrodes SU1 to SUn, and voltage (Vad + Vsc) is applied to scan electrodes SC1 to SCn. In order to apply the voltage (Vad + Vsc) to the scan electrodes SC1 to SCn, first, the transistor Q48 is turned on to set the voltage VN1 at the node N1 to the negative voltage Vad. Since the transistor Q52, which is a separation switch, is on, the voltage VN0 at the node N0 is also a negative voltage Vad similarly to the voltage VN1. Then, the transistors QH1 to QHn of the switch sections OUT1 to OUTn are turned on, the transistors QL1 to QLn are turned off, and a voltage (Vad + Vsc) is applied to the scan electrodes SC1 to SCn.

  Thereafter, a negative scan pulse voltage Vad is applied to scan electrode SC1, and a positive address pulse voltage is applied to data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among data electrodes D1 to Dm. Vd is applied. In order to apply scan pulse voltage Vad to scan electrode SC1, transistor QH1 is turned off and transistor QL1 is turned on.

  Then, in the discharge cells in the first row, address discharge occurs in the discharge cells to which the address pulse is applied, and an address operation for accumulating wall voltage on each electrode is performed. On the other hand, no address discharge occurs in the discharge cells to which the address pulse voltage Vd is not applied. In this way, the write operation is selectively performed.

  Next, the transistor QH1 is turned on, the transistor QL1 is turned off, the transistor QH2 is turned off, the transistor QL2 is turned on, and the scan pulse voltage Vad is applied to the scan electrode SC2 in the second row. Then, the address pulse voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the second row among the data electrodes D1 to Dm. Then, address discharge occurs selectively in the discharge cells in the second row. The above address operation is performed up to the discharge cell in the nth row.

  Thereafter, transistor Q48 is turned off. Then, the transistors Q53 and Q54 are turned on to set the voltage VN2 at the node N2 and the voltage VN0 at the node N0 to 0 (V). Further, the transistors QH1 to QHn of the switch sections OUT1 to OUTn are turned off and the transistors QL1 to QLn are turned on to apply 0 (V) to the scan electrodes SC1 to SCn.

  In the subsequent sustain period, sustain pulses are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. FIG. 7 is a diagram showing each control signal and sustain pulse of sustain pulse generating circuit 42 of plasma display device 30 in accordance with the exemplary embodiment of the present invention, and particularly shows the details of sustain pulse and the timing of the control signal of each transistor. ing.

  In order to apply the sustain pulse to scan electrodes SC1 to SCn, first, transistor Q57 is turned on at time t1 shown in FIG. Then, current starts to flow from recovery capacitor C56 via transistor Q57, diode D57, inductor L57, and transistors QL1 to QLn, and the voltages of scan electrodes SC1 to SCn begin to rise. Since the inductor L57 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn rises to the vicinity of the voltage Vsus after the time ½ of the resonance period has elapsed.

  At time t2, transistor Q51 is turned on. Then, the voltage VN1 at the node N1 and the voltage VN0 at the node N0 become the voltage Vsus, and the voltage Vsus is applied to the scan electrodes SC1 to SCn. At this time, since the voltage of scan electrodes SC1 to SCn rises rapidly and a large current flows, ringing occurs due to the influence of the floating inductance of scan electrode drive circuit 33 and the wiring.

  In this way, the voltages of scan electrodes SC1 to SCn are forcibly increased to voltage Vsus, and a sustain discharge is generated in the discharge cell that has caused the address discharge. Thereafter, the transistors Q57 and Q51 are turned off.

  Next, at time t3, the transistor Q58 is turned on. Then, current begins to flow from scan electrodes SC1 to SCn to recovery capacitor C56 via transistors QL1 to QLn, inductor L58, diode D58, and transistor Q58, and the voltages of scan electrodes SC1 to SCn begin to drop. Since the inductor L58 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn decreases to near 0 (V) after the time ½ of the resonance period has elapsed.

  Next, at time t4, the transistor Q54 is turned on. Then, the voltage VN2 at the node N2 and the voltage VN0 at the node N0 become 0 (V), and 0 (V) is applied to the scan electrodes SC1 to SCn. Also at this time, since the voltage of scan electrodes SC1 to SCn drops rapidly and a large current flows, ringing occurs due to the influence of the floating inductance of scan electrode drive circuit 33 and the wiring.

  As described above, sustain pulses are applied to scan electrodes SC1 to SCn. Although details are omitted, a sustain pulse is similarly applied to the sustain electrodes.

  Similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the sustain discharge continues in the discharge cells in which the address discharge is caused in the address period. Done. In this embodiment, the transistor Q52 and the transistor Q53 are turned on during the sustain period.

  As described above, in the scan electrode driving circuit 33 in the present embodiment, the switching elements interposed between the recovery capacitor C56 and the scan electrode SCi are only two transistors and one diode, and the power source and the scan of the voltage Vsus are used. Only two transistors and one diode or three transistors are interposed between the electrode SCi and between the GND and the scan electrode SCi. Furthermore, only two transistors and one diode or three transistors are interposed between the power sources of the voltage Vset and the voltage Vad and the scan electrode SCi. Thus, in the present embodiment, the output impedance of the scan electrode drive circuit 33 is suppressed by setting the number of switching elements interposed in each current path to three or less.

  In addition, each voltage value of the power supply used in this embodiment is, for example, voltage Vset = 330 (V), voltage Vsus = 190 (V), voltage Vsc = 140 (V), voltage Vad = −100 (V), voltage Ve1 = 160 (V) and voltage Ve2 = 170 (V). However, it is desirable to set these voltage values to optimum values depending on the discharge characteristics of the panel, the specifications of the plasma display device, and the like.

  Next, a control circuit for controlling the switching elements and transistors will be described. FIG. 8 is a circuit diagram showing details of the waveform generation circuit 44 of the scan electrode drive circuit 33 of the plasma display device 30 in the embodiment of the present invention, and particularly shows details of the control circuit 60 for controlling the transistor Q44. .

  The control circuit 60 includes a bootstrap circuit 61, a floating power supply 62, and a level shift circuit 63. For the following description, the source of the transistor Q44, which is the output terminal of the waveform generation circuit 44, is referred to as a “first node N61”. As described above, the first node N61 is connected to the node N2 where the sustain pulse is superimposed in the sustain period. Therefore, the voltage VN61 at the first node N61 is equal to the voltage VN2 at the node N2.

  The bootstrap circuit 61 includes a first diode D61, a first capacitor C61, a first resistor R61, and a second diode D62. One terminal of the first resistor R61 is connected to the first node N61. The other terminal of the first resistor R61 is hereinafter referred to as “second node N62”. The anode of the first diode D61 is connected to the terminal on the output side of a predetermined power supply E61 whose voltage is 15 (V), and the cathode of the first diode D61 is connected to one terminal of the first capacitor C61. Yes. The other terminal of the first capacitor C61 is connected to the second node N62. The cathode of the second diode D62 is connected to the second node N62, and the anode is connected to the reference potential side terminal of the predetermined power supply E61, that is, GND.

  The floating power source 62 includes a second capacitor C62 and a second resistor R62. One terminal of the second capacitor C62 is connected to the first capacitor C61 via the second resistor R62, and the other terminal of the second capacitor C62 is connected to the first node N61. With this configuration, the second capacitor C62 is charged from the first capacitor C61 via the second resistor R62 and operates as the floating power supply 62 superimposed on the first node N61.

  The level shift circuit 63 level-shifts the control signal Sig44 of the transistor Q44 generated by the timing generation circuit 35 to a control signal based on the potential of the first node N61. The level shift circuit 63 is supplied with power from the second capacitor C62 of the floating power supply 62.

  Next, the operation of the control circuit 60 will be described. FIG. 9 is a diagram showing the voltage VN61 at the first node N61 and the voltage VN62 at the second node N62 in the control circuit 60 of the plasma display device 30 according to the embodiment of the present invention, and surrounded by the broken line in FIG. It is an enlarged view of the ringing part of a sustain pulse. The voltage VN61 at the first node N61 in the sustain period is equal to the voltage VN0 at the node N0. Therefore, as shown in FIG. 9A, ringing is superimposed on the sustain pulse also at the first node N61, and the voltage VN61 at the first node N61 is reduced to the negative voltage Vr. The magnitude of the voltage Vr depends on the shape of the sustain pulse and the image to be displayed, but is about −10 (V) to −20 (V) in the present embodiment.

  The voltage VN62 at the second node N62 is substantially equal to the voltage VN61 while the voltage VN61 at the first node N61 is a positive voltage. However, when the voltage VN61 at the first node N61 decreases to a negative voltage, the second diode D62 conducts, so that the voltage VN62 at the second node N62 does not decrease below -0.7 (V). Then, the first diode D61 becomes conductive, and the voltage (15−0.7) = 14.3 (V) is applied to the first capacitor C61. Therefore, the maximum value of the voltage applied between the terminals of the first capacitor C61 is (14.3 − (− 0.7)) = 15 (V). In this way, the first capacitor C61 is charged to the voltage 15 (V). In the above calculation, the forward voltage drop of the first diode D61 and the second diode D62 is 0.7 (V). Thus, in the present embodiment, the first capacitor C61 of the bootstrap circuit 61 is charged to the voltage 15 (V) and is not charged beyond that.

  One terminal of the second capacitor C62 of the floating power supply 62 is connected to the first node N61, and this terminal voltage drops to a negative voltage Vr. However, since the second capacitor C62 is charged through the second resistor R62, the second capacitor C62 does not follow a rapid voltage change of the sustain pulse ringing. Since the second capacitor C62 is charged from the first capacitor C61 via the second resistor R62, the second capacitor C62 is also charged to the voltage 15 (V). Therefore, there is no possibility that an excessive voltage is applied to the level shift circuit 63.

  Thus, in the present embodiment, with respect to the first node N61 on which the sustain pulse voltage is superimposed and the second node N62 connected to the first node N61 via the first resistor R61. In the control circuit 60 of the scan electrode driving circuit 33, one terminal is connected to the output terminal of the predetermined power supply E61 via the first diode D61, and the other terminal is connected to the second node N62. In addition, a bootstrap circuit 61 having a first capacitor C61 connected to a reference potential side terminal of a predetermined power supply E61 through a second diode D62, and a second capacitor from the first capacitor C61 of the bootstrap circuit 61 to the second And a second capacitor C62 that is charged through a resistor R62 and operates as a floating power source 62 superimposed on the first node N61. The second capacitor C62 supplies power to the level shift circuit 63 of the control circuit 60 of the transistor Q44 constituting the scan electrode driving circuit 33.

  By using the bootstrap circuit 61 and the floating power supply 62 configured as described above, the floating power supply 62 having a stable voltage can be configured without being affected by the ringing superimposed on the sustain pulse. Can be operated stably.

  Assuming that a conventional bootstrap circuit composed of one diode and one capacitor is used as the floating power supply, the maximum value of the voltage applied between the terminals of the bootstrap capacitor is 15 (V) + Vr. . Therefore, the bootstrap capacitor is charged to voltage 15 (V) + Vr in the sustain period, and the voltage value may reach 25 (V) to 35 (V). When an excessive voltage exceeding the allowable value is applied to the control circuit, the operation becomes unstable and there is a possibility that an image cannot be displayed.

  However, according to the present embodiment, the voltage 15 (V) within the standard can be stably applied to the level shift circuit 63, so that the control circuit 60 can be stably operated.

  In the present embodiment, the first resistor R61 is 6.8Ω, the second resistor R62 is 75Ω, the first capacitor C61 is 4.7 μF, and the second capacitor C62 is 4.7 μF. However, it is desirable that these values be set to optimum values as appropriate in accordance with the characteristics of the panel and the specifications of the plasma display device.

  In this embodiment, the control circuit 60 that controls the transistor Q44 has been described as an example. However, the present invention is not limited to this, and the same applies to a control circuit that controls other switching elements and transistors. Can be applied to.

  It should be noted that the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the optimal values according to the panel characteristics, the plasma display device specifications, and the like.

  According to the present invention, even a large screen panel can stabilize the voltage obtained by the bootstrap circuit, and is useful as a plasma display device with excellent image display quality.

1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. Panel arrangement of panels used in the plasma display device Circuit block diagram of the plasma display device Circuit diagram showing details of scan electrode drive circuit of same plasma display device Drive voltage waveform diagram applied to each electrode of the panel of the plasma display device The figure which shows the voltage waveform of each node of the scanning electrode drive circuit of the plasma display apparatus The figure which shows the control signal and sustain pulse of the sustain pulse generation circuit of the plasma display apparatus Circuit diagram showing details of waveform generation circuit of scan electrode driving circuit of same plasma display device The figure which shows the voltage of each node of the control circuit of the plasma display apparatus

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 12 Scan electrode 13 Sustain electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 36 Power supply circuit 40 Scan pulse generation circuit 42 Sustain pulse generation circuit 44 , 46 Waveform generation circuit 50 Clamp unit 55 Power recovery unit 60 Control circuit 61 Bootstrap circuit 62 Floating power supply 63 Level shift circuit C61 First capacitor C62 Second capacitor D61 First diode D62 Second diode E61 Predetermined power source N61 1st node N62 2nd node R61 1st resistance R62 2nd resistance Sig44 Control signal Q44 Transistor

Claims (2)

A plasma display device comprising a plasma display panel comprising a plurality of discharge cells having scan electrodes, and a scan electrode driving circuit for generating sustain pulses to be applied to the scan electrodes,
The scan electrode driving circuit includes:
For a first node on which the sustain pulse is superimposed and a second node connected to the first node via a first resistor,
One terminal is connected to a terminal on the output side of a predetermined power source via a first diode, the other terminal is connected to the second node, and a reference of the predetermined power source is connected via a second diode. A bootstrap circuit having a first capacitor connected to a terminal on the potential side;
A plasma display comprising: a second capacitor that is charged from the first capacitor of the bootstrap circuit through a second resistor and that operates as a floating power source superimposed on the first node. apparatus. 2. The plasma display apparatus according to claim 1, wherein the second capacitor supplies electric power to a control circuit of a transistor constituting the scan electrode driving circuit.

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