JP2010014770A - Plasma display device - Google Patents

Abstract

A protection function for accurately controlling the rise time of a sustain pulse of a plasma display device and prohibiting an erroneous control signal is added.
A sustain pulse generating circuit includes a first clamp switch Q51 for connecting a display electrode to a high voltage side of a sustain power source, and a second clamp switch Q54 for connecting the display electrode to a low voltage side of the sustain power source. And at least one of the first clamp control signal Sig51 for controlling the first clamp switch Q51 and the second clamp control signal Sig54 for controlling the second clamp switch Q54 is transmitted via the photocoupler 87. The first clamp control signal Sig51 is input to one terminal of the light emitting diode D87 of the photocoupler 87, and the second clamp control signal Sig54 is input to the other terminal of the light emitting diode D87.
[Selection] Figure 9

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate which are arranged to face each other. A plurality of scan electrodes and sustain electrodes, which are display electrodes, are formed in parallel with each other on the front substrate, and a plurality of parallel data electrodes are formed on the back substrate. The front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode and the data electrode cross three-dimensionally. Here, a discharge cell is formed in a portion where the pair of display electrodes and the data electrode face each other. In the panel having such a configuration, color display is performed by generating a gas discharge in each discharge cell and exciting and emitting phosphors.

  As a method of driving the panel, a subfield method is generally used in which one field period is divided into a plurality of subfields and gradation display is performed by a combination of subfields that emit light. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the scan electrode and the sustain electrode which are display electrodes, a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor of the corresponding discharge cell is caused to emit light. Display.

  As a circuit for applying a sustain pulse to the display electrode, a sustain pulse generating circuit having a so-called power recovery circuit that can reduce power consumption in addition to a clamp circuit that clamps to a sustain pulse voltage is generally used. Yes. The power recovery circuit is a circuit that uses a circuit including an inductor as a constituent element to cause LC resonance between the inductor and the interelectrode capacitance of the display electrode, and rises and falls the sustain pulse.

  On the other hand, it is known that the rise time of the sustain pulse greatly affects the discharge characteristics. Various drive methods for displaying a high-quality image by accurately controlling the rise time of the sustain pulse have been studied. For example, Patent Document 1 discloses a driving method in which a sustain pulse having a steep rising edge is inserted at a rate of once every a plurality of times so that the timing of sustain discharge is aligned and display luminance is made uniform. Patent Document 2 discloses a driving method for controlling the ratio of sustain pulses having different rise times according to the lighting rate of the panel.

The rise time of the sustain pulse is controlled by the timing of the control signal for the switching element of the power recovery circuit and the control signal for the switching element of the voltage clamp circuit. The control signals for these switching elements are generated by a timing generation circuit composed of a microcomputer and a logic circuit, and are level-shifted to voltages suitable for the corresponding switching elements and supplied to each switching element (for example, see Patent Document 3). ).
JP-A-2005-338120 JP 2004-206094 A JP 2007-233223 A

  As described above, the control signal of the switching element is generated by the timing generation circuit configured using a microcomputer or a logic circuit, and is supplied to the corresponding switching element via the level shift circuit. A general-purpose half-bridge driver IC is generally used as the level shift circuit. A photocoupler or an amplifier circuit may be used as necessary. However, if there is a variation in delay time in the transmission path of the control signal of the switching element, it becomes difficult to accurately control the rise time of the sustain pulse. In particular, when the control signal of the switching element is transmitted through a circuit element such as a general-purpose half-bridge driver IC or a photocoupler that has a relatively long delay time and a large variation, the rise time of the sustain pulse cannot be accurately controlled. There was a fear.

  Each of the switching element control signals is generated by the timing generation circuit in accordance with a predetermined sequence. However, if an irregular operation is performed for some reason, an erroneous control signal may be generated.

  The present invention has been made in view of the above-described problems, and adds a protection function that accurately controls the rise time of the sustain pulse and prohibits an erroneous control signal, and has excellent image display quality and stable operation. An object is to provide a display device.

  In order to achieve the above object, the present invention provides a panel having a plurality of discharge cells having display electrodes, a sustain pulse generating circuit for generating sustain pulses to be applied to the display electrodes, and a control signal for controlling the sustain pulse generating circuit. A sustain display generating circuit including a recovery capacitor, and a first recovery switch that increases a voltage of the display electrode by causing a current to flow from the recovery capacitor to the display electrode; A second recovery switch for reducing the voltage of the display electrode by causing a current to flow from the display electrode to the recovery capacitor; and connecting the display electrode to the high voltage side of the maintenance power source for generating the sustain pulse, A first clamp switch for applying a voltage on the high voltage side, and a display electrode connected to the low voltage side of the maintenance power source to connect the display electrode to the low voltage of the maintenance power source A second clamp switch for applying the voltage of the first recovery switch, and the timing generation circuit includes a first recovery control signal for controlling the first recovery switch and a second recovery control signal for controlling the second recovery switch; Generating a first clamp control signal for controlling the first clamp switch and a second clamp control signal for controlling the second clamp switch, and outputting the first clamp control signal and the second clamp control signal. At least one is transmitted through a photocoupler, and a first clamp control signal is input to one terminal of the light-emitting diode of the photocoupler and a second clamp control signal is input to the other terminal of the light-emitting diode. And With this configuration, it is possible to provide a plasma display device with excellent image display quality and stable operation by adding a protection function for accurately controlling the rise time of the sustain pulse and prohibiting erroneous control signals.

  In the plasma display device of the present invention, at least one of the first recovery control signal and the second recovery control signal is transmitted via the photocoupler, and the first terminal is connected to one terminal of the light emitting diode of the photocoupler. A configuration may be adopted in which a recovery control signal is input and a second recovery control signal is input to the other terminal of the light emitting diode.

  In the plasma display device of the present invention, the first recovery control signal and the first clamp control signal are supplied via a level shift circuit housed in one package, and the second recovery control signal and the second clamp control signal are supplied. The clamp control signal may be supplied via a level shift circuit housed in one package.

  According to the present invention, it is possible to provide a plasma display device with excellent image display quality and stable operation by adding a protection function for accurately controlling the rise time of the sustain pulse and prohibiting erroneous control signals. Become.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. A plurality of scan electrodes 12 and sustain electrodes 13 are formed on a glass front substrate 11. The pair of scan electrodes 12 and sustain electrodes 13 form one display electrode 14. A dielectric layer 15 is formed so as to cover the display electrode 14, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode 14 and the data electrode 22 intersect each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. ing. For example, a discharge gas containing xenon is enclosed in the discharge space. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrodes 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. In panel 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) that are long in the row direction are arranged and long in the column direction. m data electrodes D1 to Dm (data electrode 22 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIG. 1 and FIG. 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, the configuration and operation of the plasma display device in the present embodiment will be described.

  FIG. 3 is a circuit block diagram of plasma display device 30 in accordance with the exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 31 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and further, the light emission / non-light emission in each of the subfields is set to “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 32 converts the image data into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm.

  The timing generation circuit 35 performs various timing signals (a first collection control signal, a second collection control signal, and a first collection control signal, which will be described later) for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. (Including various control signals of the switching element such as a clamp control signal and a second clamp control signal), and supplies them to the respective circuit blocks. Scan electrode drive circuit 33 and sustain electrode drive circuit 34 generate drive voltage waveforms based on the respective timing signals and apply them to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.

  FIG. 4 is a circuit diagram showing details of scan electrode drive circuit 33 of plasma display device 30 in the embodiment of the present invention. Scan electrode driving circuit 33 generates scan pulse generating circuit 40 for generating a scan pulse, and sustain pulses applied to scan electrodes SC1 to SCn, and at the voltage of node N0 of scan pulse generating circuit 40 shown in FIG. A sustain pulse generating circuit 42 for superimposing the sustain pulse, a waveform generating circuit 44 for generating a drive voltage waveform equal to or higher than the voltage on the low voltage side of the sustain pulse, and a drive voltage waveform below the voltage on the high voltage side of the sustain pulse are generated. Waveform generating circuit 46. In the present embodiment, the voltage on the high voltage side of the sustain power supply is the sustain pulse voltage Vsus, and the voltage on the low voltage side of the sustain power supply is GND, that is, 0 (V).

  Scan pulse generation circuit 40 includes power supply E41 of voltage Vsc superimposed on the voltage of node N0, and switch units OUT1 to OUTn that output scan pulse voltages to scan electrodes SC1 to SCn, respectively. The power supply E41 may be configured using a DC-DC converter, but may also be configured using a bootstrap circuit. Each of the switch units OUT1 to OUTn includes transistors QL1 to QLn for outputting the voltage at the node N0 and transistors QH1 to QHn for outputting a voltage obtained by superimposing the voltage Vsc on the voltage at the node N0. .

  The sustain pulse generation circuit 42 includes a clamp unit 50 and a power recovery unit 55. The clamp unit 50 connects the scan electrodes SC1 to SCn, which are display electrodes, to the voltage Vsus on the high voltage side of the sustain power source for generating the sustain pulse, and applies the voltage Vsus to the scan electrodes SC1 to SCn. The transistor Q51 as a clamp switch, the transistor Q52 as a separation switch connected in series to the transistor Q51 in back-to-back, and the scan electrodes SC1 to SCn as display electrodes are connected to the low voltage side voltage of the sustain power supply , A transistor Q54 as a second clamp switch that applies 0 (V) to the scan electrodes SC1 to SCn, and a transistor Q53 as a separation switch connected in series to the transistor Q54 in a back-to-back manner. That is, the transistor Q51 and the transistor Q52 are connected in series and between the sustaining power source of the voltage Vsus and the node N0 so that the directions of currents to be controlled are opposite to each other. Further, the transistor Q54 and the transistor Q53 are connected in series between the GND and the node N0 so that the directions of currents to be controlled are opposite to each other.

  As the clamp switch and the separation switch, an insulated gate bipolar transistor or a field effect transistor can be used, respectively. In this embodiment, insulated gate bipolar transistors are used as the transistors Q51 to Q54, the emitter of the transistor Q51 and the emitter of the transistor Q52 are connected, and the collector of the transistor Q53 and the collector of the transistor Q54 are connected. Hereinafter, the node connecting the emitter of the transistor Q51 and the emitter of the transistor Q52 is referred to as “node N1”, and the node connecting the collector of the transistor Q53 and the collector of the transistor Q54 is referred to as “node N2”.

  In addition, a diode D51, a diode D52, a diode D53, and a diode D54 for bypassing a current from the emitter to the collector are connected in parallel to each of the transistor Q51, the transistor Q52, the transistor Q53, and the transistor Q54. Therefore, by turning on the transistor Q51, a current can flow from the sustain power supply of the voltage Vsus to the node N0 via the transistor Q51 and the diode D52. By turning on the transistor Q52, the transistor Q52 and the diode D51 are turned on. A current can flow from the node N0 toward the maintenance power source. Further, when the transistor Q54 is turned on, a current can flow from the node N0 toward the GND via the diode D53 and the transistor Q54. When the transistor Q53 is turned on, the current flows from the GND via the diode D54 and the transistor Q53. A current can flow toward the node N0.

  When a field effect transistor is used as the switching element, the body diode of the field effect transistor bypasses the current in the reverse direction, so that the corresponding diode may be omitted.

  The power recovery unit 55 has a recovery capacitor C56 for recovering power and a current path for increasing the voltage of the scan electrodes SC1 to SCn by flowing current from the recovery capacitor C56 to the scan electrodes SC1 to SCn as display electrodes. A first recovery switch to be formed, and a second recovery switch for forming a current path for causing current to flow from the scan electrodes SC1 to SCn, which are display electrodes, to the recovery capacitor C56 to lower the voltage of the scan electrodes SC1 to SCn. have. A current path through which a current flows from the recovery capacitor C56 to the scan electrodes SC1 to SCn is configured by connecting a transistor Q57 as a first recovery switch, a diode D57, and an inductor L57 in series. The current path through which current flows from the scan electrodes SC1 to SCn to the recovery capacitor C56 is configured by connecting a transistor Q58 as a second recovery switch, a diode D58, and an inductor L58 in series. Then, the interelectrode capacitance Cp and the inductor L57 or the inductor L58 are LC-resonated to rise and fall the sustain pulse. The recovery capacitor C56 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vsus / 2, which is half the voltage Vsus, so as to serve as a power source for the power recovery unit 55.

  The waveform generation circuit 44 includes a Miller integration circuit that includes a field effect transistor Q44, a capacitor C44, a resistor R44, and a Zener diode D44, and is connected to the power supply of the voltage Vset. Generate voltage. The drain of the transistor Q44 is connected to the power source of the voltage Vset, and the source of the transistor Q44 is connected to the connection point between the transistor Q53 and the transistor Q54, that is, the node N2.

  The waveform generation circuit 46 includes a Miller integration circuit composed of a field effect transistor Q46, a capacitor C46, and a resistor R46 and connected to the power source of the voltage Vad, and generates a downward ramp waveform voltage that gently decreases the voltage at the node N0. Let The source of the transistor Q46 is connected to the power supply of the voltage Vad, and the drain of the transistor Q46 is connected to the connection point between the transistor Q51 and the transistor Q52, that is, the node N1. The waveform generation circuit 46 includes a transistor Q48 and a diode D48 connected to the power source of the voltage Vad, and clamps the voltage at the node N1 to the negative voltage Vad. The emitter of the transistor Q48 is connected to the power source of the voltage Vad, and the collector of the transistor Q48 is connected to the node N1 between the transistors Q51 and Q52.

  In this way, the output side of the waveform generation circuit 46 is connected to the node N1, and the output side of the waveform generation circuit 44 is connected to the node N2, so that the voltage at the node N0 is the upslope waveform voltage and the downslope waveform. The voltage can be set to a voltage such as a voltage, a voltage Vsus, a negative voltage Vad, or 0 (V).

  FIG. 5 is a circuit diagram showing details of sustain electrode drive circuit 34 of plasma display device 30 in accordance with the exemplary embodiment of the present invention. Sustain electrode drive circuit 34 includes a sustain pulse generation circuit 62 that generates a sustain pulse to be applied to sustain electrodes SU1 to SUn, and a voltage generation circuit 64 that generates voltage Ve1 and voltage Ve2.

  The sustain pulse generation circuit 62 includes a clamp unit 70 and a power recovery unit 75. The clamp unit 70 serves as a first clamp switch that connects the sustain electrodes SU1 to SUn to the voltage Vsus on the high voltage side of the sustain power source for generating the sustain pulse, and applies the voltage Vsus to the sustain electrodes SU1 to SUn. The transistor Q71 includes a transistor Q74 as a second clamp switch that connects the sustain electrodes SU1 to SUn to the low voltage side voltage of the sustain power supply and applies 0 (V) to the sustain electrodes SU1 to SUn. .

  The power recovery unit 75 forms a recovery capacitor C76 for recovering power, and a first current path for flowing current from the recovery capacitor C76 to the sustain electrodes SU1 to SUn in order to increase the voltage of the sustain electrodes SU1 to SUn. A recovery switch and a second recovery switch that forms a current path through which a current flows from the sustain electrodes SU1 to SUn to the recovery capacitor C76 in order to reduce the voltage of the sustain electrodes SU1 to SUn. A current path through which a current flows from the recovery capacitor C76 to the sustain electrodes SU1 to SUn is formed by connecting a transistor Q77 as a first recovery switch, a diode D77, and an inductor L77 in series. Further, the current path through which current flows from the sustain electrodes SU1 to SUn to the recovery capacitor C76 is formed by connecting a transistor Q78 as a second recovery switch, a diode D78, and an inductor L78 in series. The interelectrode capacitance Cp and the inductor L77 or the inductor L78 are LC-resonated to rise and fall the sustain pulse. The recovery capacitor C76 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vsus / 2, which is half of the voltage Vsus, so as to serve as a power source for the power recovery unit 75.

  As the first clamp switch, the second clamp switch, the first recovery switch, and the second recovery switch, an insulated gate bipolar transistor or a field effect transistor can be used, respectively. In this embodiment, insulated gate bipolar transistors are used as the transistor Q71, transistor Q74, transistor Q77, and transistor Q78, and a diode D71 for bypassing the current flowing from the emitter to the collector of the transistor Q71 and transistor Q74. The diodes D74 are connected in parallel.

  When a field effect transistor is used as the switching element, the body diode of the field effect transistor bypasses the current in the reverse direction, so that the corresponding diode may be omitted.

  The voltage generation circuit 64 includes a transistor Q64 and a backflow prevention diode D64 connected to the power source of the voltage Ve1, a transistor Q65 and a backflow prevention diode D65 connected to the power source of the voltage Ve2, and the sustain electrode SU1. The voltage Ve1 or Ve2 is applied to .about.SUn.

  Next, operations of scan electrode drive circuit 33 and sustain electrode drive circuit 34 will be described together with a method for driving panel 10. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. In the address period, a scan pulse is applied to the scan electrodes SC1 to SCn as an address voltage and an address pulse is selectively applied to the data electrodes D1 to Dm to selectively generate an address discharge in the discharge cells to emit light. Form a charge. In the sustain period, sustain pulses of the number corresponding to the luminance weight are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn as display electrodes, and the sustain discharge is generated in the discharge cells that have generated the address discharge. To emit light.

  FIG. 6 is a drive voltage waveform diagram applied to each electrode of panel 10 of plasma display device 30 in accordance with the exemplary embodiment of the present invention, and shows drive voltage waveforms of two subfields. FIG. 7 is a diagram showing voltage waveforms at the nodes N0, N1, and N2 of the scan electrode driving circuit 33 of the plasma display device 30 according to the embodiment of the present invention. Details of the operation of one subfield will be described below.

  In the first half of the initialization period, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and an upward ramp waveform voltage that gradually increases is applied to the scan electrodes SC1 to SCn. In order to apply 0 (V) to sustain electrodes SU1 to SUn, transistor Q74 is turned on.

  In order to apply an upward ramp waveform voltage to scan electrodes SC1 to SCn, transistors Q53 and Q54 are turned on, voltage VN0 at node N0 is set to 0 (V), and transistors QH1 to QHn of switch units OUT1 to OUTn are turned on. Then, voltage Vsc is applied to scan electrodes SC1 to SCn. Next, the transistor Q54 is turned off and a current is supplied to the transistor Q44 to operate the Miller integrating circuit. Then, the voltage VN2 at the node N2 rises gradually toward the voltage Vset after the voltage rises by the Zener voltage Vz of the Zener diode D44. Since the transistor Q53, which is a separation switch, is on, the voltage VN0 at the node N0 also rises gradually toward the voltage Vset similarly to the voltage VN2 at the node N2. Thus, each of the switch sections OUT1 to OUTn outputs a voltage obtained by superimposing the voltage Vsc on the voltage VN0 of the node N0, so that a ramp waveform voltage that gradually increases toward the voltage (Vsc + Vset) is applied to the scan electrodes SC1 to SCn. .

  While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, and wall voltages are accumulated on the respective electrodes. The Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a downward ramp waveform voltage that gently falls is applied to scan electrodes SC1 to SCn. In order to apply voltage Ve1 to sustain electrodes SU1 to SUn, transistor Q74 is turned off and transistor Q64 is turned on.

  In order to apply a downward ramp waveform voltage to scan electrodes SC1 to SCn, transistor Q44 is first turned off. Then, the transistors Q51 and Q52 are turned on to change the voltage VN0 at the node N0 to the voltage Vsus. Thereafter, the transistors QH1 to QHn of the switch units OUT1 to OUTn are turned off and the transistors QL1 to QLn are turned on to apply the voltage Vsus to the scan electrodes SC1 to SCn. Thereafter, the transistor Q51 and the transistor Q53 are turned off and a current is supplied to the transistor Q46 to operate the Miller integrating circuit. Then, the voltage VN1 at the node N1 gradually decreases toward the voltage Vad. Since the transistor Q52, which is a separation switch, is on, the voltage VN0 at the node N0 gradually decreases toward the voltage Vad similarly to the voltage VN1 at the node N1. In this way, a ramp waveform voltage that gently falls toward voltage Vad is applied to scan electrodes SC1 to SCn.

  Then, a weak initializing discharge occurs again between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm while the ramp waveform voltage decreases, and the wall voltage on each electrode is written. It is adjusted to a value suitable for operation. In the present embodiment, in order to finely adjust the wall voltage, the voltage drop is stopped immediately before the voltage applied to scan electrodes SC1 to SCn reaches voltage Vad.

  In this way, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. Note that, as shown in the initialization period of the second subfield in FIG. 6, the first half of the initialization period may be omitted. In this case, an initializing discharge is selectively generated in a discharge cell that has undergone a sustain discharge in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Ve2 is first applied to sustain electrodes SU1 to SUn, and voltage (Vad + Vsc) is applied to scan electrodes SC1 to SCn. In order to apply voltage Ve2 to sustain electrodes SU1 to SUn, transistor Q64 is turned off and transistor Q65 is turned on. In order to apply the voltage (Vad + Vsc) to the scan electrodes SC1 to SCn, first, the transistor Q48 is turned on to set the voltage VN1 at the node N1 to the negative voltage Vad. Since the transistor Q52, which is a separation switch, is on, the voltage VN0 at the node N0 is also a negative voltage Vad similarly to the voltage VN1. Then, the transistors QH1 to QHn of the switch sections OUT1 to OUTn are turned on, the transistors QL1 to QLn are turned off, and a voltage (Vad + Vsc) is applied to the scan electrodes SC1 to SCn.

  Thereafter, a negative scan pulse voltage Vad is applied to scan electrode SC1, and a positive address pulse voltage is applied to data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among data electrodes D1 to Dm. Vd is applied. In order to apply scan pulse voltage Vad to scan electrode SC1, transistor QH1 is turned off and transistor QL1 is turned on.

  Then, in the discharge cells in the first row, address discharge occurs in the discharge cells to which the address pulse is applied, and an address operation for accumulating wall voltage on each electrode is performed. On the other hand, no address discharge occurs in the discharge cells to which the address pulse voltage Vd is not applied. In this way, the write operation is selectively performed.

  Next, the transistor QH1 is turned on, the transistor QL1 is turned off, the transistor QH2 is turned off, the transistor QL2 is turned on, and the scan pulse voltage Vad is applied to the scan electrode SC2 in the second row. Then, the address pulse voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the second row among the data electrodes D1 to Dm. Then, address discharge occurs selectively in the discharge cells in the second row. The above address operation is performed up to the discharge cell in the nth row.

  Thereafter, transistor Q48 is turned off. Then, the transistors Q53 and Q54 are turned on to set the voltage VN2 at the node N2 and the voltage VN0 at the node N0 to 0 (V). Further, the transistors QH1 to QHn of the switch sections OUT1 to OUTn are turned off and the transistors QL1 to QLn are turned on to apply 0 (V) to the scan electrodes SC1 to SCn.

  In the subsequent sustain period, sustain pulses are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, which are display electrodes. FIG. 8 is a diagram showing the control signal and sustain pulse of the sustain pulse generating circuit of plasma display apparatus 30 in the embodiment of the present invention, and particularly shows the details of the sustain pulse and the timing of the control signal of each transistor. .

  In order to apply the sustain pulse to scan electrodes SC1 to SCn, first, transistor Q57 is turned on at time t1 shown in FIG. Then, current starts to flow from recovery capacitor C56 via transistor Q57, diode D57, inductor L57, and transistors QL1 to QLn, and the voltages of scan electrodes SC1 to SCn begin to rise. Since the inductor L57 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn rises to the vicinity of the voltage Vsus after the time ½ of the resonance period has elapsed.

  At time t2, transistor Q51 is turned on. Then, the voltage VN1 at the node N1 and the voltage VN0 at the node N0 become the voltage Vsus, and the voltage Vsus is applied to the scan electrodes SC1 to SCn.

  In this way, the voltages of scan electrodes SC1 to SCn are forcibly increased to voltage Vsus, and a sustain discharge is generated in the discharge cell that has caused the address discharge. Thereafter, the transistors Q57 and Q51 are turned off.

  Next, transistor Q58 is turned on at time t3. Then, current begins to flow from scan electrodes SC1 to SCn to recovery capacitor C56 via transistors QL1 to QLn, inductor L58, diode D58, and transistor Q58, and the voltages of scan electrodes SC1 to SCn begin to drop. Since the inductor L58 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn decreases to near 0 (V) after the time ½ of the resonance period has elapsed.

  Next, at time t4, the transistor Q54 is turned on. Then, the voltage VN2 at the node N2 and the voltage VN0 at the node N0 become 0 (V), and 0 (V) is applied to the scan electrodes SC1 to SCn.

  In order to apply a sustain pulse to sustain electrodes SU1 to SUn, first, transistor Q77 is turned on at time t5. Then, current begins to flow from recovery capacitor C76 via transistor Q77, diode D77, and inductor L77, and the voltages of sustain electrodes SU1 to SUn begin to rise. Since the inductor L77 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes SU1 to SUn rises to the vicinity of the voltage Vsus after the time ½ of the resonance period has elapsed.

  At time t6, transistor Q71 is turned on. Then, voltage Vsus is applied to sustain electrodes SU1 to SUn.

  In this manner, the voltage of sustain electrodes SU1 to SUn is forcibly increased to voltage Vsus, and a sustain discharge is generated in the discharge cell that has caused the address discharge. Thereafter, the transistors Q77 and Q71 are turned off.

  Next, transistor Q78 is turned on at time t7. Then, current starts to flow from the sustain electrodes SU1 to SUn to the recovery capacitor C76 via the inductor L78, the diode D78, and the transistor Q78, and the voltage of the sustain electrodes SU1 to SUn starts to decrease. Since the inductor L78 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes SU1 to SUn decreases to near 0 (V) after a time ½ of the resonance period has elapsed.

  Next, at time t8, the transistor Q74 is turned on. Then, voltage 0 (V) is applied to sustain electrodes SU1 to SUn.

  In the same manner, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a pair of scan electrodes 12 and sustain electrodes 13 constituting display electrode 14 is applied. By applying a potential difference therebetween, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period. In this embodiment, the transistor Q52 and the transistor Q53 are turned on during the sustain period.

  As described above, in the scan electrode driving circuit 33 in the present embodiment, the switching elements interposed between the recovery capacitor C56 and the scan electrode SCi are only two transistors and one diode, and the power source and the scan of the voltage Vsus are used. Only two transistors and one diode or three transistors are interposed between the electrode SCi and between the GND and the scan electrode SCi. Furthermore, only two transistors and one diode or three transistors are interposed between the power sources of the voltage Vset and the voltage Vad and the scan electrode SCi. Thus, in the present embodiment, the output impedance of the scan electrode drive circuit 33 is suppressed by setting the number of switching elements interposed in each current path to three or less.

  In addition, each voltage value of the power supply used in this embodiment is, for example, voltage Vset = 330 (V), voltage Vsus = 190 (V), voltage Vsc = 140 (V), voltage Vad = −100 (V), voltage Ve1 = 160 (V) and voltage Ve2 = 170 (V). However, it is desirable to set these voltage values to optimum values depending on the discharge characteristics of the panel, the specifications of the plasma display device, and the like.

  Next, a method for controlling the rise time of the sustain pulse will be described. In order to generate a sustain pulse with a short rise time as described in Patent Document 1 and Patent Document 2, the rising of the sustain pulse is performed using the power recovery unit 55, the power recovery unit 75, the clamp unit 50, and the clamp unit 70. It suffices to set a short time.

  For example, to apply a sustain pulse having a short rise time to scan electrodes SC1 to SCn, transistor Q57 is turned on at time t11 shown in FIG. Then, current starts to flow from recovery capacitor C56 via transistor Q57, diode D57, inductor L57, and transistors QL1 to QLn, and the voltages of scan electrodes SC1 to SCn begin to rise. Assuming that the sustain pulse rises using the power recovery unit 55 continuously after this, as shown by a broken line in FIG. 8, the scan electrodes SC <b> 1 to SCn are scanned after a half of the resonance period has elapsed. The voltage rises to near the voltage Vsus.

  However, when a sustain pulse with a short rise time is applied, the transistor Q51 is turned on at time t12 before ½ time of the resonance period elapses. Then, the voltage of scan electrodes SC1 to SCn rapidly rises to voltage Vsus, and a sustain pulse having a short rise time (time from time t11 to time t12), that is, a steep sustain pulse is applied to scan electrodes SC1 to SCn.

  The same applies when a sustain pulse having a short rise time is applied to sustain electrodes SU1 to SUn.

  Further, in order to generate a sustain pulse having a long rise time, the power recovery unit 55, the power recovery unit 75, the clamp unit 50, and the clamp unit 70 may be used to set a long time for the sustain pulse to rise.

  For example, in order to apply a sustain pulse having a long rise time to sustain electrodes SU1 to SUn, transistor Q77 is turned on at time t15 shown in FIG. Then, a current starts to flow from the recovery capacitor C76 via the transistor Q77, the diode D77, and the inductor L77, and the voltages of the sustain electrodes SU1 to SUn begin to rise. Then, the voltage of sustain electrodes SU1 to SUn rises to the vicinity of voltage Vsus after the half of the resonance period has elapsed, and when a sustain discharge occurs at this time, the voltage of sustain electrodes SU1 to SUn drops.

  For example, the transistor Q71 is turned on at time t16 after a time longer than half the resonance period has elapsed. Then, the voltage of sustain electrodes SU1 to SUn once decreases and then increases again to voltage Vsus. When such a sustain pulse is applied, it is possible to generate two peaks of sustain discharge as described in Patent Document 2.

  The same applies when a sustain pulse having a long rise time is applied to scan electrodes SC1 to SCn.

  In this way, in order to accurately control the rise time of sustain pulse, transistor Q57 and transistor Q51 of scan electrode drive circuit 33 and transistor Q77 and transistor Q71 of sustain electrode drive circuit 34 should be controlled accurately. Good. Although detailed description is omitted, in order to accurately control the falling time of the sustain pulse, the transistor Q54 and the transistor Q58 of the scan electrode driving circuit 33 and the transistor Q74 and the transistor Q78 of the sustain electrode driving circuit 34 are accurately controlled. Control well.

  8 shows a drive voltage waveform diagram in which the transistor Q77 is turned on after the transistor Q54 is turned on. However, the transistor Q54 may be turned on after the transistor Q77 is turned on. Q54 may be turned on simultaneously. Similarly, a driving voltage waveform diagram in which the transistor Q57 is turned on after the transistor Q74 is turned on is shown. However, the transistor Q74 may be turned on after the transistor Q57 is turned on, and the transistor Q57 and the transistor Q74 are turned on simultaneously. You may turn it on.

  Next, a circuit configuration for accurately controlling the rising time and falling time of the sustain pulse will be described.

  The emitter of the transistor Q51 is the node N1, and its voltage fluctuates as shown in FIG. 7. Therefore, in order to control the transistor Q51, it is necessary to shift the level to a control signal superimposed on the voltage of the node N1. Therefore, the first clamp control signal Sig51 is transmitted to the transistor Q51 via the level shift circuit. The same applies to the transistors Q57 and Q58.

  The level shift circuit can be configured using a transistor or the like. However, using a general-purpose level shift IC is advantageous in terms of cost and mounting. In this embodiment, the level shift circuit is configured by using a half bridge driver IC in which two circuits of the level shift circuit are integrated in one package. Although the emitters of the transistors Q51 and Q57 are reduced to the negative voltage Vad, many general-purpose half-bridge driver ICs cannot shift the level to a negative voltage. In this case, a photocoupler is used or this embodiment is implemented. As in the embodiment, a general-purpose half-bridge driver IC and a photocoupler may be used in combination.

  FIG. 9 is a circuit diagram including control signals of scan electrode drive circuit 33 of plasma display device 30 in accordance with the exemplary embodiment of the present invention. Transistor Q51, transistor Q54, transistor Q57, transistor Q58, and transmission of these control signals The circuit is shown.

  The first clamp control signal Sig51 for controlling the transistor Q51 which is the first clamp switch is input to the anode of the light emitting diode D87 of the photocoupler 87 via the buffer G91 and the resistor R91. The output of the phototransistor Q87 of the photocoupler 87 is transmitted to the gate of the transistor Q51 via the inverter G97 and the level shift circuit 81. The first recovery control signal Sig57 for controlling the transistor Q57 as the first recovery switch is input to the anode of the light emitting diode D88 of the photocoupler 88 via the buffer G93 and the resistor R93. The output of the phototransistor Q88 of the photocoupler 88 is transmitted to the gate of the transistor Q57 via the inverter G98 and the level shift circuit 82. Here, the resistors R97 and R98 are pull-up resistors. The second clamp control signal Sig54 for controlling the transistor Q54 which is the second clamp switch is transmitted to the gate of the transistor Q54 via the buffer G96 and the level shift circuit 85. A second recovery control signal Sig58 for controlling the transistor Q58 which is the second recovery switch is transmitted to the gate of the transistor Q58 via the buffer G95 and the level shift circuit 84.

  In the present embodiment, the second clamp control signal Sig54 is input to the cathode of the light emitting diode D87 of the photocoupler 87 via the buffer G92. Further, the second recovery control signal Sig58 is input to the cathode of the light emitting diode D88 of the photocoupler 88 via the buffer G94.

  Note that each of the control signals is transmitted through the buffers G91 to G96, but it is desirable to insert them as necessary in view of the driving capability of the photocoupler and the level shift circuit. The control signal is transmitted via the inverter G97 and the inverter G98, and it is desirable to insert these signals as necessary in order to maintain logic consistency.

  In the present embodiment, the first clamp control signal Sig51 and the first recovery control signal Sig57 are stored in two photocouplers 87, a photocoupler 88, and one package 83 stored in one package 89. The two level shift circuits 81 and 82 are supplied to the transistors Q51 and Q57, respectively. The two level shift circuits 81 and 82 are integrated in one half bridge driver IC, and this half bridge driver IC is housed in a package 83. Further, the second clamp control signal Sig54 and the first recovery control signal Sig58 are obtained by using the two level shift circuits 85 and level shift circuit 84 housed in one package 86, respectively, and the transistors Q54 and Q58. Has been supplied to. The two level shift circuits 84 and 85 are integrated in one half bridge driver IC, and this half bridge driver IC is housed in a package 86. In this way, by transmitting the first clamp control signal Sig51 and the first recovery control signal Sig57, the rising time of the sustain pulse can be controlled with high accuracy. Further, by transmitting the second clamp control signal Sig54 and the second recovery control signal Sig58 in this manner, the falling time of the sustain pulse can be accurately controlled. The reason will be described below.

  The level shift circuit and the photocoupler have a relatively long delay time when transmitting a signal and a large variation. Similarly, the level shift circuit integrated in the half-bridge driver IC also has a relatively long delay time and a large variation. However, the delay times of the two level shift circuits integrated in one half bridge driver IC are relatively uniform, and their relative variations are small. For example, the delay time of two level shift circuits integrated in one half-bridge driver IC used in the present embodiment is 200 ns ± 50 ns, but the relative variation is ± 15 ns. Similarly, the absolute value of the delay time and its variation are large for the two photocouplers housed in one package, but the relative variation is small.

  As described above, the rise time of the sustain pulse applied to scan electrodes SC1 to SCn is determined by the time from when transistor Q57 is turned on to when transistor Q51 is turned on. Transistor control signals are respectively generated by the timing generation circuit 35 and transmitted via a photocoupler, a level shift circuit, or the like. For this reason, when the delay time of each control signal varies, the rise time also varies.

  However, in the present embodiment, the first clamp control signal Sig51 and the first recovery control signal Sig57 are stored in two photocouplers 87, a photocoupler 88, and one package 83 housed in one package 89. The signal is transmitted to the corresponding transistor Q51 and transistor Q57 via the two level shift circuits 81 and 82. Since the two photocouplers 87 and 88 are housed in one package 89, the photocoupler 87 and the photocoupler 88 have substantially the same temperature, and variations due to the temperature difference can be suppressed. Further, the two level shift circuits 81 and the level shift circuit 82 have substantially the same temperature, and variations due to the temperature difference can be suppressed. Furthermore, since the two level shift circuits 81 and 82 are integrated in one half-bridge driver IC, variations due to manufacturing conditions can be suppressed. Therefore, it is possible to transmit the first clamp control signal Sig51 and the first recovery control signal Sig57 to the transistor Q51 and the transistor Q57 while suppressing the relative variation in the delay time, and to accurately control the rise time of the sustain pulse. can do.

  In this embodiment, it should be noted that the first clamp control signal Sig51 is input to the anode of the light emitting diode D87 of the photocoupler 87, and the cathode of the light emitting diode D87 is not GND but the second clamp control signal Sig54. Is the point where is entered. The first collection control signal Sig57 is connected to the anode of the light emitting diode D88 of the photocoupler 88, and the second collection control signal Sig58 is input to the cathode of the light emitting diode D88 instead of GND.

  By connecting in this way, the light emitting diode emits light and the transistor Q51 is turned on only when the second clamp control signal Sig54 is at low level and the first clamp control signal Sig51 is at high level. When the second clamp control signal Sig54 is at a high level, the light emitting diode does not emit light and the transistor Q51 is turned off even if the first clamp control signal Sig51 is at a high level. That is, when both the first clamp control signal Sig51 and the second clamp control signal Sig54 are at a high level, the second clamp control signal Sig54 is transmitted at a high level and the transistor Q54 is turned on. Since the low level of the clamp control signal Sig51 is transmitted and the transistor Q51 is turned off, the transistor Q51 and the transistor Q54 are not turned on at the same time, and there is no possibility that the power source of the voltage Vsus is short-circuited to GND.

  The first clamp control signal Sig51 and the second clamp control signal Sig54 generated by the timing generation circuit 35 are not originally at a high level. However, even if both the first clamp control signal Sig51 and the second clamp control signal Sig54 become high level for some reason, such as performing an irregular operation or superimposing noise, according to the present embodiment. For example, neither the transistor Q51 nor the transistor Q54 is turned on, and there is no possibility that the power source of the voltage Vsus is short-circuited with the GND.

  Similarly, for the first collection control signal Sig57 and the second collection control signal Sig58, when both the first collection control signal Sig57 and the second collection control signal Sig58 are at the high level, the second collection control signal Sig58. Is preferentially transmitted to turn on the transistor Q58, the low level of the first recovery control signal Sig57 is transmitted, and the transistor Q57 is turned off. Therefore, there is no possibility that a malfunction that both the transistor Q57 and the transistor Q58 are turned on will occur.

  The general-purpose half-bridge driver IC assumes a usage method of generating a pulse waveform by controlling the switching element on the high voltage side and the switching element on the low voltage side, and the switching element on the high voltage side and the low voltage side switching element. Some have incorporated a logic circuit for prohibiting the timing when the switching elements are simultaneously turned on.

  However, in the present embodiment, the first clamp control signal Sig51 of the transistor Q51, which is a high voltage side switching element, and the second clamp control signal Sig54 of the transistor Q54, which is a low voltage side switching element, are in different packages. A housed level shift circuit is used. Therefore, it is not possible to use a half bridge driver IC in which a logic circuit for prohibiting the timing when both switching elements are simultaneously turned on is incorporated.

  Therefore, in this embodiment, a function for prohibiting the timing at which the two control signals are simultaneously turned on is added by simply changing the connection of the control signals input to the photocoupler without adding new parts. is doing.

  That is, the first clamp control signal Sig51 is transmitted through the photocoupler 87, the first clamp control signal Sig51 is input to the anode of the light emitting diode D87 of the photocoupler 87, and the second clamp is applied to the cathode of the light emitting diode D87. A control signal Sig54 is input. The first recovery control signal Sig57 is transmitted via the photocoupler 88, the first recovery control signal Sig57 is input to the anode of the light emitting diode D88 of the photocoupler 88, and the second recovery control signal is input to the cathode of the light emitting diode D88. The signal Sig58 is input. And by comprising in this way, the protection function which prohibits an erroneous control signal is added, and the operation | movement of the plasma display apparatus 30 is stabilized.

  In the present embodiment, the first clamp control signal Sig51 is transmitted to the first clamp switch via the photocoupler 87, and the first clamp control signal Sig51 is supplied to the anode of the light emitting diode D87 of the photocoupler 87. The second clamp control signal Sig54 was input to the cathode of the light emitting diode D87. The first recovery control signal Sig57 is transmitted to the first recovery switch via the photocoupler 88, the first recovery control signal Sig57 is input to the anode of the light emitting diode D88 of the photocoupler 88, and the cathode of the light emitting diode D88. The second recovery control signal Sig58 is input to the input. However, the present invention is not limited to this. At least one of the first clamp control signal and the second clamp control signal is transmitted through the photocoupler, and is transmitted to one terminal of the light emitting diode of the photocoupler. What is necessary is just to input a 1st clamp control signal and to input a 2nd clamp control signal into the other terminal of a light emitting diode. With this configuration, it is possible to inhibit the timing at which the first clamp control signal and the second clamp control signal are simultaneously turned on. Further, at least one of the first recovery control signal and the second recovery control signal is transmitted through the photocoupler, and the first recovery control signal is input to one terminal of the light emitting diode of the photocoupler to What is necessary is just to input a 2nd collection | recovery control signal into the other terminal. With this configuration, the timing at which the first recovery control signal and the second recovery control signal are simultaneously turned on can be prohibited.

  It should be noted that the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the optimal values according to the panel characteristics, the plasma display device specifications, and the like.

  According to the present invention, since a protection function for accurately controlling the rise time of the sustain pulse and prohibiting an erroneous control signal is added, it is useful as a plasma display device with excellent image display quality and stable operation. .

1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. Panel arrangement of panels used in the plasma display device Circuit block diagram of the plasma display device Circuit diagram showing details of scan electrode drive circuit of same plasma display device Circuit diagram showing details of sustain electrode drive circuit of same plasma display device Drive voltage waveform diagram applied to each electrode of the panel of the plasma display device The figure which shows the voltage waveform of each node of the scanning electrode drive circuit of the plasma display apparatus The figure which shows the control signal and sustain pulse of the sustain pulse generation circuit of the plasma display apparatus Circuit diagram including control signal of scan electrode drive circuit of same plasma display device

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 12 Scan electrode 13 Sustain electrode 14 Display electrode 22 Data electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 40 Scan pulse generation circuit 42, 62 Sustain pulse generation circuit 44, 46 Waveform generation circuit 50, 70 Clamp unit 55, 75 Power recovery unit 64 Voltage generation circuit 81, 82, 84, 85 Level shift circuit 83, 86, 89 Package 87, 88 Photocoupler Q51 Transistor (first) 1 clamp switch)
Q54 transistor (second clamp switch)
Q57 Transistor (first recovery switch)
Q58 transistor (second recovery switch)
Sig51 First clamp control signal Sig54 Second clamp control signal Sig57 First recovery control signal Sig58 Second recovery control signal D87, D88 Light emitting diode

Claims (3)

A plasma display panel having a plurality of discharge cells each having a display electrode, a sustain pulse generating circuit for generating a sustain pulse to be applied to the display electrode, and a timing generating circuit for generating a control signal for controlling the sustain pulse generating circuit A plasma display device comprising:
The sustain pulse generating circuit includes a recovery capacitor, a first recovery switch that increases a voltage of the display electrode by causing a current to flow from the recovery capacitor to the display electrode, and a current that flows from the display electrode to the recovery capacitor. A second recovery switch for reducing the voltage of the display electrode; and connecting the display electrode to a high voltage side of a sustain power source for generating a sustain pulse, and applying a voltage on the high voltage side of the sustain power source to the display electrode. A first clamp switch to be applied, and a second clamp switch for connecting the display electrode to a low voltage side of the sustain power source and applying a voltage on the low voltage side of the sustain power source to the display electrode,
The timing generation circuit controls a first recovery control signal for controlling the first recovery switch, a second recovery control signal for controlling the second recovery switch, and a first for controlling the first clamp switch. And a second clamp control signal for controlling the second clamp switch,
At least one of the first clamp control signal and the second clamp control signal is transmitted via a photocoupler;
The plasma display apparatus, wherein the first clamp control signal is input to one terminal of the light emitting diode of the photocoupler, and the second clamp control signal is input to the other terminal of the light emitting diode. At least one of the first recovery control signal and the second recovery control signal is transmitted via a photocoupler;
2. The first recovery control signal is input to one terminal of the light emitting diode of the photocoupler, and the second recovery control signal is input to the other terminal of the light emitting diode. Plasma display device. The first recovery control signal and the first clamp control signal are supplied via a level shift circuit housed in one package,
The plasma display apparatus of claim 1, wherein the second recovery control signal and the second clamp control signal are supplied through a level shift circuit housed in one package.

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