JP2010160228A - Plasma display apparatus - Google Patents

Abstract

A plasma display device including a driving circuit capable of generating a ramp waveform voltage while suppressing power consumption is provided.
A scan electrode driving circuit includes a scan pulse generating circuit and a ramp waveform generating circuit, and the scan pulse generating circuit includes a power source E70 having a positive voltage superimposed on a reference potential of the scan pulse generating circuit, The ramp waveform generating circuit 60 is connected to the first ramp waveform generating circuit 61 in which one is connected to the high voltage side of the power supply E70 and the other is connected to the first potential. A second ramp waveform generating circuit 62 connected to a low second potential, and the second ramp waveform generating circuit 62 is constituted by a Miller integrating circuit having a transistor Q62, a capacitor C62, and a constant current circuit 63. The voltage supply circuit 65 further supplies a voltage equal to or lower than the cut-off voltage of the transistor Q62 to the gate terminal of the transistor Q62.
[Selection] Figure 7

Description

  The present invention relates to a plasma display device using a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) includes a front plate on which a plurality of display electrode pairs each composed of a pair of scan electrodes and sustain electrodes are formed, and a plurality of parallel electrodes. A large number of discharge cells are formed between a back plate on which various data electrodes are formed. Then, ultraviolet rays are generated by gas discharge in the discharge cell, and the phosphors of red, green and blue colors are excited and emitted by the ultraviolet rays to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining one subfield to emit light after dividing one field into a plurality of subfields is common. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed. In the address period, address discharge is selectively generated in the discharge cells in accordance with the image to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode to generate a sustain discharge, and the phosphor layer of the corresponding discharge cell emits light to display an image.

In this driving method, in order to generate a weak initializing discharge in the initializing period, and to generate an erasing discharge at the end of the sustaining period, a ramp waveform voltage that gradually increases or decreases is applied to one or both of the display electrode pairs. It was necessary to apply to. In order to stably generate the ramp waveform voltage, conventionally, a Miller integration circuit has been mainly used (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-133914

  However, when a power supply having a high voltage is prepared and a ramp waveform voltage is generated therefrom using a Miller integrating circuit, there is a problem that power consumption increases. Furthermore, with the recent increase in the panel screen, this increase in power consumption cannot be ignored. Since the Miller integrating circuit uses semiconductor elements in the active region, it cannot be used to disperse power consumption by connecting the semiconductor elements in parallel unless semiconductor elements having completely the same characteristics are used. Therefore, when the power increases, the semiconductor elements that can be used are limited, and the heat dissipation design becomes difficult.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a plasma display device including a drive circuit capable of generating a ramp waveform voltage while suppressing power consumption.

  The present invention includes a panel having a plurality of discharge cells having scan electrodes and a scan electrode driving circuit for applying a drive voltage waveform to the scan electrodes, and scanning the scan electrodes with an initialization period in which a ramp waveform voltage is applied to the scan electrodes. A plasma display apparatus configured to display an image by forming a single field using a plurality of subfields each having an address period for applying a pulse and a sustain period for applying a sustain pulse to a scan electrode. A generation circuit and a ramp waveform generation circuit, the scan pulse generation circuit has a positive voltage power source superimposed on the reference potential of the scan pulse generation circuit, and one of the ramp waveform generation circuits is on the high voltage side of the power source A first ramp waveform generating circuit connected to the first potential and the other connected to the reference potential and a second connected to the second potential lower than the first potential. A second ramp waveform generation circuit including a transistor, a capacitor, and a constant current circuit, and supplying a voltage equal to or lower than the cutoff voltage of the transistor to the gate terminal of the transistor. A voltage supply circuit is further provided. With this configuration, it is possible to provide a plasma display device including a drive circuit that can generate a ramp waveform voltage while suppressing power consumption.

  The plasma display apparatus of the present invention operates the first ramp waveform generation circuit to lower the reference potential at the first speed, and then operates the second ramp waveform generation circuit to operate the reference at the second speed. It is desirable to lower the potential.

  The power source of the plasma display device of the present invention may be a bootstrap power source having a capacitor and a diode.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the plasma display apparatus provided with the drive circuit which can generate a ramp waveform voltage, suppressing power consumption.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  As shown in FIG. 1 and FIG. 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance. An interelectrode capacitance also exists between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Therefore, scan electrodes SC1 to SCn are capacitive loads having a large equivalent capacitance Cp.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display apparatus displays an image by subfield method, that is, by dividing one field into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, an initializing discharge is generated, and an initializing operation for forming wall charges necessary for the subsequent address discharge on each electrode is performed. The initializing operation at this time includes all-cell initializing operation in which initializing discharge is generated in all discharge cells, and selective initializing operation in which initializing discharge is generated in the discharge cell that has undergone sustain discharge in the immediately preceding subfield. There is. In the address period, an address operation is performed in which address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, sustain pulses of the number corresponding to the luminance weight determined in advance for each subfield are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells in which the address discharge has been generated. .

  As a subfield configuration, for example, one field is divided into ten subfields (first SF, second SF,..., Tenth SF), and each subfield is (1, 2, 3, 6, 11, 18, 30, 44, 60, 80). In addition, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. However, the present invention is not limited to the subfield configuration described above. Note that an initialization period for performing the all-cell initialization operation is an all-cell initialization period, and an initialization period for performing the selective initialization operation is a selection initialization period.

  FIG. 3 is a waveform diagram of driving voltage applied to each electrode of the plasma display device in accordance with the exemplary embodiment of the present invention.

  In the first half of the initializing period of the first SF, voltage 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the scan electrodes SC1 to SCn are discharged to the sustain electrodes SU1 to SUn. An upward ramp waveform voltage that gently rises from a voltage Vi1 equal to or lower than the start voltage toward a voltage Vi2 that exceeds the discharge start voltage is applied. While the rising ramp waveform voltage rises, weak initialization discharges occur between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn and data electrodes D1 to Dm, respectively. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer 33 covering the electrode, the protective layer 26, the phosphor layer 35, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and discharge start voltage is applied to scan electrodes SC1 to SCn from voltage Vi3 that is equal to or lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn. A downward ramp waveform voltage that gently falls toward the voltage Vi4 exceeding the threshold voltage is applied. During this time, weak initialization discharges occur between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Then, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for generating the initializing discharge in all the discharge cells is completed.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Next, a negative scan pulse having a voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes D1 to Dm. ) Is applied with a positive address pulse having a voltage Vd. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference between the externally applied voltages (Vd−Va). Addition exceeds the discharge start voltage. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative wall is applied on sustain electrode SU1. A voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and a sustain pulse of voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. At this time, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk.

  However, the sustain discharge does not occur in the discharge cells that did not cause the address discharge in the address period, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi.

  At the end of the sustain period, an erase waveform is applied to scan electrodes SC1 to SCn to erase the wall voltage on scan electrode SCi and sustain electrode SUi while leaving the positive wall voltage on data electrode Dk. ing. Specifically, after sustain electrodes SU1 to SUn are returned to voltage 0 (V), an upward ramp waveform voltage that gently rises to voltage Vr is applied to scan electrodes SC1 to SCn. Then, a weak discharge occurs between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred, and the wall voltage between scan electrode SCi and sustain electrode SUi is weakened. Thereafter, the voltage applied to scan electrodes SC1 to SCn is returned to voltage 0 (V). Thus, the maintenance operation in the maintenance period is completed.

  In the initialization period of the second SF, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn gradually drop from voltage 0 (V) toward voltage Vi4 exceeding the discharge start voltage. Apply a falling ramp waveform voltage. In the meantime, in the discharge cells in which the sustain discharge is performed in the sustain period of the first SF, weak initializing discharges are respectively generated between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn and data electrode Dk. Occur. Then, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrode Dk is adjusted to a value suitable for the write operation. In the discharge cells in which the sustain discharge is not performed in the sustain period of the first SF, the initialization discharge does not occur and the wall voltage before that is stored.

  Thus, the selective initializing operation for generating the initializing discharge in the discharge cell that has generated the sustaining discharge in the immediately preceding subfield is completed.

  The subsequent second field writing period, sustain period, and subsequent subfield operations are performed in substantially the same manner as described above, except that the number of sustain pulses corresponding to the luminance weight of each subfield is used. Description is omitted.

  In this embodiment, the voltage values applied to the electrodes are, for example, voltage Vi1 = 140 (V), voltage Vi2 = 430 (V), voltage Vi3 = 200 (V), and voltage Vi4 = −195 (V). , Voltage Vc = −60 (V), voltage Va = −200 (V), voltage Vs = 200 (V), voltage Vr = 200 (V), voltage Ve1 = 130 (V), voltage Ve2 = 140 (V) The voltage Vd is 70 (V). However, these voltage values are merely an example, and it is desirable to set them to optimal values as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.

  Next, a driving circuit for driving the panel 10 and its operation will be described. FIG. 4 is a circuit block diagram of plasma display device 40 in accordance with the exemplary embodiment of the present invention. The plasma display device 40 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the synchronization signal, and supplies it to each circuit block. Scan electrode driving circuit 43 drives each of scan electrodes SC1 to SCn based on the timing signal. Sustain electrode drive circuit 44 drives sustain electrodes SU1 to SUn based on the timing signal.

  FIG. 5 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 40 in accordance with the exemplary embodiment of the present invention.

  Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, upward ramp waveform generation circuit 55, downward ramp waveform generation circuit 60, and scan pulse generation circuit 70.

  Sustain pulse generating circuit 50 clamps scan electrodes SC1 to SCn at voltage Vs or voltage 0 (V), and power recovery circuit 51 for collecting and reusing power when driving scan electrodes SC1 to SCn. And a sustain circuit to be applied to scan electrodes SC1 to SCn during the sustain period.

  The up-slope waveform generating circuit 55 includes a Miller integrating circuit 56 and a switch 57 that connects the Miller integrating circuit 56 to the power source of the voltage Vset or the power source of the voltage Vr. Here, the switching elements Q91 and Q92 are separation switches, and are provided in order to prevent a current from flowing back through the parasitic diode of the transistor constituting the scan electrode driving circuit 43. Then, the rising ramp waveform generating circuit 55 generates the rising ramp waveform voltage applied to the first half of the initialization period and the rising ramp waveform voltage applied at the end of the sustain period.

  It should be noted that the circuit configurations of sustain pulse generating circuit 50 and rising ramp waveform generating circuit 55 shown in FIG. 5 are merely examples, and the present invention is not limited to this.

  The scan pulse generating circuit 70 supplies a positive voltage Vscn power source E70 superimposed on the reference potential of the scan pulse generating circuit 70 (the potential of the node indicated by “A” in FIG. 5), and a high voltage side voltage of the power source E70. Switching elements Q71H1 to Q71Hn to be applied to scan electrodes SC1 to SCn, switching elements Q71L1 to Q71Ln for applying a voltage on the low voltage side of power supply E70 to scan electrodes SC1 to SCn, and a switching element for clamping the reference potential to negative voltage Va Q72. Scan pulse generation circuit 70 sequentially applies scan pulses to each of scan electrodes SC1 to SCn in the address period, and sustain pulse generation circuit 50, up-slope waveform generation circuit 55, or down-slope waveform in the initialization period and the sustain period. The output of generation circuit 60 is applied to each of scan electrodes SC1 to SCn.

  The power supply E70 may be configured using a DC-DC converter or the like, but in this embodiment, the power supply E70 is configured using a bootstrap circuit having a capacitor and a diode.

  The switching element Q72 can be shared with a transistor Q62 described later.

  The downward slope waveform generation circuit 60 includes a first Miller integration circuit 61 as a first slope waveform generation circuit, a second Miller integration circuit 62 as a second slope waveform generation circuit, and a backflow prevention diode D61. And generating a falling ramp waveform voltage to be applied in the latter half of the all-cell initializing period and the selective initializing period. The first Miller integrating circuit 61 includes a transistor Q61, a capacitor C61, and a resistor R61, one of which is connected to the high voltage side of the power supply E70 and the other is connected to the ground potential which is the first potential. Then, the potential on the high voltage side of the power supply E70 is gradually lowered toward the ground potential. The second Miller integrating circuit 62 includes a transistor Q62, a capacitor C62, and a resistor R62, one connected to the reference potential of the scan pulse generating circuit 70 and the other connected to the negative voltage Va which is the second potential. Yes. Then, the reference potential of the scan pulse generation circuit 70 is gradually lowered toward the voltage Va.

  In the present embodiment, the voltage value of each power source is, for example, voltage Vset = 290 (V), voltage Vs = 200 (V), voltage Vr = 200 (V), voltage Vscn = 140 (V), voltage Va = −200 (V). The voltage Vi1 = the voltage Vscn, the voltage Vi2 = the voltage Vscn + the voltage Vset, the voltage Vi3 = the voltage Vs, the voltage Vi4 = the voltage Va + 5 (V), and the voltage Vc = the voltage Va + the voltage Vscn. However, these voltage values are merely an example, and it is desirable to set them to optimum values as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device 40.

Next, the operation of the scan electrode drive circuit 43 will be described with a focus on the downward slope waveform generation circuit 60 which is the main point of the present invention. FIG. 6 is a diagram showing the operation of scan electrode drive circuit 43 during the selective initialization period of plasma display device 40 in accordance with the exemplary embodiment of the present invention. FIG. 6 (a) shows the reference potential and power supply of scan pulse generation circuit 70. FIG. 6B shows the drain current _ID1 of the transistor Q61, and FIG. 6C shows the drain current _ID2 of the transistor Q62.

First, at the beginning of the selective initialization period, switching elements Q71H1 to Q71Hn are off, switching elements Q71L1 to Q71Ln are on, and the reference potential of scan pulse generating circuit 70 is voltage 0 (V). This voltage 0 (V) is applied to scan electrodes SC1 to SCn via switching elements Q71L1 to Q71Ln. Therefore, the potential on the high voltage side of the power supply E70 is the voltage Vscn, and the drain current I _D1 of the transistor Q61 and the drain current I _D2 of the transistor Q62 are both “0”. Then, switching elements Q91 and Q92, which are separation switches, are turned off, and switching element Q72 is turned off.

At time t1, a predetermined potential is applied to the resistor R61 to operate the first Miller integrating circuit 61. Then, the potential on the high voltage side of the power supply E70, which is the output of the first Miller integrating circuit 61, starts to decrease at a first speed determined from the current flowing through the resistor R61 and the capacitance of the capacitor C61. At this time, current I _D1 flows from equivalent capacitance Cp of scan electrodes SC1 to SCn to ground potential via switching elements Q71L1 to Q71Ln, power supply E70, diode D61, and transistor Q61.

At time t2, when the potential on the high voltage side of the power supply E70 decreases to near the ground potential and the reference potential decreases to near the voltage (−Vscn), the first Miller integrating circuit 61 can further decrease the output voltage. Disappear. Therefore, a predetermined potential is applied to the resistor R62 to operate the second Miller integrating circuit 62. Then, the output of the second Miller integrating circuit 62, that is, the reference potential of the scan pulse generating circuit 70 starts to decrease at a second speed determined by the current flowing through the resistor R62 and the capacitance of the capacitor C62. At this time, current _ID2 flows from equivalent capacitance Cp of scan electrodes SC1 to SCn to power supply of voltage Va via switching elements Q71L1 to Q71Ln and transistor Q62. Then, at time t3, the reference potential decreases to the voltage Vi4. In the present embodiment, in order to stably generate the address discharge, a ramp waveform voltage that decreases to a voltage Vi4 slightly higher than the voltage Va is applied to scan electrodes SC1 to SCn.

  Thus, in the present embodiment, the downward ramp waveform generation circuit 60 is a first ramp waveform generation circuit (that is, one connected to the high voltage side of the power supply E70 and the other connected to the ground potential which is the first potential (ie, the first ramp waveform generation circuit). A first Miller integrating circuit 61) and a second ramp waveform generating circuit (ie, one connected to a reference potential and the other connected to a power source of a voltage Va which is a second potential lower than the first potential) A second Miller integrating circuit 62), and the first Miller integrating circuit 61 is operated while the reference potential of the scan pulse generating circuit 70 is lowered from the voltage 0 (V) to the voltage (−Vscn). The reference potential is gradually lowered at a speed of ½ and while the voltage (−Vscn) is lowered from the voltage Vi4, the second Miller integration circuit 62 is operated to gradually lower the reference potential at the second speed. .

Next, the power consumption of the transistors Q61 and Q62 is estimated. Since no current flows through the transistor Q62 during the period from the time t1 to the time t2, the power consumption of the transistor Q62 is “0”. On the other hand, a constant current I _D1 flows through the transistor Q61, and the drain-source voltage V _DS1 of the transistor Q61 decreases from the voltage Vscn to almost the voltage 0 (V). The current I _D1 uses the equivalent capacitance Cp,
I _D1 = Cp · dV _DS1 / dt
It can be expressed as
^{_{∫I D1 V DS1 dt = CpV DS1}} 2/2
Next, the power consumption of the transistor Q61 is CpVscn ^2/2.

Since no current flows through the transistor Q61 during the period from time t2 to time t3, the power consumption of the transistor Q61 is “0”. Meanwhile, the voltage _{V DS2} between the drain and source of the transistor Q62 with the transistor Q62 flows through a constant current _{I D2} decreases from voltage (-Vscn-Va) to a voltage (Vi4-Va). The difference between the voltage Vi4 and the voltage Va is so small that it can be ignored.
^{_{∫I D2 V DS2 dt = CpV DS2}} 2/2
In the power consumption of the transistor Q62 represented is, Cp ^(-Vscn-Va) is a 2/2.

Here, it is assumed that the voltage of the reference potential is reduced from the voltage 0 (V) to the voltage Va by using only one Miller integrating circuit in order to estimate the power consumption of the downward ramp waveform generation circuit in the conventional plasma display device. Then, the power consumption of the transistor is ^{Cp (0-Va) 2/} 2.

  Substituting voltage Vscn = 140 (V) and voltage Va = −200 (V), the power consumption of the transistor of the conventional plasma display device and the power consumption of the transistors Q61 and Q62 of the plasma display device 40 of the present embodiment And the power consumption of the transistor of the conventional plasma display device is 20000 × Cp.

  On the other hand, the power consumption of the transistor Q61 of the plasma display device 40 of the present embodiment is 9800 × Cp, and the power consumption of the transistor Q62 is 1800 × Cp. Thus, the power consumption of the transistor Q61 is about ½ of that of the conventional transistor, and the power consumption of the transistor Q62 is about 1/10 of that of the conventional transistor. It can be seen that the total power consumption is reduced by about half.

  As described above, the downward ramp waveform generation circuit 60 in the present embodiment includes the first Miller integration circuit 61 connected to the high voltage side of the power supply E70 superimposed on the reference potential of the scan pulse generation circuit 70, and And a second Miller integrating circuit 62 connected to the reference potential, and driving them in a time-sharing manner, thereby suppressing the power consumption of the entire downward ramp waveform generating circuit 60 and at the same time the transistor Q61 of each Miller integrating circuit. The power consumption is distributed to the transistor Q62.

  It should be noted that there is a time delay after the first Miller integrating circuit 61 stops and before the second Miller integrating circuit 62 starts operating. This time delay occurs because it takes a certain amount of time for the gate voltage of the transistor Q62 to rise. This time delay can be shortened by increasing the gate voltage of the transistor Q62 of the second Miller integrating circuit 62 in advance during the operation of the first Miller integrating circuit 61. A specific circuit example will be described below.

  FIG. 7 is a circuit diagram of the downward ramp waveform generation circuit 60 in the embodiment of the present invention. As shown in FIG. 7, the downward slope waveform generation circuit 60 includes a first Miller integration circuit 61, a second Miller integration circuit 62, and a backflow prevention diode D61. In addition, FIG. 7 shows a constant current circuit 63 and a voltage dividing circuit 65 as a voltage supply circuit. The power supply E70 is shown as a bootstrap power supply having a capacitor C70 and a diode D70.

  The first Miller integrating circuit 61 is controlled by the control signal sig61. By setting the control signal sig61 to a predetermined potential, the potential of the output of the transistor Q61 is reduced at a speed determined by the current flowing through the resistor R61 and the capacitance of the capacitor C61. Can be made.

  The second Miller integrating circuit 62 shown in FIG. 7 includes a constant current circuit 63 instead of the resistor R62. The constant current circuit 63 includes a transistor Q63, a Zener diode D63, a resistor R63, and a resistor R64. Then, by setting the control signal sig 62a to a predetermined potential, the constant current circuit 63 operates as a constant current source determined by the voltage of the Zener diode D63 and the resistance value of the resistor R63, and the current flowing through the constant current circuit 63 and the capacitor C62 The potential of the output of the transistor Q62 can be lowered at a speed determined from the capacitance.

  The voltage dividing circuit 65 includes a transistor Q65, a resistor R65, and a resistor R66. Then, the potential of the control signal sig62b is divided by the resistors R65 and R66, impedance-converted by the transistor Q65, and output to the gate of the transistor Q62. Here, the potential of the control signal sig62b is set so that the output voltage of the voltage dividing circuit 65 is equal to or lower than the cut-off voltage of the transistor Q62, and the transistor Q62 cannot be turned on by the control signal sig62b. However, by adding this voltage dividing circuit 65, the time delay until the second Miller integrating circuit 62 starts operating can be shortened.

  FIG. 8 is a timing chart for explaining the operation of the downward ramp waveform generation circuit 60 of the plasma display device 40 according to the embodiment of the present invention. FIG. 8A shows the voltage of the reference potential of the scan pulse generation circuit 70. ing. 8B shows the control signal sig61, FIG. 8C shows the gate-source voltage Vgs1 of the transistor Q61, FIG. 8D shows the control signal sig62a, and FIG. 8E shows the control signal. FIG. 8F shows the gate-source voltage Vgs2 of the transistor Q62.

  When the control signal sig61 is set to a predetermined potential at time t11, a constant current starts to flow through the resistor R61, and the gate-source voltage Vgs1 of the transistor Q61 starts to rise. At time t12, when the gate-source voltage Vgs1 exceeds the cutoff voltage, a current flows between the drain and source of the transistor Q61, and the transistor Q61 operates as the first Miller integrating circuit 61.

  At this time, the control signal sig62b is also set to a predetermined potential. Then, the voltage dividing circuit 65 divides the voltage of the control signal sig62b to increase the gate-source voltage Vgs2 of the transistor Q62. However, since this voltage is set to be equal to or lower than the cut-off voltage of transistor Q62, no current flows between the drain and source of transistor Q62.

  At time t13, the control signal sig61 is set to voltage 0 (V), and the control signal sig62a is set to a predetermined potential. Then, a constant current starts to flow through the constant current circuit 63, and the gate-source voltage Vgs2 of the transistor Q62 begins to rise. However, since the gate-source voltage Vgs2 of the transistor Q62 has already risen to near the cutoff voltage, the gate-source voltage Vgs2 immediately exceeds the cutoff voltage at time t14. Then, current flows between the drain and source of the transistor Q62, and the transistor Q62 operates as the second Miller integrating circuit 62.

  If it is assumed that the voltage dividing circuit 65 is not provided, the gate-source voltage Vgs2 of the transistor Q62 at time t13 is the voltage 0 (V). Therefore, it takes time until the gate-source voltage Vgs2 exceeds the cut-off voltage, and the operation as the Miller integrating circuit starts at time t15 after time t14, as indicated by a broken line in FIG.

  However, in the present embodiment, the gate terminal of the transistor Q62 constituting the second Miller integrating circuit 62 is provided with a voltage supply circuit (that is, a voltage dividing circuit 65) that supplies a voltage equal to or lower than the cut-off voltage of the transistor Q62. Since the gate-source voltage Vgs2 of the transistor Q62 is increased in advance, the operation of the second Miller integrating circuit 62 can be started immediately after the first Miller integrating circuit 61 is stopped.

  In this embodiment, the control signal sig61 and the control signal sig62b are provided independently. However, the control signal sig61 and the control signal sig62b may be a common control signal. For example, the control signal sig61 is level-shifted. The control signal sig62b may be used.

  In the present embodiment, the reference potential of the scan pulse generation circuit 70 has been described as being lowered from the initial voltage 0 (V). However, if the potential on the high voltage side of the power supply E70 is positive, the initial voltage is the voltage. A voltage other than 0 (V) may be used.

  6 and 8 show drawings in which the voltage drop rates of the first Miller integrating circuit 61 and the second Miller integrating circuit 62 are approximately the same, but the present invention is limited to this. It is not a thing. As is clear from the method of estimating power consumption, power consumption depends on the voltage Vscn, the voltage Va, and the equivalent capacitance Cp, but does not depend on the drop rate. Therefore, the voltage drop rate of each Miller integrating circuit may be arbitrarily set according to the characteristics of the panel 10 or the like.

  FIG. 9 is a diagram showing the shape of the downward ramp waveform voltage of the plasma display device according to another embodiment of the present invention. In the embodiment shown in FIG. 9, the first Miller integrating circuit 61 reduces the reference potential from the voltage 0 (V) to the vicinity of the voltage (−Vscn) at the first speed 8.0 (V / μs). Thereafter, the second Miller integration circuit 62 is used to reduce the speed at the second speed 2.5 (V / μs), and then the second Miller integration circuit 62 is used to reduce the third speed 1.0. The voltage is reduced to voltage Vi4 at (V / μs). As described above, by reducing the voltage at a relatively high speed at first and at a low speed thereafter, the driving time can be shortened while generating a stable initializing discharge.

FIG. 10 is a circuit diagram of the constant current circuit 163 of the descending ramp waveform generating circuit 60 of the plasma display device in another embodiment of the present invention. The constant current circuit 163 includes a transistor Q63, a variable shunt regulator IC 163, a resistor R64, a variable resistor VR165, a resistor R166, a resistor R167, and a switch S167. When the switch S167 is turned off, by setting the control signal sig62a to the “H” level, a current determined by the voltage of the variable shunt regulator IC 163 and the resistance value of the resistor R166 flows into the capacitor C62. The voltage at the node A drops at a speed determined from the capacitance of the capacitor C62. That is, the voltage drop rate dV / dt is
dV / dt = V163 / (c62 · r166)
It is. In the above equation, V163 is the voltage of the variable shunt regulator IC 163, c62 is the capacitance of the capacitor C62, and r166 is the resistance value of the resistor R166. The base-emitter voltage of transistor Q63 was ignored.

When the switch S167 is turned on, the control signal sig62a is set to the “H” level so that a current determined by the voltage of the variable shunt regulator IC163 and the resistance value of the parallel resistance of the resistor R166 and the resistor R167 is supplied to the capacitor C62. The voltage at the node A drops at a speed determined by this current and the capacitance of the capacitor C62. That is, the voltage drop rate dV / dt is
dV / dt = V163 / {c62 · r166 · r167 / (r166 + r167)}
It is. Where V163 is the voltage of the variable shunt regulator IC163, c62 is the capacitance of the capacitor C62, r166 is the resistance value of the resistor R166, and r167 is the resistance value of the resistor R167. Again, the base-emitter voltage of transistor Q63 was ignored.

  As described above, the constant current circuit 163 of the downward ramp waveform generation circuit 60 includes the variable shunt regulator IC 163 that is a variable voltage source and the resistor connected thereto, and switches the resistance value of the resistor connected to the variable shunt regulator IC 163. By switching at S167, the speed at which the voltage at the node A decreases can be switched. Furthermore, by setting the resistance value of the resistor R166 and the resistance value of the resistor R167 with high precision, the second speed and the third speed that are the voltage drop speed of the node A are adjusted by adjusting one variable resistor VR165. At the same time, it can be adjusted accurately.

  When the voltage at the node A is further reduced at the fourth speed using the second Miller integrating circuit 62, a series circuit of a resistor and a switch is further connected in parallel with the resistor R166 as shown by a broken line in FIG. Connect to

  In addition, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the optimal values according to the characteristics of the panel 10 and the specifications of the plasma display device. .

  The present invention can generate a ramp waveform voltage while suppressing power consumption, and is useful as a plasma display device.

1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. Panel arrangement of panels used in the plasma display device Drive voltage waveform diagram applied to each electrode of the plasma display device Circuit block diagram of the plasma display device Circuit diagram of scan electrode driving circuit of same plasma display device The figure which shows the operation | movement of the scanning electrode drive circuit in the selective initialization period of the plasma display apparatus Circuit diagram of descending ramp waveform generation circuit in the plasma display device Timing chart for explaining the operation of the downward ramp waveform generation circuit of the plasma display device The figure which shows the shape of the downward gradient waveform voltage of the plasma display apparatus in other embodiment of this invention. Circuit diagram of constant current circuit of descending ramp waveform generation circuit of plasma display device

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50 Sustain pulse generation circuit 51 Power Recovery circuit 52 Clamp circuit 55 Up slope waveform generation circuit 56 Miller integration circuit 57 Switch 60 Down slope waveform generation circuit (slope waveform generation circuit)
61 First Miller integrating circuit (first ramp waveform generating circuit)
62 Second Miller integrating circuit (second ramp waveform generating circuit)
63,163 Constant current circuit 65 Voltage divider circuit (voltage supply circuit)
70 Scanning pulse generator

Claims (3)

A plasma display panel having a plurality of discharge cells each having a scan electrode; a scan electrode driving circuit for applying a drive voltage waveform to the scan electrode; an initialization period for applying a ramp waveform voltage to the scan electrode; and the scan A plasma display apparatus configured to display an image by forming one field using a plurality of subfields having an address period in which a scan pulse is applied to an electrode and a sustain period in which a sustain pulse is applied to the scan electrode,
The scan electrode drive circuit has a scan pulse generation circuit and a ramp waveform generation circuit,
The scan pulse generation circuit has a positive voltage power source superimposed on a reference potential of the scan pulse generation circuit,
The ramp waveform generation circuit includes a first ramp waveform generation circuit in which one is connected to the high voltage side of the power supply and the other is connected to the first potential, and one is connected to the reference potential and the other is the first A second ramp waveform generation circuit connected to a second potential lower than the potential,
The second ramp waveform generating circuit includes a Miller integrating circuit including a transistor, a capacitor, and a constant current circuit, and further includes a voltage supply circuit that supplies a voltage not higher than a cutoff voltage of the transistor to the gate terminal of the transistor. A plasma display device comprising: Operating the first ramp waveform generation circuit to lower the reference potential at a first speed, and then operating the second ramp waveform generation circuit to lower the reference potential at a second speed. The plasma display device according to claim 1. The plasma display apparatus according to claim 1, wherein the power source is a bootstrap power source having a capacitor and a diode.

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