JP2010164742A - Plasm display - Google Patents

Abstract

A plasma display device including a novel sustain electrode driving circuit using a transistor with a low withstand voltage is provided.
A sustain electrode driving circuit includes: a first switch connected to a power supply having a first voltage; a second switch connected to a power supply having a second voltage lower than the first voltage; And a third switch 60 connected to the power source of the third voltage Ve lower than the first voltage and higher than the second voltage, and the third switch 60 has a drain connected to the power source of the third voltage Ve. First transistor Q61, a second transistor Q62 having a drain connected to the output terminal N0 and a source connected to the source of the first transistor Q61, and the source of the first transistor Q61 or the second transistor Q62. And a breakdown voltage compensating capacitor C78 having one terminal connected to the floating power supply and the other terminal connected to the output terminal N0.
[Selection] Figure 5

Description

  The present invention relates to a plasma display device which is an image display device using a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate which are arranged to face each other. On the front substrate, a plurality of display electrode pairs including a pair of scan electrodes and sustain electrodes are formed in parallel to each other, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. A plurality of parallel data electrodes, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes are formed on the back substrate, respectively. A phosphor layer is formed on the side surface. Then, the front substrate and the rear substrate are disposed opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and red, green, and blue phosphors are excited and emitted by the ultraviolet light to perform color display.

  As a method for driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. The subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization voltage is applied to each electrode to form wall charges necessary for the subsequent address operation. In the address period, a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode to cause an address discharge in the discharge cell to be displayed. In the sustain period, a sustain pulse is alternately applied to the scan electrode and the sustain electrode, a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell is caused to emit light, thereby displaying an image. .

  As described above, the plasma display device is provided with a drive circuit for each electrode in order to drive each electrode of the panel, and these electrode drive circuits are configured using many transistors (for example, see Patent Document 1). ).

However, since a high voltage is applied to these transistors, a drive circuit must be configured using high-breakdown-voltage transistors, and many transistors are connected in parallel because the high-breakdown-voltage transistors have high on-resistance. It was necessary to lower the output impedance. In particular, a scan electrode drive circuit has been proposed that can lower the breakdown voltage of a transistor of a scan electrode drive circuit that tends to have a complicated circuit configuration (see, for example, Patent Document 2).
JP 2005-266460 A Japanese Patent Laid-Open No. 2006-201735

  However, with regard to the sustain electrode drive circuit having a simpler circuit configuration than the scan electrode drive circuit, there has not been much study on lowering the breakdown voltage of the transistor.

  On the other hand, with the recent trend toward larger screen panels, the demand for thinner, lighter, and lower-power image display devices has become stronger. Also for the electrode drive circuit, there is an increasing need to lower the voltage of components as much as possible.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a plasma display device including a novel sustain electrode driving circuit using a transistor having a low breakdown voltage.

  In order to achieve the above object, a plasma display apparatus according to the present invention includes a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a sustain electrode that generates a drive voltage waveform applied to the sustain electrode. And the sustain electrode driving circuit includes a first switch having one terminal connected to the power source of the first voltage and the other terminal connected to the output terminal, and one terminal from the first voltage. A second switch having a lower second voltage connected to the output terminal and the other terminal connected to the output terminal; and a third switch having one terminal lower than the first voltage and higher than the second voltage. And a third switch having the other terminal connected to the output terminal, the third switch having a drain connected to the power supply of the third voltage and a drain connected to the output terminal. Connected and source is first A second transistor connected to the source of the transistor, a floating power supply connected to the source of the first transistor or the source of the second transistor, one terminal connected to the floating power supply and the other terminal to the output terminal And a withstand voltage compensation capacitor connected thereto. With this configuration, it is possible to provide a plasma display device including a novel sustain electrode driving circuit using a transistor with a low breakdown voltage.

  In addition, the plasma display device of the present invention includes a panel including a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and a sustain electrode drive circuit that generates a drive voltage waveform applied to the sustain electrode, The sustain electrode driving circuit includes a first switch having one terminal connected to the power supply of the first voltage and the other terminal connected to the output terminal, and a second voltage having one terminal lower than the first voltage. A second switch having the other terminal connected to the output terminal and one terminal connected to a power supply having a third voltage lower than the first voltage and higher than the second voltage. A third switch connected to the output terminal, the third switch having a collector connected to the power supply of the third voltage, a collector connected to the output terminal, and an emitter first. Transistor transistor A second transistor connected to the power supply, a floating power supply connected to the emitter of the first transistor or the emitter of the second transistor, one terminal connected to the floating power supply, and the other terminal connected to the output terminal It is also possible to have a configuration having a withstand voltage compensation capacitor.

  The breakdown voltage of the second transistor of the plasma display device of the present invention may be smaller than the voltage difference between the first voltage and the second voltage.

  The capacitance of the withstand voltage compensation capacitor of the plasma display device of the present invention is preferably 2 to 5 times the parasitic capacitance between the drain and source of the first transistor.

  The capacitance of the withstand voltage compensation capacitor of the plasma display device of the present invention is preferably 2 to 5 times the parasitic capacitance between the collector and the emitter of the first transistor.

  According to the present invention, it is possible to provide a plasma display device including a novel sustain electrode driving circuit using a transistor having a low breakdown voltage.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. For example, a discharge gas containing xenon is enclosed in the discharge space. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, the configuration and operation of the plasma display device in the present embodiment will be described.

  FIG. 3 is a circuit block diagram of plasma display device 40 in accordance with the exemplary embodiment of the present invention. The plasma display device 40 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. 46 is provided.

  The image signal processing circuit 41 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and the light emission / non-light emission in each of the subfields is set to “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 42 converts the image data into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to each circuit block. Scan electrode drive circuit 43 generates a drive voltage waveform based on the timing signal, and drives scan electrodes SC1 to SCn. Sustain electrode drive circuit 44 generates a drive voltage waveform based on the timing signal, and drives sustain electrodes SU1 to SUn.

  The power supply circuit 46 includes a power supply 47 that supplies the first voltage Vs to the sustain electrode drive circuit 44 and a power supply 48 that supplies the third voltage Ve. In the present embodiment, the second voltage is the GND potential, that is, the voltage 0 (V). Hereinafter, the first voltage Vs is simply abbreviated as “voltage Vs”, and the third voltage Ve is simply abbreviated as “voltage Ve”.

  FIG. 4 is a circuit diagram showing details of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the exemplary embodiment of the present invention. Sustain electrode driving circuit 44 generates sustain pulse generating circuit 50 for generating sustain pulses to be applied to sustain electrodes SU1 to SUn based on power supply 47, and Ve voltage for generating voltage Ve to be applied to sustain electrodes SU1 to SUn based on power supply 48. And a generation circuit 60.

  The sustain pulse generation circuit 50 includes a power recovery unit 51 and a clamp unit 54. The clamp unit 54 includes a transistor Q55 that clamps the output to the voltage Vs of the power supply 47, and a transistor Q56 that clamps the output to the GND potential, that is, the voltage 0 (V). The node that is the output terminal of sustain pulse generating circuit 50 is hereinafter referred to as “node N0”.

  In the present embodiment, the first switch having one terminal connected to the power source of the voltage Vs and the other terminal connected to the node N0 is the transistor Q55, and the second switch has a second voltage lower than the voltage Vs. The transistor Q56 is a second switch that is connected to the 0 (V) power supply GND and has the other terminal connected to the node N0.

  As the transistors Q55 and Q56, an insulated gate bipolar transistor (IGBT), a field effect transistor (FET), or the like can be used. In this embodiment, an IGBT is used. Diodes D55 and D56 for bypassing the current from the emitter to the collector are connected in parallel to the transistors Q55 and Q56, respectively.

  The power recovery unit 51 includes a power recovery capacitor C51, a transistor Q51 and a diode D51 connected in series to form a current path through which a current flows from the power recovery capacitor C51 to the sustain electrodes SU1 to SUn. In order to form a current path through which a current flows from the electrodes SU1 to SUn to the power recovery capacitor C51, a transistor Q52 and a diode D52 connected in series, and a recovery inductor L51 are included. Then, the inter-electrode capacitance Cp and the recovery inductor L51 are LC-resonated so that the sustain pulse rises and falls. The power recovery capacitor C51 has a sufficiently large capacity compared to the interelectrode capacitance Cp, and is charged to about Vs / 2, which is half of the voltage Vs, so as to serve as a power source for the power recovery unit 51.

  The Ve voltage generation circuit 60 includes a first transistor Q61 and a second transistor Q62 that perform output control of the voltage Ve, and an output control unit 70 that performs on / off control of the first transistor Q61 and the second transistor Q62. It has.

  In the present embodiment, the Ve voltage generation circuit 60 is a third switch in which one terminal is connected to the power source 48 having a voltage Ve lower than the voltage Vs and higher than the voltage 0 (V) and the other terminal is connected to the node N0. is there. The first transistor whose drain is connected to the power source 48 of the voltage Ve is the transistor Q61, and the second transistor whose drain is connected to the output terminal N0 and whose source is connected to the source of the first transistor Q61 is the transistor Q62. . Hereinafter, the first transistor Q61 is simply referred to as “transistor Q61”, and the second transistor Q62 is simply referred to as “transistor Q62”.

  As the transistors Q61 and Q62, an insulated gate bipolar transistor (IGBT), a field effect transistor (FET), or the like can be used. In this embodiment, an FET is used. Needless to say, when an IGBT or a normal bipolar transistor is used as the transistors Q61 and Q62, the drain may be replaced with a collector, and the source may be replaced with an emitter. That is, the first transistor whose collector is connected to the power source 48 of the voltage Ve is the transistor Q61, and the second transistor whose collector is connected to the output terminal N0 and whose emitter is connected to the emitter of the first transistor Q61 is the transistor Q62. Become.

  Thus, in the present embodiment, the transistor Q61 and the transistor Q62 are connected in series so that the directions of currents to be controlled are opposite to each other. The node to which the sources are connected is hereinafter referred to as “node N1”. The drain of the transistor Q61 is connected to the power source 48 of the voltage Ve, and the drain of the transistor Q62 is connected to the node N0. Here, the transistor Q62 uses a transistor with a low withstand voltage, as will be described in detail later. In this embodiment, a transistor with a withstand voltage smaller than the voltage Vs is used. The diodes D61 and D62 in FIG. 4 are parasitic diodes of FETs used as the transistors Q61 and Q62.

  FIG. 5 is a circuit diagram illustrating details of the output control unit 70 of the plasma display device 40 according to the embodiment of the present invention. The output control unit 70 includes transistors Q71 and Q72, a diode D75, a capacitor C75, a resistor R75, and a withstand voltage compensation capacitor C78. In FIG. 5, the source-drain parasitic capacitances C61 and C62 associated with the transistors Q61 and Q62 are indicated by broken lines.

  The transistors Q71 and Q72 amplify the control signal sig70 to the transistors Q61 and Q62.

  The diode D75, the capacitor C75, and the resistor R75 constitute a bootstrap power supply and function as a power supply circuit for the output control unit 70. In the present embodiment, the floating power source connected to the source of transistor Q61 or the source of transistor Q62 is a bootstrap power source composed of a diode D75, a capacitor C75, and a resistor R75.

  One terminal of the withstand voltage compensation capacitor C78 is connected to the high voltage side of the bootstrap power supply, and the other terminal is connected to the node N0 which is an output terminal. Therefore, a withstand voltage compensation capacitor C78 and a capacitor C75 connected in series are connected between the drain and source of the transistor Q62. As will be described in detail later, the withstand voltage compensation capacitor C78 lowers the voltage applied between the source and drain of the transistor Q62, so that a transistor with a low withstand voltage can be used as the transistor Q62. Hereinafter, the withstand voltage compensation capacitor C78 is simply referred to as “capacitor C78”.

  Next, the operation of sustain electrode drive circuit 44 will be described together with the method for driving panel 10. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, sustain pulses are alternately applied to the display electrode pairs, and a sustain discharge is generated in the discharge cells that have generated the address discharge to emit light.

  FIG. 6 is a drive voltage waveform diagram applied to each electrode of panel 10 of plasma display device 40 in accordance with the exemplary embodiment of the present invention, and shows drive voltage waveforms of two subfields.

  In the first half of the initialization period, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the transistor Q56 is turned on, and the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn. At this time, a current flows from the power supply of voltage 15 (V) to the capacitor C75 via the diode D75, and the capacitor C75 is charged to the voltage 15 (V). Then, an upward ramp waveform voltage that gently rises from voltage Vi1 to voltage Vi2 is applied to scan electrodes SC1 to SCn.

  While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, and wall voltages are accumulated on the respective electrodes. . Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the second half of the initialization period, the transistor Q56 is turned off, the control signal sig70 is set to the “H” level, the transistors Q61 and Q62 are turned on, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn. A downward ramp waveform voltage that gently falls from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge occurs again between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm while the ramp waveform voltage decreases, and the wall voltage on each electrode is written. It is adjusted to a value suitable for operation.

  In this way, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. Note that, as shown in the initialization period of the second subfield in FIG. 6, the first half of the initialization period may be omitted. In this case, an initializing discharge is selectively generated in a discharge cell that has undergone a sustain discharge in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Vc is applied to scan electrodes SC1 to SCn while voltage Ve is applied to sustain electrodes SU1 to SUn. Thereafter, a scan pulse of negative voltage Va is applied to scan electrode SC1, and positive voltage Vd is applied to data electrode Dk (k = 1 to m) of the discharge cell to be lit in the first row among data electrodes D1 to Dm. Apply the write pulse. Then, among the discharge cells in the first row, a discharge cell to which an address pulse is applied generates a discharge between data electrode Dk and scan electrode SC1, and this discharge extends to a discharge between scan electrode SC1 and sustain electrode SU1. Address discharge occurs. Thus, an address operation for accumulating positive wall voltage on scan electrode SC1 and negative wall voltage on sustain electrode SU1 is performed. On the other hand, no address discharge occurs in the discharge cells to which the address pulse voltage Vd is not applied.

  Next, a scan pulse of voltage Va is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk of the discharge cell to be emitted in the second row among data electrodes D1 to Dm. . Then, address discharge occurs selectively in the discharge cells in the second row. The above address operation is performed up to the discharge cell in the nth row. Then, the control signal sig70 is set to the “L” level to turn off the transistors Q61 and Q62.

  In the subsequent sustain period, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and a sustain pulse of voltage Vs is applied to scan electrodes SC1 to SCn.

  In order to apply the voltage 0 (V) to the sustain electrodes SU1 to SUn, the transistor Q52 is first turned on. Then, current begins to flow from sustain electrodes SU1 to SUn to capacitor C51 for power recovery via inductor L51, diode D52, and transistor Q52, and the voltages of sustain electrodes SU1 to SUn begin to decrease. Since the inductor L51 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes SU1 to SUn drops to near voltage 0 (V) after a time ½ of the resonance period has elapsed.

  Next, the transistor Q56 is turned on. Then, voltage 0 (V) is applied to sustain electrodes SU1-SUn via transistor Q56. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. At this time, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. Thereafter, the transistors Q52 and Q56 are turned off.

  Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn.

  In order to apply the voltage Vs to the sustain electrodes SU1 to SUn, first, the transistor Q51 is turned on. Then, a current starts to flow from the power recovery capacitor C51 via the transistor Q51, the diode D51, and the inductor L51, and the voltages of the sustain electrodes SU1 to SUn begin to rise. Since the inductor L51 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes SU1 to SUn rises to the vicinity of the voltage Vs after the time ½ of the resonance period has elapsed.

  Then, the transistor Q55 is turned on. Then, voltage Vs is applied to sustain electrodes SU1 to SUn.

  In this way, the voltage of sustain electrodes SU1 to SUn is forcibly increased to voltage Vs, and the sustain discharge is generated again in the discharge cell that has caused the address discharge. Thereafter, the transistors Q51 and Q55 are turned off.

  Similarly, the address discharge is applied in the address period by applying sustain pulses of the number corresponding to the luminance weight alternately to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and applying a potential difference between the electrodes of the display electrode pair. The sustain discharge is continuously performed in the discharge cell that has caused the failure.

  Since the operation of the subsequent subfield is substantially the same, the description thereof is omitted.

  In addition, each voltage value of the power supply used in this embodiment is, for example, voltage Vi1 = 140 (V), voltage Vi2 = 430 (V), voltage Vs = 200 (V), voltage Vc = −60 (V), The voltage Va = −200 (V) and the voltage Ve = 140 (V).

  Next, the reason why the Ve voltage generation circuit 60 in this embodiment can be realized by using a low breakdown voltage transistor will be described.

  FIG. 7 is a diagram showing voltages at various parts of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the exemplary embodiment of the present invention. Control signal sig70, voltage at node N0, voltage at node N1, node N0 and node N1 , That is, the voltage applied between the drain and source of the transistor Q62.

  In the first half of the initialization period, since the output voltage of the sustain electrode drive circuit 44, that is, the node N0 is the voltage 0 (V), the parasitic diode D62 is turned on and the node N1 is also reduced to the voltage 0 (V). In the latter half of the initialization period and the writing period, both the transistors Q61 and Q62 are turned on, so that the node N1 is the voltage Ve and the node N0 is also the voltage Ve. When the node N0 becomes the voltage 0 (V) in the next sustain period, the parasitic diode D62 is turned on and the node N1 is also reduced to the voltage 0 (V).

  However, when a sustain pulse is applied to sustain electrodes SU1 to SUn and the voltage at node N0 rises to voltage Vs, both transistors Q61 and Q62 are off, so that node N1 is in a high impedance state. The voltage is determined by the capacity division between the capacity between the power sources of the node N1 and the voltage Ve and the capacity between the nodes N1 and N0.

  In the present embodiment, the capacitance between the node N1 and the node N0 is obtained by adding the series capacitance of the capacitor C75 and the capacitor C78 in addition to the parasitic capacitance C62, and the capacitance between the node N1 and the voltage Ve (parasitic capacitance C61). Therefore, the voltage at the node N0 rises to the voltage Vs and the voltage at the node N1 also rises. Then, when the voltage at the node N1 exceeds the voltage Ve, the parasitic diode D61 is turned on, and the voltage at the node N1 is kept at the voltage Ve. Therefore, the drain-source voltage of transistor Q62 does not exceed voltage (Vs-Ve), and does not exceed voltage 60 (V) in this embodiment. Therefore, according to the present embodiment, an FET having a withstand voltage lower than the voltage Vs can be used as the transistor Q62 even if noise and the like are considered.

  Assuming that the capacitor C78 is not provided, if the parasitic capacitance C61 and the parasitic capacitance C62 are approximately the same, the sustain pulse is applied to the sustain electrodes SU1 to SUn, and the voltage at the node N0 rises to the voltage Vs. At this time, the voltage at the node N1 rises only by about the voltage Vs / 2, and the voltage Vs / 2 is applied between the drain and source of the transistor Q62. If the parasitic capacitance C61 is larger than the parasitic capacitance C62, the voltage at the node N1 hardly rises, and the voltage Vs is applied between the drain and source of the transistor Q62. In this case, as the transistor Q62, it is necessary to use a transistor having a withstand voltage exceeding the voltage Vs, for example, a transistor having a withstand voltage 1.5 times the voltage Vs.

  However, since the capacitor C78 is provided in the present embodiment, when the sustain pulse is applied to the sustain electrodes SU1 to SUn and the voltage at the node N0 rises to the voltage Vs, the voltage at the node N1 is also the node N0. Similarly, the voltage rises to reach the voltage Ve, so that the voltage applied between the drain and the source of the transistor Q62 is equal to or lower than the voltage (Vs−Ve).

  If it is assumed that the capacitor C78 is provided in parallel between the drain and the source of the transistor Q62, the voltage between the drain and the source of the transistor Q62 can be suppressed to the voltage (Vs−Ve). However, when the voltage at the node N0 decreases from the voltage Vs to the voltage 0 (V), the voltage at the node N1 decreases to the voltage 0 (V) or less, and the capacitor C75 of the bootstrap power supply is overcharged, and the output There is a risk of destroying the control unit 70.

  However, according to the present embodiment, since the capacitor C78 is provided between the high voltage side of the bootstrap power supply and the node N0, there is no possibility that the bootstrap power supply is overcharged.

  As described above, in this embodiment, since a voltage equal to or higher than the voltage (Vs−Ve) is not applied to the transistor Q62, a transistor with a very low breakdown voltage can be used. Even in consideration of the possibility that a voltage such as noise is superimposed on the node N1, a transistor having a breakdown voltage smaller than the voltage Vs can be used.

  As described above, the voltage applied to the transistor Q62 can be lowered by setting the capacitance of the capacitor C78 to be equal to or higher than the parasitic capacitance C61. However, since the power for charging and discharging increases as the capacity increases, it is desirable that the capacity of the capacitor C78 be set to be not less than 2 times and not more than 5 times the parasitic capacity C61 between the drain and source of the transistor Q61. In the present embodiment, the parasitic capacitance C61 is 500 pF, the parasitic capacitance C62 is 200 pF, and the capacitance of the capacitor C78 is set to 1000 pF. Further, it is desirable to set the capacity of the capacitor C75 to a certain large capacity in order to operate as a power supply circuit of the output control unit 70 and to use a capacitor having good high frequency characteristics. In the present embodiment, the capacitance of the capacitor C75 is 1 μF, and capacitors having better high frequency characteristics are connected in parallel.

  It should be noted that the specific numerical values used in the present embodiment are merely examples, and it is desirable to set them to optimal values as appropriate in accordance with panel characteristics, plasma display device specifications, and the like.

  The present invention includes a novel sustain electrode driving circuit using a transistor having a low breakdown voltage, and is useful as a plasma display device.

The exploded perspective view of the panel used for the plasma display apparatus in an embodiment of the invention Panel arrangement of panels used in the plasma display device Circuit block diagram of the plasma display device Circuit diagram showing details of sustain electrode drive circuit of same plasma display device Circuit diagram showing details of output control unit of same plasma display device Drive voltage waveform diagram applied to each electrode of the panel of the plasma display device The figure which shows the voltage of each part of the sustain electrode drive circuit of the plasma display apparatus

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 46 Power supply circuit 47 (Voltage Vs Power supply 48 (voltage Ve) power supply 50 sustain pulse generation circuit 51 power recovery unit 54 clamp unit 60 Ve voltage generation circuit (third switch)
70 Output control section Q55 Transistor (first switch)
Q56 transistor (second switch)
Q61 (first) transistor Q62 (second) transistor D75 diode C75 capacitor R75 resistor C78 (withstand voltage compensation) capacitor

Claims (5)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A sustain electrode drive circuit for generating a drive voltage waveform to be applied to the sustain electrode,
The sustain electrode driving circuit includes a first switch having one terminal connected to a power source having a first voltage and the other terminal connected to an output terminal, and a second switch having one terminal lower than the first voltage. A second switch connected to the power supply of the second voltage and the other terminal connected to the output terminal; and one terminal connected to a power supply of the third voltage lower than the first voltage and higher than the second voltage. And the other terminal has a third switch connected to the output terminal,
The third switch includes a first transistor whose drain is connected to the power supply of the third voltage, and a second transistor whose drain is connected to the output terminal and whose source is connected to the source of the first transistor. A transistor, a floating power source connected to the source of the first transistor or the source of the second transistor, and one terminal connected to the floating power source and the other terminal connected to the output terminal for withstand voltage compensation A plasma display device comprising a capacitor. A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A sustain electrode drive circuit for generating a drive voltage waveform to be applied to the sustain electrode,
The sustain electrode driving circuit includes a first switch having one terminal connected to a power source having a first voltage and the other terminal connected to an output terminal, and a second switch having one terminal lower than the first voltage. A second switch connected to the power supply of the second voltage and the other terminal connected to the output terminal; and one terminal connected to a power supply of the third voltage lower than the first voltage and higher than the second voltage. And the other terminal has a third switch connected to the output terminal,
The third switch includes a first transistor whose collector is connected to the power supply of the third voltage, and a second transistor whose collector is connected to the output terminal and whose emitter is connected to the emitter of the first transistor. A transistor, a floating power supply connected to the emitter of the first transistor or the emitter of the second transistor, and one terminal connected to the floating power supply and the other terminal connected to the output terminal for withstand voltage compensation A plasma display device comprising a capacitor. 3. The plasma display device according to claim 1, wherein a breakdown voltage of the second transistor is smaller than a voltage difference between the first voltage and the second voltage. 2. The plasma display device according to claim 1, wherein a capacitance of the withstand voltage compensation capacitor is not less than 2 times and not more than 5 times a parasitic capacitance between a drain and a source of the first transistor. 3. The plasma display device according to claim 2, wherein a capacitance of the withstand voltage compensating capacitor is not less than 2 times and not more than 5 times a parasitic capacitance between a collector and an emitter of the first transistor.

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