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DE60211190D1 - Verfahren zur herstellung einer halbleiter-schichtstruktur und entsprechende struktur - Google Patents

Verfahren zur herstellung einer halbleiter-schichtstruktur und entsprechende struktur

Info

Publication number
DE60211190D1
DE60211190D1 DE60211190T DE60211190T DE60211190D1 DE 60211190 D1 DE60211190 D1 DE 60211190D1 DE 60211190 T DE60211190 T DE 60211190T DE 60211190 T DE60211190 T DE 60211190T DE 60211190 D1 DE60211190 D1 DE 60211190D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor coating
coating structure
corresponding structure
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60211190T
Other languages
English (en)
Other versions
DE60211190T2 (de
Inventor
Wilfried Attenberger
Joerg Lindner
Bernd Stritzker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universitaet Augsburg 86159 Augsburg De
Original Assignee
Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Publication of DE60211190D1 publication Critical patent/DE60211190D1/de
Application granted granted Critical
Publication of DE60211190T2 publication Critical patent/DE60211190T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10P30/204—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H10P30/208—
    • H10W10/00—
    • H10W10/01—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
DE60211190T 2001-10-12 2002-10-11 Verfahren zur herstellung einer halbleiter-schichtstruktur und entsprechende struktur Expired - Lifetime DE60211190T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US32875901P 2001-10-12 2001-10-12
US328759P 2001-10-12
PCT/EP2002/011423 WO2003034484A2 (en) 2001-10-12 2002-10-11 A method for forming a layered semiconductor structure and corresponding structure

Publications (2)

Publication Number Publication Date
DE60211190D1 true DE60211190D1 (de) 2006-06-08
DE60211190T2 DE60211190T2 (de) 2006-10-26

Family

ID=23282315

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60211190T Expired - Lifetime DE60211190T2 (de) 2001-10-12 2002-10-11 Verfahren zur herstellung einer halbleiter-schichtstruktur und entsprechende struktur

Country Status (8)

Country Link
US (1) US7294564B2 (de)
EP (1) EP1435110B1 (de)
JP (1) JP4225905B2 (de)
KR (1) KR100618103B1 (de)
CN (1) CN1316586C (de)
AU (1) AU2002340555A1 (de)
DE (1) DE60211190T2 (de)
WO (1) WO2003034484A2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2843061B1 (fr) * 2002-08-02 2004-09-24 Soitec Silicon On Insulator Procede de polissage de tranche de materiau
US7390739B2 (en) 2005-05-18 2008-06-24 Lazovsky David E Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
US7749881B2 (en) 2005-05-18 2010-07-06 Intermolecular, Inc. Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
US8084400B2 (en) 2005-10-11 2011-12-27 Intermolecular, Inc. Methods for discretized processing and process sequence integration of regions of a substrate
US8882914B2 (en) 2004-09-17 2014-11-11 Intermolecular, Inc. Processing substrates using site-isolated processing
US7879710B2 (en) 2005-05-18 2011-02-01 Intermolecular, Inc. Substrate processing including a masking layer
US7309658B2 (en) 2004-11-22 2007-12-18 Intermolecular, Inc. Molecular self-assembly in substrate processing
DE102005024073A1 (de) * 2005-05-25 2006-11-30 Siltronic Ag Halbleiter-Schichtstruktur und Verfahren zur Herstellung einer Halbleiter-Schichtstruktur
US7955436B2 (en) 2006-02-24 2011-06-07 Intermolecular, Inc. Systems and methods for sealing in site-isolated reactors
US7544574B2 (en) 2005-10-11 2009-06-09 Intermolecular, Inc. Methods for discretized processing of regions of a substrate
JP2009523319A (ja) * 2006-01-12 2009-06-18 エヌエックスピー ビー ヴィ 前面基板接点を有する絶縁体上半導体デバイスの製造方法
US8772772B2 (en) 2006-05-18 2014-07-08 Intermolecular, Inc. System and method for increasing productivity of combinatorial screening
EP1901345A1 (de) * 2006-08-30 2008-03-19 Siltronic AG Mehrlagiger Halbleiterwafer und entsprechendes Verfahren
US8011317B2 (en) 2006-12-29 2011-09-06 Intermolecular, Inc. Advanced mixing system for integrated tool having site-isolated reactors
JP2009149481A (ja) * 2007-12-21 2009-07-09 Siltronic Ag 半導体基板の製造方法
DE102008006745B3 (de) * 2008-01-30 2009-10-08 Siltronic Ag Verfahren zur Herstellung einer Halbleiterstruktur
EP2172967A1 (de) 2008-08-04 2010-04-07 Siltronic AG Verfahren zur Herstellung von Siliciumcarbid
US7868306B2 (en) * 2008-10-02 2011-01-11 Varian Semiconductor Equipment Associates, Inc. Thermal modulation of implant process
US10049914B2 (en) 2015-11-20 2018-08-14 Infineon Technologies Ag Method for thinning substrates
US10319599B2 (en) 2017-05-31 2019-06-11 Infineon Technologies Ag Methods of planarizing SiC surfaces
EP4135006A1 (de) 2021-08-13 2023-02-15 Siltronic AG Verfahren zur herstellung eines substratwafers zum darauf erstellen von gruppe-iii-v-vorrichtungen und substratwafer zum darauf erstellen von gruppe-iii-v-vorrichtungen

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3622382A (en) * 1969-05-05 1971-11-23 Ibm Semiconductor isolation structure and method of producing
WO1997039476A1 (fr) * 1996-04-18 1997-10-23 Matsushita Electric Industrial Co., Ltd. ELEMENT EN SiC ET SON PROCEDE DE PRODUCTION
JP3958404B2 (ja) * 1997-06-06 2007-08-15 三菱電機株式会社 横型高耐圧素子を有する半導体装置
ES2165315B1 (es) * 2000-03-31 2003-08-01 Consejo Superior Investigacion Procedimiento de fabricacion de capas de carburo de silicio (sic) mediante implantacion ionica de carbono y recocidos.

Also Published As

Publication number Publication date
AU2002340555A1 (en) 2003-04-28
US7294564B2 (en) 2007-11-13
EP1435110B1 (de) 2006-05-03
WO2003034484A3 (en) 2003-09-18
JP2005506699A (ja) 2005-03-03
KR20050035156A (ko) 2005-04-15
CN1316586C (zh) 2007-05-16
JP4225905B2 (ja) 2009-02-18
DE60211190T2 (de) 2006-10-26
US20040248390A1 (en) 2004-12-09
WO2003034484A2 (en) 2003-04-24
KR100618103B1 (ko) 2006-08-29
CN1698193A (zh) 2005-11-16
EP1435110A2 (de) 2004-07-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: UNIVERSITAET AUGSBURG, 86159 AUGSBURG, DE