DE60042254D1 - Verfahren zur Herstellung einer Halbleiter-Anordnung - Google Patents

Verfahren zur Herstellung einer Halbleiter-Anordnung

Info

Publication number: DE60042254D1
Authority: DE; Germany
Prior art keywords: producing; semiconductor device; semiconductor
Prior art date: 1999-08-26
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE60042254T

Other languages

English (en)

Inventor

Shingo Hagiwara

Amane Inoue

Eiichi Nagai

Masaji Inami

Tohru Takeshima

Kouichi Noro

Hideaki Suzuki

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Fujitsu Semiconductor Ltd

Original Assignee

Fujitsu Semiconductor Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1999-08-26

Filing date

2000-03-16

Publication date

2009-07-09

2000-03-16 Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd

2009-07-09 Application granted granted Critical

2009-07-09 Publication of DE60042254D1 publication Critical patent/DE60042254D1/de

2020-03-17 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- H10P74/273—
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10W72/90—
- H10W72/07554—
- H10W72/547—
- H10W72/932—

DE60042254T 1999-08-26 2000-03-16 Verfahren zur Herstellung einer Halbleiter-Anordnung Expired - Lifetime DE60042254D1 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP24022799		1999-08-26
JP2000038777A JP2001135597A (ja)	1999-08-26	2000-02-16	半導体装置の製造方法

Publications (1)

Publication Number	Publication Date
DE60042254D1 true DE60042254D1 (de)	2009-07-09

Family

ID=26534628

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE60042254T Expired - Lifetime DE60042254D1 (de)	1999-08-26	2000-03-16	Verfahren zur Herstellung einer Halbleiter-Anordnung

Country Status (4)

Country	Link
US (1)	US6365443B1 (de)
EP (2)	EP1079430B1 (de)
JP (1)	JP2001135597A (de)
DE (1)	DE60042254D1 (de)

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JP3583662B2 (ja) *	1999-08-12	2004-11-04	株式会社沖マイクロデザイン	半導体装置および半導体装置の製造方法
US7678836B2 (en) *	1999-11-04	2010-03-16	Fxs Ventures, Llc	Method for rendering a contact lens wettable
US6730989B1 (en) *	2000-06-16	2004-05-04	Infineon Technologies Ag	Semiconductor package and method
US6815803B1 (en)	2000-06-16	2004-11-09	Infineon Technologies Ag	Multiple chip semiconductor arrangement having electrical components in separating regions
US6770544B2 (en) *	2001-02-21	2004-08-03	Nec Machinery Corporation	Substrate cutting method
JP3737405B2 (ja) *	2001-09-13	2006-01-18	Ｎｅｃマイクロシステム株式会社	チップ製造方法およびシステム、回路基板、回路チップ
US7183623B2 (en) *	2001-10-02	2007-02-27	Agere Systems Inc.	Trimmed integrated circuits with fuse circuits
US6759311B2 (en) *	2001-10-31	2004-07-06	Formfactor, Inc.	Fan out of interconnect elements attached to semiconductor wafer
JP4189902B2 (ja)	2002-02-06	2008-12-03	富士通株式会社	認証回路、半導体素子及びその使用方法、並びに、ｉｃカード及びその使用方法
US7259043B2 (en) *	2002-05-14	2007-08-21	Texas Instruments Incorporated	Circular test pads on scribe street area
US7026646B2 (en)	2002-06-20	2006-04-11	Micron Technology, Inc.	Isolation circuit
JP4405719B2 (ja) *	2002-10-17	2010-01-27	株式会社ルネサステクノロジ	半導体ウエハ
US20060258135A1 (en) *	2003-09-22	2006-11-16	Matsushita Electtric Industrial Co., Ltd.	Semiconductor integrated circuit
JP4462903B2 (ja) *	2003-11-18	2010-05-12	パナソニック株式会社	半導体ウェハ
JP2005252196A (ja) *	2004-03-08	2005-09-15	Toshiba Corp	半導体装置及びその製造方法
DE102004014644A1 (de) *	2004-03-25	2005-10-13	Atmel Germany Gmbh	Integrierter Schaltkreis
JP4595416B2 (ja) *	2004-07-15	2010-12-08	ソニー株式会社	半導体ウェハ、半導体装置及び半導体装置の製造方法
FR2875624A1 (fr) *	2004-09-23	2006-03-24	St Microelectronics Sa	Generation deterministe d'un numero d'identifiant d'un circuit integre
JP2006140338A (ja) *	2004-11-12	2006-06-01	Matsushita Electric Ind Co Ltd	半導体装置
US20060125508A1 (en) *	2004-12-15	2006-06-15	Impinj, Inc.	On wafer testing of RFID tag circuit with pseudo antenna signal
JP2006253402A (ja) *	2005-03-10	2006-09-21	Nec Electronics Corp	半導体装置の製造方法
DE102005022600A1 (de)	2005-05-10	2006-11-23	Atmel Germany Gmbh	Integrierter Schaltkreis mit Abgleichelementen und Verfahren zu seiner Herstellung
JP2006344795A (ja) *	2005-06-09	2006-12-21	Disco Abrasive Syst Ltd	ウエーハの分割方法
JP4661383B2 (ja) *	2005-06-15	2011-03-30	エプソントヨコム株式会社	圧電発振器の製造方法
US8067819B2 (en) *	2005-11-24	2011-11-29	Ricoh Company, Ltd.	Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line
JP4861022B2 (ja)	2006-02-28	2012-01-25	富士通セミコンダクター株式会社	半導体装置の試験用回路および試験方法、半導体ウエハ、並びに半導体チップの製造方法
JP4907678B2 (ja) *	2009-02-20	2012-04-04	ルネサスエレクトロニクス株式会社	半導体装置の製造方法
ITMI20111418A1 (it) *	2011-07-28	2013-01-29	St Microelectronics Srl	Architettura di testing di circuiti integrati su un wafer
US8552534B2 (en) *	2011-11-01	2013-10-08	Headway Technologies, Inc.	Laminated semiconductor substrate, semiconductor substrate, laminated chip package and method of manufacturing the same
US9508618B2 (en) *	2014-04-11	2016-11-29	Globalfoundries Inc.	Staggered electrical frame structures for frame area reduction
JP6558213B2 (ja)	2014-11-19	2019-08-14	株式会社デンソー	半導体ウェハおよび半導体装置の製造方法
US10312091B1 (en) *	2015-10-13	2019-06-04	Multibeam Corporation	Secure permanent integrated circuit personalization
US10103116B2 (en)	2016-02-01	2018-10-16	Qualcomm Incorporated	Open-passivation ball grid array pads
DE102017207046B4 (de) *	2017-04-26	2019-09-12	Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.	Verfahren zum Herstellen und Auslesen einer kryptografischen Schaltung
US9818656B1 (en) *	2017-05-23	2017-11-14	Nxp Usa, Inc.	Devices and methods for testing integrated circuit devices

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US4446475A (en) *	1981-07-10	1984-05-01	Motorola, Inc.	Means and method for disabling access to a memory
JPS59172243A (ja)	1983-03-18	1984-09-28	Nippon Denso Co Ltd	Ｉｃウエハ
JPS60121599A (ja) *	1983-12-06	1985-06-29	Fujitsu Ltd	集積回路装置
JPS6187349A (ja)	1984-10-04	1986-05-02	Nippon Denso Co Ltd	半導体ウエハ
US4845351A (en) *	1985-09-30	1989-07-04	Casio Computer Co., Ltd.	IC card
JPH0676000B2 (ja)	1985-09-30	1994-09-28	カシオ計算機株式会社	Ｉｃカードの製造方法
JPH0758725B2 (ja) *	1990-01-19	1995-06-21	株式会社東芝	半導体ウェハ
US5059899A (en) *	1990-08-16	1991-10-22	Micron Technology, Inc.	Semiconductor dies and wafers and methods for making
EP0494782B1 (de) *	1991-01-11	1997-04-23	Texas Instruments Incorporated	Prüf- und Einbrennsystem für einen Wafer und Methode für deren Herstellung
JPH0621188A (ja) *	1991-12-13	1994-01-28	Yamaha Corp	半導体ウェハ
JPH0737950A (ja) *	1993-07-20	1995-02-07	Matsushita Electric Ind Co Ltd	回路検査用パッドを有する半導体装置
JPH07169807A (ja) *	1993-12-16	1995-07-04	Nippondenso Co Ltd	半導体ウェハ
JPH07302773A (ja) *	1994-05-06	1995-11-14	Texas Instr Japan Ltd	半導体ウエハ及び半導体装置
US5895942A (en) *	1996-06-18	1999-04-20	Kabushiki Kaisha Toshiba	Fuse selectable modules
JP3529581B2 (ja) *	1997-03-14	2004-05-24	東芝マイクロエレクトロニクス株式会社	半導体ウェーハ及びｉｃカード

2000
- 2000-02-16 JP JP2000038777A patent/JP2001135597A/ja active Pending
- 2000-03-16 DE DE60042254T patent/DE60042254D1/de not_active Expired - Lifetime
- 2000-03-16 EP EP00302139A patent/EP1079430B1/de not_active Expired - Lifetime
- 2000-03-16 EP EP07108693A patent/EP1833086A3/de not_active Withdrawn
- 2000-03-30 US US09/538,231 patent/US6365443B1/en not_active Expired - Lifetime

Also Published As

Publication number	Publication date
US6365443B1 (en)	2002-04-02
JP2001135597A (ja)	2001-05-18
EP1079430A3 (de)	2002-10-16
EP1079430A2 (de)	2001-02-28
EP1079430B1 (de)	2009-05-27
EP1833086A2 (de)	2007-09-12
EP1833086A3 (de)	2008-08-13

Publication	Publication Date	Title
DE60044639D1 (de)	2010-08-19	Verfahren zur herstellung einer halbleitervorrichtung
DE60042254D1 (de)	2009-07-09	Verfahren zur Herstellung einer Halbleiter-Anordnung
DE60113574D1 (de)	2006-02-09	Verfahren zur Herstellung einer Halbleitervorrichtung
DE69918636D1 (de)	2004-08-19	Verfahren zur herstellung einer halbleitervorrichtung
DE60042787D1 (de)	2009-10-01	Verfahren zur Herstellung einer verpackten Halbleiteranordnung
DE69836401D1 (de)	2006-12-28	Verfahren zur Herstellung einer Halbleiteranordnung
DE69942812D1 (de)	2010-11-11	Verfahren zur Herstellung einer Halbleitervorrichtung
DE60143882D1 (de)	2011-03-03	Verfahren zur Herstellung einer MOS-gesteuerten Halbleiteranordnung
DE60307157D1 (de)	2006-09-14	Verfahren zur Herstellung einer Halbleitervorrichtung
DE60038423D1 (de)	2008-05-08	Verfahren zur Herstellung eines Halbleiterbauelements
DE69926960D1 (de)	2005-10-06	Verfahren zur Herstellung einer photovoltaischen Vorrichtung
DE10080916T1 (de)	2001-06-13	Verfahren zur Herstellung einer photovoltaischen Vorrichtung
DE69730940D1 (de)	2004-11-04	Verfahren zur herstellung einer halbleiteranordnung
DE69636338D1 (de)	2006-08-24	Verfahren zur herstellung einer halbleitervorrichtung
DE60030949D1 (de)	2006-11-09	Verfahren zur herstellung einer karte
DE60028912D1 (de)	2006-08-03	Verfahren zur Herstellung von Hableitervorrichtungen
DE69939514D1 (de)	2008-10-23	Verfahren zur herstellung einer strukturierten dünnschichtvorrichtung
DE69912376D1 (de)	2003-12-04	Verfahren zur herstellung eines halbleiterbauelements
DE60033847D1 (de)	2007-04-19	Vorrichtung und verfahren zur herstellung einer kohlenstoffhaltigen schicht
DE60125755D1 (de)	2007-02-15	Verfahren zur herstellung einer flexodruckplatte
DE69906491D1 (de)	2003-05-08	VERFAHREN ZUR HERSTELLUNG EINER SiCOI-STRUKTUR
DE60218802D1 (de)	2007-04-26	Verfahren zur Herstellung einer Vorrichtung
DE60022857D1 (de)	2005-11-03	Verfahren zur Herstellung eines Halbleiterbauelements
DE69940737D1 (de)	2009-05-28	Verfahren zur herstellung einer halbleiteranordnung
DE50113179D1 (de)	2007-12-13	Verfahren zur Herstellung eines Halbleiterbauelements

Legal Events

Date	Code	Title	Description
2010-06-17	8364	No opposition during term of opposition
2010-11-25	8327	Change in the person/name/address of the patent owner	Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP
2011-02-10	8328	Change in the person/name/address of the agent	Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE