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CN1148804C - 高集成度芯片上芯片封装 - Google Patents

高集成度芯片上芯片封装 Download PDF

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CN1148804C
CN1148804C CNB991070917A CN99107091A CN1148804C CN 1148804 C CN1148804 C CN 1148804C CN B991070917 A CNB991070917 A CN B991070917A CN 99107091 A CN99107091 A CN 99107091A CN 1148804 C CN1148804 C CN 1148804C
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克罗德·露易斯·伯汀
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托马斯·乔治·弗伦斯
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韦恩·约翰·霍威尔
埃德蒙·朱里斯·斯泊吉斯
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Abstract

一种高集成度芯片上芯片封装，它包含：至少两个叠置的芯片上芯片组件，其中每一个芯片上芯片组件至少具有二个有源区电连接在一起的独立芯片，其中所述二个芯片的所述有源区彼此面对；以及用来将所述芯片电连接到外部电路的互连衬底，该互连衬底包含：连接于芯片的有源区的第一组连接元件；用来连接到所述外部电路的第二组连接元件；以及具有导电线条的衬底，所述导电线条将所述第一组连接元件连接到所述第二组连接元件。其中所述第二组连接元件包含：与所述至少两个芯片上芯片组件中一个的外侧面齐平的第一组连接件；以及与所述至少两个芯片上芯片组件中另一个的外侧面齐平的第二组连接件。

Description

高集成度芯片上芯片封装
本申请涉及到二个共同未决的申请：Bertin等人的题为“半导体封装件中的微弯曲工艺”的美国申请No.09/105382和Ference等人的题为“改变特性的芯片上芯片互连”的美国申请No.09/105477。相关的申请被转让于记载的受让人，因而同时提出申请，此处并列为参考。
技术领域
本发明一般涉及到半导体器件，更具体地说是涉及到半导体器件中的芯片上芯片封装。
背景技术
在电子开发和封装中，最近50年已发生了巨大的进步。集成电路密度已经并继续高速提高。但80年代之前，制作在芯片中的电路外部的互连电路密度的相应提高跟不上集成电路密度的提高。出现了许多新的封装工艺。一个特定的工艺称为“芯片上芯片组件”工艺。本发明涉及到芯片上芯片组件的具体技术领域。
许多情况下，比之设计新的衬底集成电路，可以更快速而便宜地制造芯片上芯片组件。芯片上芯片组件工艺由于密度的提高而显现出优点。由于密度的提高，在信号传播速度和与其它装置不协调的器件总重量方面得到了同样的改进。目前的芯片上芯片组件结构通常由直接粘合到一系列集成电路元件的印刷电路板衬底组成。
还有许多不同的技术领域，与如何将粘合有芯片上芯片组件的衬底从外部电连接到衬底上的电路有关。这些技术领域包括引线键合、载带自动键合(TAB)、倒装TAB和倒装芯片。在下列美国专利中可找到一些例子：1994年6月授予Fogal等人的美国专利No.5323060“具有叠层芯片分布的多芯片组件”、1997年2月授予B0ne等人的美国专利No.5600541“具有由介质载带制作的分立芯片载体的垂直IC芯片叠层”、1996年2月授予Korneld等人的美国专利No.5495394“多芯片组件中的三维管芯封装”、以及1995年3月授予Rostoker等人的美国专利No.5399898“采用倒装芯片管芯的多芯片半导体分布”。
不幸的是，这些技术很昂贵，而且在大多数情况下无法返工(亦即清除和代换)封装件的组元，从而降低了成品率并增加了成本。芯片尺寸的个性化设计也受到严重限制。目前，芯片能够在晶片级或封装级进行个性化设计。由于在封装之前，在晶片后制造工艺中不能够个性化设计芯片，而无法得到产品应用的明显灵活性和制造成本的优点。
发明内容
因此，本发明的优点是提供消除上述和其它限制的芯片上芯片元件、互连、及其制造方法。
本发明提供一种高集成度芯片上芯片封装，它包含：至少两个叠置的芯片上芯片组件，其中每一个芯片上芯片组件至少具有二个有源区电连接在一起的独立芯片，其中所述二个芯片的所述有源区彼此面对；以及用来将所述芯片电连接到外部电路的互连衬底，该互连衬底包含：连接于芯片的有源区的第一组连接元件；用来连接到所述外部电路的第二组连接元件；以及具有导电线条的衬底，所述导电线条将所述第一组连接元件连接到所述第二组连接元件，其中所述第二组连接元件包含：与所述至少两个芯片上芯片组件中一个的外侧面齐平的第一组连接件；以及与所述至少两个芯片上芯片组件中另一个的外侧面齐平的第二组连接件。
在上述芯片上芯片封装的一个实施例中，该至少二个芯片的工艺不同。
在上述芯片上芯片封装的一个实施例中，所述外部电路是可插接的连接。
在上述芯片上芯片封装的一个实施例中，所述互连衬底与所述芯片上芯片组件的所述至少二个芯片中的一个的高度相同。
在上述芯片上芯片封装的一个实施例中，多个芯片上芯片组件相互堆叠放置。
在上述芯片上芯片封装的一个实施例中，第一组连接件包括焊料球。
在上述芯片上芯片封装的一个实施例中，第二组连接件包括金属焊点。
借助于具有至少二个功能完全独立的芯片且电连接在一起的芯片上芯片组件以及用来将芯片电连接到外部电路的芯片上芯片元件连接/互连，实现了本发明的优点。
从如附图所示的本发明最佳实施例的更确切的描述中，本发明的上述和其它的优点和特定将更为明显。
附图说明
以下结合附图来描述本发明的最佳示范实施例，在这些附图中，相似的参考号表示相似的元件。
图1是根据本发明最佳实施例的具有第一示范芯片上芯片元件连接的芯片上芯片元件的剖面图；
图2、3和4是根据本发明最佳实施例的具有第二、第三和第四示范芯片上芯片元件连接的芯片上芯片元件的剖面图；
图5是采用图4的示范芯片上芯片元件连接的芯片上芯片封装件的剖面图；
图6是具有第五示范芯片上芯片元件连接的图1的芯片上芯片元件的剖面图；
图7是采用图6的示范芯片上芯片元件连接的芯片上芯片封装件的剖面图；
图8、9、10、11、12和13剖面图示出了根据本发明第二实施例的芯片上芯片元件的制造顺序；
图14是根据本发明第三实施例的芯片上芯片元件的剖面图；
图15是采用图14的芯片上芯片元件的芯片上芯片封装件的剖面图；
图16是根据本发明第四实施例的芯片上芯片元件的剖面图；
图17是根据本发明第五实施例的芯片上芯片元件的剖面图；
图18是采用图17的芯片上芯片元件的芯片上芯片封装件的剖面图。
具体实施方式
参照图1，示出了根据本发明最佳实施例的第一示范芯片上芯片元件10。芯片上芯片元件10包含第一芯片30、第二芯片40和芯片上芯片元件连接20。第一芯片30的有源区35通过诸如C4(控制熔塌芯片连接)焊料球连接50之类的芯片间连接或光子互连，被电连接到第二芯片40的有源区45。焊料球连接50提供了芯片间联系的高性能电通路。这一互连与芯片电学布线的固有高性能一起，大大地降低了第一芯片30和第二芯片40二者的芯片外驱动器(未示出)的尺寸和功率。虽然此例和以后的例子具体示出了焊料球和焊料柱，但应该理解，也可以采用诸如聚合物金属复合物互连、电镀铜柱、微锁连接等等之类的不同组分构成的其它互连。
在此特定例子中，芯片上芯片元件连接20是连接于第一芯片30的焊料柱22。焊料柱22使得能够将芯片上芯片元件10一般通过衬底连接到外部电路。
图2示出了第二示范芯片上芯片元件，其中芯片上芯片元件连接20包含焊料球。在图1和2中，在IBM Dkt，No.BU9-98-011的相关应用中，可找到制造焊料柱和焊料球的示范性方法。也可以通过下列步骤来制造焊料柱和焊料球：
1)制造具有可焊金属焊点的第一芯片。可以用作焊料柱焊点的外围区焊点的直径可以是例如125微米，间距为250微米。中心区焊点的直径可以是50微米，间距为100微米。
2)制造具有C4焊料球阵列的第二芯片。C4的组分可以是Pb∶Sn＝97∶3，且C4应该与第一芯片中心区焊点的间距一致。
3)将第一芯片固定到第二芯片。通过标准的芯片拾放技术(CPP)，或通过诸如不用清除的助熔剂、PADS、松香助熔剂与炉回流结合的工艺，可以做到这一点。
4)将焊料柱或焊料球固定到第二芯片。通过焊料注入铸模，可以做到这一点。
5)将芯片上芯片元件连接到衬底。借助于通过标准的放置与连结工艺将易熔焊料连结在衬底TSM焊点上，可以做到这一点。
图3和4示出了芯片上芯片元件的第三和第四例子，其中的芯片上芯片元件连结20包含焊料球26和布线25(图3)或丝焊28(图4)。在图3中，在衬底57中制作空腔55，使第二芯片40的顶部与衬底57的顶部的高度相同。焊料球26则可以与连接的焊料球50尺寸相同，从而将芯片上芯片元件连接到衬底57。
图5示出了采用图4的芯片上芯片元件10A的芯片上芯片封装件。丝焊28连接于衬底72的顶侧。衬底72的底侧包含用来将芯片上芯片封装件连接于不同封装级的焊料球76。粘合剂71将芯片上芯片元件10A机械连接于衬底72。树脂挡条66和包封剂64保护着芯片30和40，并为丝焊和芯片结构60提供强度。金属盖62提供了紧凑、耐用而热增强的芯片上芯片封装件。
如图6和7可见，芯片上芯片元件10B的芯片上芯片元件连结20包含焊料球插件32。焊料球插件32提供了到衬底的电互连以及第二芯片40的尺寸所需的高度。焊料球插件32由连接于一个芯片40的有源区的第一组焊料球、连接于外部电路的第二组焊料球、以及第一组和第二组焊料球之间的导电通道组成。此通道被不导电的材料包围。图7示出了采用图6的芯片上芯片元件10B的芯片上芯片封装件。焊料球插件被连接于衬底72的顶侧。衬底72的底侧包含用来将芯片上芯片封装件连接于不同级封装件的焊料球76。散热器74通过粘合剂78被连接到第一芯片30。散热器使芯片上芯片元件10B得以散热。
图1-7和后面例子的芯片上芯片元件的一些优点包括：可以用不同的半导体工艺来制造芯片30和40，并将它们连接起来而不受这些工艺用于单一芯片时所固有的限制。例如，芯片30可以是逻辑芯片，而芯片40可以是DRAM芯片，在芯片上芯片元件级上产生逻辑/DRAM组合。第二，比之在每个芯片上提供所有功能和电路的单个芯片来说，芯片30和40单独地说是较小而较不复杂的。第三，大量存储器可以位于处理器的紧邻。第四，由于芯片上芯片元件的极为平坦的金属特性，而具有较大的互连密度。最后，本发明的芯片上芯片元件提供了比提供同样功能的简单高集成芯片更低的成本、更低的功率和更高的性能。
图8-13剖面图示出了根据本发明第二实施例的芯片上芯片元件的制造顺序。在图8中，示出了具有有源电路和互连层145的芯片晶片140。晶片140可以是例如硅晶片、GaAs晶片、SiGe晶片等。有源电路和互连层145包含外部互连所需的结构和图形。在图9中，二类元件被固定到晶片140：集成电路(IC)芯片130和焊料球插件(也称为隔件)32。IC芯片130被电连接于晶片140中的有源电路，并提供较高水平的集成电路功能。可以使用诸如带包封的焊料球和丝焊之类的电连接。焊料球插件32提供了晶片140上有源电路层145和IC芯片130有源电路层侧形成的平面之间的电通路。虽然在本例子中具体示出了焊料球插件32，但也可以使用诸如具有通道孔的硅晶片、多层陶瓷和有机PCB间隔之类的其它间隔。同时，虽然在本例子中用焊料球来将IC芯片130和焊料球插件32连接到晶片140，但也可以采用诸如导电环氧树脂、PMC胶、各向异性导电粘合剂和瞬变液相键合之类的其它互连方法。可以用焊料球包封体(未示出)来包围焊料球。
如图10所见，在整个表面上淀积共形涂层34(例如对二甲苯)。然后如图11所示，用机械和/或化学方法整平此涂层。整平的一个例子可以是用标准的晶片抛光方法对表面进行机械抛光。这一整平使结构中焊料球插件32中的互连通道孔出现在表面上。这些通道孔构成到外部电路的连接。图12示出了在焊料球插件32上制造用于对外部电路互连的焊料球36。在预定点38处切割芯片上芯片元件，形成能够用焊料球36连接到外部电路的“超芯片”。图13示出了连接于载体/衬底72的超芯片。制造图13所示的超芯片有一些优点。这些优点包括：用多层不同半导体工艺的非常高的集成度；元件速度、带宽要求和芯片外速度方面的优越性能；组元芯片物理上很小且不需要复杂的电路或制造工艺，导致成品率高和成本低；以及借助于以各种形式连接几个组元元件，能够达到专用化。
图14和15是根据本发明第三实施例的芯片上芯片元件80的剖面图。芯片上芯片元件80包含由二个芯片构成一组的二个组，每个组有电连接于第二芯片的第一芯片30和40以及30A和40A(例如图1中的芯片上芯片元件10)。在此例子中，芯片30和30A的背侧彼此相对。二组芯片通过芯片上芯片元件连接20A(此例子中是互连衬底88)电连接到一起。互连衬底88还通过诸如丝焊84、C4连接86和金属焊点连接82之类的电连接，将芯片上芯片元件80连接到外部器件。虽然为了说明的目的，在图14和15的芯片上芯片元件80上示出了不同类型的连接，但通常对于一种应用只使用一种类型的连接(亦即，连接82、84和86可以都是例如C4连接)。图15示出了采用图14的芯片上芯片元件80的芯片上芯片封装件。二个散热器92通过粘合剂94被连接于芯片30和30A。散热器使芯片上芯片元件80得以散热。在衬底57中制作空腔55，使第二芯片40的顶部与衬底57的顶部的高度相同。焊料球26则可以与连接的焊料球50尺寸相同，从而将芯片上芯片元件连接到衬底57。这样，如根据本发明这一实施例所述，可以将几个各具有分立和特定功能且可能用不同的半导体工艺制造的芯片结合在一起。
图16是根据本发明第四实施例的包含芯片上芯片元件80A的可插接的芯片上芯片封装件的剖面图。芯片上芯片元件80A包含芯片30、30A、40、40A、互连衬底88A、和耦合衬底88B。在此例子中，芯片上芯片元件80A被包封剂96包封，从而提供一个坚实的元件。互连衬底88A使得能够通过可插接界面电连接到外部电路。
图17是根据本发明第五实施例的芯片上芯片元件80B的剖面图。除了芯片上芯片元件连接20A包含延伸于芯片上芯片元件80B上下表面的可堆叠的互连衬底88C之外，芯片上芯片元件80B与芯片上芯片元件80(图14)是相似的。芯片上芯片元件连接20A的上表面包含可熔性金属焊点82，而芯片上芯片元件连接20A的下表面包含焊料球86。芯片上芯片元件结构80B是三维可堆叠组件的示范单元结构。另一种示范单元结构可以包含取消芯片40和40A，并使芯片上芯片元件连接20A延伸跨过芯片30和30A。图18示出了含有二个图17的芯片上芯片元件单元结构80B的堆叠的组件。
堆叠的组件和单元结构的一些优点是：首先，可以容易地适应不同尺寸和厚度的芯片。第二，结构是可返工的。第三，各种尺寸的结构都是可能的而没有明显的先决条件。第四，有可能安排单元结构之间的热问题。
于是，根据本发明的芯片上芯片元件和连接，使得能够得到高集成度工艺和可靠而紧凑的半导体封装件。芯片上芯片封装件还提供了增强的电学性能、机械性能与热性能。
虽然参照最佳实施例已经具体地描述了本发明，但本技术领域熟练人员能够理解，可以作出上述的和其它的形式和细节的改变而不超越本发明的构思与范围。

Claims (7)

1.一种高集成度芯片上芯片封装，它包含：
至少两个叠置的芯片上芯片组件，其中每一个芯片上芯片组件至少具有二个有源区电连接在一起的独立芯片，其中所述二个芯片的所述有源区彼此面对；以及
用来将所述芯片电连接到外部电路的互连衬底，该互连衬底包含：连接于芯片的有源区的第一组连接元件；用来连接到所述外部电路的第二组连接元件；以及具有导电线条的衬底，所述导电线条将所述第一组连接元件连接到所述第二组连接元件，
其中所述第二组连接元件包含：与所述至少两个芯片上芯片组件中一个的外侧面齐平的第一组连接件；以及与所述至少两个芯片上芯片组件中另一个的外侧面齐平的第二组连接件。
2.权利要求1的芯片上芯片封装，其中该至少二个芯片的工艺不同。
3.权利要求1的芯片上芯片封装，其中所述外部电路是可插接的连接。
4.权利要求1的芯片上芯片封装，其中所述互连衬底与所述芯片上芯片组件的所述至少二个芯片中的一个的高度相同。
5.权利要求1的芯片上芯片封装，其中多个芯片上芯片组件相互堆叠放置。
6.权利要求1的芯片上芯片封装，其中第一组连接件包括焊料球。
7.权利要求1的芯片上芯片封装，其中第二组连接件包括金属焊点。
CNB991070917A 1998-06-26 1999-05-27 高集成度芯片上芯片封装 Expired - Fee Related CN1148804C (zh)

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US6294406B1 (en) 2001-09-25

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