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CN1065662C - 半导体芯片封装及其制造方法 - Google Patents

半导体芯片封装及其制造方法 Download PDF

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CN1065662C
CN1065662C CN96109458A CN96109458A CN1065662C CN 1065662 C CN1065662 C CN 1065662C CN 96109458 A CN96109458 A CN 96109458A CN 96109458 A CN96109458 A CN 96109458A CN 1065662 C CN1065662 C CN 1065662C
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CN1153997A (zh
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宋致仲
李柱华
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SK Hynix Inc
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LG Semicon Co Ltd
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Abstract

本发明公开的改进封装增加了存储容量，改善了热辐射效果，并且是比较薄的。该封装包括若干条引线，其中每条引线包括具有上和下表面的第一衬底引线和第二衬底引线。集成芯片，例如半导体芯片附着在第一衬底引线上表面的区域。芯片和引线被模制以致第一衬底引线的下表面和第二衬底引线的上表面被露出。

Description

半导体芯片封装及其制造方法
本发明涉及半导体芯片封装以及制备这种半导体封装的方法，特别涉及这样一种半导体芯片封装，其引一的上或下表面的预定区域向外暴露。
图1示出了美国专利第5，428，248号公开的暴露引线的半导体封装，该申请已转让给LG半导体株式会社。半导体芯片11通过粘附元件13安装在衬底引线12a的上表面。从衬底引线12a扩展的芯片引线12b具有近似于半导体芯片11上表面的高度的预定高度。在半导体芯片11上形成的若干键合焊盘和芯片引线12b通过引线14相连接。包括半导体芯片11和若干引线12a和12b的预定区域用树脂模制，衬底引线12a的下表面从封装的下表面区域露出以电连接电路衬底(未示出)的金属图形。
传统的露线式半导体封装的缺点是，由于衬底引线朝封装的下表面暴露，因而该封装不能层叠很多半导体芯片，从而限制了存储容量的增加。此外，由于传统的露线式半导体封装具有只朝暴露的衬底引线辐射热的结构，因此不能实现所期望的热辐射效果。另外，由于引线焊接要在半导体芯片下部区域完成以及包括半导体上部的预定区域要由树脂模制，因此封装的厚度需要增加。
所以，本发明的目的是提出能解决上述问题的露线式半导体封装。
本发明的优点是提供了较薄的露线式半导体封装。
本发明另一个优点是增加了半导体封装的存储芯片容量。
本发明再一个优点是改善了封装中的由半导体封装产生的热辐射。
上述目的和优点部分地由集成芯片封装来实现，一种半导体芯片封装，包括：
一个半导体芯片，其中具有多个键合焊盘，一个引线框架，具有多个各自具有下表面和上表面的引线，每个引线具有第一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；粘附元件，用于将半导体芯片固定到引线框架上；多个导电元件，用于将芯片上的所述多个键合焊盘与多个引线相连；模制体，用于封装所述半导体芯片、引线框架、粘附元件和导电元件；其特征在于：所述第二衬底引线的上表面的所述平行部分和所述第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
为实现上述目的和优点，本发明提供的制造上述半导体封装的方法，包括：模键合步骤，用于将一半导体芯片用粘附元件固定到一引线框架的第一衬底引线的上表面上，所述引线框架具有多个各自具有下表面和上表面的引线，每个引线具有第一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；电性连接步骤，利用导电元件使所述半导体芯片上的键合焊盘与引线框架的引线的一个表面相连；模制步骤，用于封装半导体芯片、粘附元件、导电元件和引线，其中使引线框架的第二衬底引线的上表面的所述平行部分和引线框架的第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
本发明的附加优点、目的和其他特点将在下文中说明，对本领域的普通技术人员来说，根据对下文的分析将会清楚这些特点(附加优点，目的和其它特点)或者能够从本发明的实践中了解这些特点(附加优点、目的和其它特点)。本发明的目的和优点能够象权利要求书特别指出的那样实现和达到。
下面参照附图详细说明本发明，在图中相同的参考标号指相同的元件。
图1是美国专利第5，428，248号公开的露线式半导体封装的剖面图；
图2是本发明实施例的露线式半导体封装的剖面图；
图3是图2所示的露线式半导体封装的底(仰)视图；
图4是本发明另一实施例的暴露引线式半导体封装的剖面图；
图5是根据本发明层叠图2所示半导体封装的增加集成芯片容量的结构的剖面图；
图6是根据本发明层叠图4所示半导体封装的增加集成芯片容量的结构的剖面图．
图2是根据具有示出底部视图的图3的本发明实施例所示的露线式半导体封装的剖面图。半导体芯片21在其下表面形成有若干键合焊盘。引线框架22设置在半导体芯片21的下部，它包括若干条引线。每条引线包括第一衬底引线22a和第二衬底引线22b。第二衬底引线的预定长度在从第一衬底引线22a的一端上向弯曲之后平行于第一衬底引线22a伸展。
若干个粘附元件23用于固定或安装半导体芯片21到第一衬底引线22a另一端部分的上表面。粘附元件23可以是双面绝缘带或者基于聚酰胺或环氧树脂的绝缘胶。若干导线24把半导体芯片下表面上的若干键合焊盘电连接到第二衬底引线22b的下表面。
树脂制作的模制体26采用模制工艺形成以封装半导体芯片21、若干导线24、粘附元件23、第一衬底引线22a的上表面和第二衬底引线22b的下表面。尽管这样，第一衬底引线22a的下表面和第二衬底引线22b的上表面仍被暴露并且实质上与模制体26的外表面共面。所以，从第一衬底引线22a的下表面到第二衬底引线22b的上表面的高度等于半导体封装的厚度。第一衬底引线22a的被暴露下表面的面积可以相似于第二衬底引线22b的被暴露上表面的面积。此后，第一衬底引线22a的被暴露的下表面或第二衬底引线22b的被暴露上表面连接到印刷电路板的金属图形(未示出)。
图4示出了根据本发明另一个实施例的露线式半导体封装的剖面图。图4的实施例类似于图2的实施例。在该实施例中，不是用若干导线24而是用若干焊料块25把键合焊盘连接到第一衬底引线22a的上表面。
本发明的第一和第二实例的露线式半导体封装的加工方法是类似的。在图2所示的实施例中，该方法包括：用于把半导体芯片21从晶片中分离的锯开步骤；用于利用粘附元件23把半导体芯片21安装在第一衬底引线22a上表面的模键合步骤；用于使用像金或铝那样的导线24连接半导体芯片21的若干键合焊盘和衬底引线22a的导线焊接步骤；和模制步骤，它用于采用模制树脂封装焊接引线的半导体芯片21和衬底引线22a以便引线22可以部分地暴露于封装体的上和下表面。在图4所示的实施例中，导线连接工序用焊接工序可替换。在两个实施例中，成型和修整工序不再需要，从而节省了制造封装的费用。
如图2和图4所示，封装的高度被减小。此外，由于引线被暴露在半导体封装的上、下表面上，因此引线又成为了散热片，从而改善了热辐射，增强了抵抗热损坏的芯片可靠性。从上所述不难看到，本发明可以容易地实现封装的小型化，能够非常容易地完成芯片的安装。并且还能够容易地完成电特性试验，这样就增强了电气可靠性。
在上述实施例中，所述的表面指便于说明附图视图中的本发明的上表面和下表面。也可以理解为依据封装定向的参考表面。此外，上述实施例只不过是示范，不能作为限定本发明来作解释。例如，图2和图4实施例示出了密封的半导体芯片，但本领域的普通技术人员可以容易地封装具有暴露芯片上表面的芯片。本领域的技术人员将会明白本发明的许多变形和变化的任一种。

Claims (18)

1．一种半导体芯片封装，包括：
一个半导体芯片，其中具有多个键合焊盘，
一个引线框架，具有多个各自具有下表面和上表面的引线，每个引线具有一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；
粘附元件，用于将半导体芯片固定到引线框架上；
多个导电元件，用于将芯片上的所述多个键合焊盘与多个引线相连；
模制体，用于封装所述半导体芯片、引线框架、粘附元件和导电元件；
其特征在于：
所述第二衬底引线的上表面的所述平行部分和所述第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
2．根据权利要求1的半导体芯片封装，其中所述粘附元件至少是双面绝缘胶带和绝缘膏中的一种。
3．根据权利要求1的半导体芯片封装，其特征在于所述导电元件包括多根引线。
4．根据权利要求1的半导体芯片封装，其特征在于所述导电元件包括多个焊料块。
5．根据权利要求3的半导体封装，其特征在于所述多根引线用于将芯片上的键合焊盘到连接到相应的第二衬底引线的下表面。
6．根据权利要求4的半导体封装，其特征在于所述多个焊料块将芯片上的键合焊盘连接到相应的第一衬底引线的上表面。
7．根据权利要求1的半导体封装，其特征在于所述第一和第二衬底引线的向外暴露部分与所述模制体的外表面共面。
8．根据权利要求1的半导体封装，其特征在于所述半导体芯片被部分地由模制体封装，至少芯片的一个表面向外暴露。
 9．根据权利要求1的半导体封装，其特征在于所述第二衬底引线与第一衬底引线的一端弯折后的那部分平行。
10．用于制造半导体芯片封装的方法，包括以下步骤：
模键合步骤，用于将一半导体芯片用粘附元件固定到一引线框架的第一衬底引线的上表面上，所述引线框架具有多个各自具有下表面和上表面的引线，每个引线具有第一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；
电性连接步骤，利用导电元件使所述半导体芯片上的键合焊盘与引线框架的引线的一个表面相连；
模制步骤，用于封装半导体芯片、粘附元件、导电元件和引线，其中使引线框架的第二衬底引线的上表面的所述平行部分和引线框架的第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
11．根据权利要求10的方法，其中所述粘附元件至少是双面绝缘胶带和绝缘膏中的一种。
12．根据权利要求10的方法，其中所述导电元件包括多根引线。
13．根据权利要求10的方法，其中所述导电元件包括多个焊料块。
14．根据权利要求12的方法，其中所述多根引线用于将芯片上的键合焊盘到连接到相应的第二衬底引线的下表面。
15．根据权利要求13的方法，其中所述多个焊料块将芯片上的键合焊盘连接到相应的第一衬底引线的上表面。
16．根据权利要求10的方法，其中所述第一和第二衬底引线的向外暴露部分与所述模制体的外表面共面。
17．根据权利要求10的方法，其中所述半导体芯片被部分地由模制体封装，至少芯片的一个表面向外暴露。
18．根据权利要求10的方法，其中所述第二衬底引线与第一衬底引线的一端弯折后的那部分平行。
CN96109458A 1995-12-29 1996-08-23 半导体芯片封装及其制造方法 Expired - Fee Related CN1065662C (zh)

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