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KR20010037247A - 반도체패키지 - Google Patents

반도체패키지 Download PDF

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Publication number
KR20010037247A
KR20010037247A KR1019990044651A KR19990044651A KR20010037247A KR 20010037247 A KR20010037247 A KR 20010037247A KR 1019990044651 A KR1019990044651 A KR 1019990044651A KR 19990044651 A KR19990044651 A KR 19990044651A KR 20010037247 A KR20010037247 A KR 20010037247A
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South Korea
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mounting plate
chip mounting
chip
semiconductor
semiconductor package
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서무환
이태헌
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마이클 디. 오브라이언
앰코테크놀로지코리아 주식회사
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Priority to KR1019990044651A priority Critical patent/KR20010037247A/ko
Priority to JP2000015004A priority patent/JP2001077278A/ja
Priority to US09/687,585 priority patent/US6696747B1/en
Publication of KR20010037247A publication Critical patent/KR20010037247A/ko
Priority to US10/763,859 priority patent/US7115445B2/en
Priority to US11/492,481 priority patent/US7321162B1/en
Priority to US11/947,505 priority patent/US20080283979A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

이 발명은 반도체패키지에 관한 것으로, MLF(Micro LeadFrame)형 반도체패키지에서 그 두께를 더욱 얇게 하기 위해, 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착된 칩탑재판과; 상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 내부리드와; 상기 반도체칩의 입출력패드와 내부리드를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 봉지재로 봉지하되, 상기 칩탑재판 및 내부리드의 저면과 측면은 외부로 노출되도록 봉지하여 형성된 패키지몸체로 이루어진 반도체패키지에 있어서, 상기 칩탑재판은 상면 전체에 할프에칭면이 형성되어 내부리드의 두께보다 얇게 형성된 것을 특징으로 하는 반도체패키지.

Description

반도체패키지{semiconductor package}
본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 MLF(Micro LeadFrame)형 반도체패키지에서 그 두께를 더욱 얇게 할 수 있는 반도체패키지에 관한 것이다.
최근의 전자기기 예를 들면, 휴대폰, 셀룰러 폰, 노트북 등의 마더보드에는 많은 수의 반도체칩들이 패키징되어 최소 시간내에 그것들이 다기능을 수행할 수 있도록 설계되는 동시에, 전자기기 자체가 초소형화 되어 가는 추세에 있다. 이에 따라 반도체칩이 고집적화됨은 물론, 이를 패키징한 반도체패키지의 크기도 축소되고 있으며, 또한 실장밀도도 고밀도화되어 가고 있다.
이러한 추세에 따라 최근에는 반도체칩의 전기적 신호를 마더보드로 전달해줌은 물론 마더보드(mother board) 상에서 일정한 형태로 지지되도록 하는 반도체패키지의 크기가 대략 1×1mm ~ 10×10mm 내외로 개발되고 있으며, 이러한 반도체패키지의 예로서 MLF(Micro LeadFrame)형 패키지 등이 알려져 있다.
여기서 상기 MLF형 패키지(100')를 도1a 및 도1b에 도시하였다.
도시된 바와 같이 상면에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면에는 접착제로 칩탑재판(4)이 접착되어 있다. 상기 칩탑재판(4)은 측면 둘레에 할프에칭부(4a)가 형성되어 있고 모서리에는 외측으로 연장되고 역시 할프에칭부(도시되지 않음)가 구비된 타이바(28)가 형성되어 있다. 상기 칩탑재판(4)의 외주연에는 방사상으로 배열되어 있으며 칩탑재판(4)을 향하는 단부에 할프에칭부(6a)가 형성된 다수의 내부리드(6)가 구비되어 있다. 상기 반도체칩(2)의 입출력패드(2a)와 내부리드(6)는 도전성와이어(8)에 의해 서로 전기적으로 접속되어 있다. 계속해서 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4) 및 내부리드(6)는 봉지재로 봉지되어 소정의 패키지몸체(10)를 형성하고 있으며, 상기 칩탑재판(4), 내부리드(6) 및 타이바(28)의 저면은 패키지몸체(10) 저면으로 노출되어 있다.
그러나 상기와 같은 종래의 반도체패키지는 내부리드의 두께와 칩탑재판의 두께가 동일함으로써 반도체패키지의 전체적인 두께를 얇게 하는데 한계가 있다. 또한, 상기 칩탑재판과 내부리드의 두께가 동일함으로써 상기 칩탑재판에 탑재된 반도체칩의 입출력패드 위치가 내부리드의 위치에 비해 훨씬 높은 곳에 위치하기 때문에 그 반도체칩과 내부리드 사이를 연결하는 도전성와이어의 루프 하이트(loop hight)도 커지는 문제점이 있다. 상기와 같이 루프 하이트가 크게되면 반도체패키지의 제조 공정(특히 봉지 공정)중 와이어 스위핑(wire sweeping) 문제가 발생할 수 있다.
한편, 상기와 같은 종래의 반도체패키지에서 그 두께를 감소시키기 위한 기술로 반도체칩을 백그라인딩(back grinding)한 후 상기 칩탑재판에 탑재하는 기술이 알려져 있다. 그러나, 이는 반도체칩에 많은 악영향을 끼친다. 즉, 얇아진 반도체칩은 워페이지(warpage)되기 쉬어 내부의 집적회로가 손상되거나 또는 크랙되는 경우가 있고, 또한 상기 백그라인딩 공정중 반도체칩 자체가 크랙되어 파손될 수도 있다.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 반도체칩을 백그라인딩하지 않으면서도 반도체패키지의 두께를 초박형화 할 수 있는 반도체패키지를 제공하는데 있다.
도1a 및 도1b는 종래의 반도체패키지를 도시한 단면도 및 저면도이다.
도2는 본 발명에 의한 반도체패키지를 도시한 단면도이다.
- 도면중 주요 부호에 대한 설명 -
100; 반도체패키지 2; 반도체칩
2a; 입출력패드 4; 칩탑재판
4c; 칩탑재판의 할프에칭면 6; 내부리드
6a; 내부리드의 할프에칭부 8; 도전성와이어
10; 패키지몸체 28; 타이바
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착된 칩탑재판과; 상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 내부리드와; 상기 반도체칩의 입출력패드와 내부리드를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 봉지재로 봉지하되, 상기 칩탑재판 및 내부리드의 저면과 측면은 외부로 노출되도록 봉지하여 형성된 패키지몸체로 이루어진 반도체패키지에 있어서, 상기 칩탑재판은 상면 전체에 할프에칭면이 형성되어 내부리드의 두께보다 얇게 형성된 것을 특징으로 한다.
여기서, 상기 칩탑재판은 그 두께가 내부리드 두께의 대략 25~75%로 함이 바람직하다.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 칩탑재판의 상면 전체에 할프에칭면을 형성하여, 칩탑재판 자체의 두께를 내부리드와 비교하여 얇게 함으로써 결국 반도체패키지의 두께를 종래에 비해 더욱 박형화 할 수 있게 된다.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.
도2는 본 발명에 의한 반도체패키지(100)를 도시한 단면도이다.
도시된 바와 같이 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면에는 칩탑재판(4)이 접착제로 접착되어 있다. 상기 칩탑재판(4)의 외주연에 일정거리 이격되어서는 다수의 내부리드(6)가 형성되어 있고, 상기 반도체칩(2)의 입출력패드(2a)와 내부리드(6)는 도전성와이어(8)로 연결되어 있다. 상기 반도체칩(2), 도전성와이어(8), 칩탑재판(4) 및 내부리드(6) 등은 봉지재로 봉지되어 있되, 상기 칩탑재판(4) 및 내부리드(6)의 저면과 측면은 외부로 노출되도록 봉지되어 패키지몸체(10)를 형성하고 있으며, 이상의 구조는 종래와 동일하다.
단, 본 발명은 상기 칩탑재판(4)의 상면 전체에 할프에칭면(4c)이 형성됨으로써 내부리드(6)의 두께(h1)보다 상기 칩탑재판(4)의 두께(h2)가 더욱 얇게 형성된 것이 특징이다.
상기 칩탑재판(4)의 두께(h2)는 내부리드(6)의 두께(h1)에 비하여 대략 25~75%가 되도록 함이 바람직하지만 이를 한정하는 것은 아니다.
또한, 상기 칩탑재판(4)의 상면 전체에 할프에칭면(4c)을 형성하는 공정은 통상 내부리드(6)에 할프에칭부(6a)를 형성하는 동안 동시에 형성함이 바람직하지만 이를 한정하는 것은 아니다.
상기와 같이 칩탑재판(4)의 상면 전체에 할프에칭면(4c)을 형성함으로써 결국 그것에 탑재되는 반도체칩(2)의 높이도 동시에 작아지게 된다. 그러면, 도전성와이어(8)의 루프 하이트도 작아지게 되고 따라서 반도체패키지(100)의 봉지 공정 동안 발생하던 종래의 와이어 스위핑 문제도 억제된다. 또한 반도체칩(2)의 높이가 종래보다 작아짐으로써 패키지몸체(10)의 두께도 작아지게 되어 결국 반도체패키지(100)의 두께가 종래보다 박형화되는 것이다.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.
따라서 본 발명에 의한 반도체패키지에 의하면, 칩탑재판의 상면 전체에 할프에칭면을 형성하여, 칩탑재판 자체의 두께를 내부리드와 비교하여 얇게 함으로써 결국 패키지몸체 즉, 반도체패키지의 두께를 종래에 비해 더욱 박형화할 수 있는 효과가 있다.
또한 칩탑재판의 두께가 작아짐으로써 그것에 탑재되는 반도체칩의 높이도 작아져 상기 반도체칩과 내부리드를 연결하는 와이어의 루프 하이트도 작아져 와이어 스위핑 문제도 해결할 수 있게 된다.

Claims (2)

  1. 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면에 접착제로 접착된 칩탑재판과; 상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 내부리드와; 상기 반도체칩의 입출력패드와 내부리드를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 봉지재로 봉지하되, 상기 칩탑재판 및 내부리드의 저면과 측면은 외부로 노출되도록 봉지하여 형성된 패키지몸체로 이루어진 반도체패키지에 있어서,
    상기 칩탑재판은 상면 전체에 할프에칭면이 형성되어 내부리드의 두께보다 얇게 형성된 것을 특징으로 하는 반도체패키지.
  2. 제1항에 있어서, 상기 칩탑재판은 두께가 내부리드 두께의 대략 25~75%인 것을 특징으로 하는 반도체패키지.
KR1019990044651A 1999-10-15 1999-10-15 반도체패키지 Ceased KR20010037247A (ko)

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JP2000015004A JP2001077278A (ja) 1999-10-15 2000-01-24 半導体パッケージと、このためのリードフレーム及び、半導体パッケージの製造方法とそのモールド
US09/687,585 US6696747B1 (en) 1999-10-15 2000-10-13 Semiconductor package having reduced thickness
US10/763,859 US7115445B2 (en) 1999-10-15 2004-01-23 Semiconductor package having reduced thickness
US11/492,481 US7321162B1 (en) 1999-10-15 2006-07-25 Semiconductor package having reduced thickness
US11/947,505 US20080283979A1 (en) 1999-10-15 2007-11-29 Semiconductor Package Having Reduced Thickness

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