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WO2018218718A1 - 双向移位寄存器单元、双向移位寄存器及显示面板 - Google Patents

双向移位寄存器单元、双向移位寄存器及显示面板 Download PDF

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Publication number
WO2018218718A1
WO2018218718A1 PCT/CN2017/089702 CN2017089702W WO2018218718A1 WO 2018218718 A1 WO2018218718 A1 WO 2018218718A1 CN 2017089702 W CN2017089702 W CN 2017089702W WO 2018218718 A1 WO2018218718 A1 WO 2018218718A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
circuit
signal
switch
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/089702
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English (en)
French (fr)
Inventor
曾勉
陈书志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US15/545,690 priority Critical patent/US10438676B2/en
Publication of WO2018218718A1 publication Critical patent/WO2018218718A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a bidirectional shift register unit, a bidirectional shift register, and a display panel.
  • a shift register for a liquid crystal display panel is formed by cascading a plurality of shift register units, each scan line is connected to a shift register unit, and a single pulse signal is outputted to a scan line line by line through a shift register. line-by-line scan.
  • the 8CK shift register circuit of 8 clock signals is taken as an example, according to the Nth
  • the stage shift register unit controls charging of the Nth horizontal scanning line G(N) of the display area, the Nth
  • the stage shift register unit includes a pull-up control circuit 101, a pull-up circuit 102, a down-transfer circuit 103, a bootstrap capacitor 104, a pull-down circuit 105, a pull-down sustain circuit 106 and a pull-down sustain circuit 2107.
  • the 8CK shift register circuit can only implement one-way scanning, and the flexibility is not high.
  • the technical problem to be solved by the present invention is to provide a bidirectional shift register unit, a bidirectional shift register and a display panel, which can solve the problem that the existing shift register can only scan in one direction.
  • a technical solution adopted by the present invention is to provide a bidirectional shift register unit, comprising: a pull-up circuit for converting an input first clock signal into a scan signal outputted by the same stage;
  • the control circuit comprises a forward pull-up sub-circuit and a reverse pull-up sub-circuit, wherein the forward pull-up sub-circuit is used to pull up the potential of the pull-up circuit control terminal during forward scanning, and the reverse pull-up sub-circuit is used for reverse scanning Pulling up the potential of the control terminal of the pull-up circuit; pulling down the circuit for pulling down the potential of the scanning signal of the pull-up circuit control terminal and the output of the current stage in the pull-down phase; and pulling down the sustain circuit for continuously pulling down the pull-up circuit in the pull-down phase
  • the pull-down circuit includes a first pull-down circuit and a second pull-down circuit; the first pull-down circuit is configured to pull down the potential of the
  • the pull-down sub-circuit is used to pull down the potential of the pull-up circuit control terminal during the pull-down phase of the reverse scan;
  • the pull-down sustain circuit includes a first pull-down sustain sub-circuit and a second pull-down sustain sub-circuit, the first pull-down sustain sub-circuit and
  • the second pull-down maintaining sub-circuit is configured to continuously pull down the potential of the scan signal outputted by the pull-up circuit control end and the current stage according to the fifth control signal and the sixth control signal respectively in the pull-down phase; wherein the fifth control signal and the sixth control The phases of the signals are complementary, and the potentials of the two are transformed once per preset time period.
  • a bidirectional shift register including a plurality of cascaded bidirectional shift register units;
  • the bidirectional shift register unit includes: a pull-up circuit for The input first clock signal is converted into a scan signal outputted by the stage;
  • the pull-up control circuit includes a forward pull-up sub-circuit and a reverse pull-up sub-circuit, and the forward pull-up sub-circuit is used to pull up the pull-up during forward scanning
  • the potential of the circuit control terminal, the reverse pull-up sub-circuit is used to pull up the potential of the control terminal of the pull-up circuit during the reverse scan;
  • the pull-down circuit is used to pull down the pull-up phase of the pull-up circuit and the output signal of the output of the stage a potential pull-down maintaining circuit for continuously pulling down the potential of the scan signal outputted by the pull-up circuit control terminal and the current stage in the pull-down phase;
  • the number of the first clock signal is m, the first control of the first m
  • a display panel including a bidirectional shift register including a plurality of cascaded bidirectional shift register units;
  • the bidirectional shift register unit includes: a pull-up circuit for converting the input first clock signal into a scan signal of the output of the stage;
  • the pull-up control circuit comprises a forward pull-up sub-circuit and a reverse pull-up sub-circuit, and the forward pull-up sub-circuit is used in the forward direction During scanning, the potential of the control terminal of the pull-up circuit is pulled up, and the reverse pull-up sub-circuit is used to pull up the potential of the control terminal of the pull-up circuit during reverse scanning;
  • the pull-down circuit is used to pull down the pull-up circuit control terminal during the pull-down phase and The potential of the scan signal outputted by the stage;
  • the pull-down sustain circuit is configured to continuously pull down the potential of the scan signal outputted by the pull-up circuit control terminal and the current stage in the pull-down phase;
  • the beneficial effects of the present invention are: different from the prior art, in the bidirectional shift register unit of the present invention, the forward pull-up sub-circuit and the reverse pull-up sub-circuit are used to realize the pull-up in the forward/reverse scan.
  • the potential of the control terminal of the pull-up circuit is pulled down by the pull-down circuit in the pull-down phase to lower the potential of the scan signal of the pull-up circuit control terminal and the output of the current stage, so that the bidirectional shift register unit can perform both forward scan and reverse scan
  • the pull-up circuit converts the clock signal into the output scan signal of the stage, thereby implementing bidirectional scanning and improving circuit flexibility.
  • FIG. 1 is a schematic diagram of a prior art 8CK shift register circuit of the present invention
  • FIG. 2 is a schematic diagram of a circuit principle of an embodiment of a bidirectional shift register unit of the present invention
  • FIG. 3 is a schematic circuit diagram of another embodiment of a bidirectional shift register unit of the present invention.
  • FIG. 4 is a detailed circuit diagram of an embodiment of a bidirectional shift register unit of the present invention.
  • FIG. 5 is a timing chart showing the operation waveforms of the circuit shown in FIG. 4 during forward scanning
  • FIG. 6 is a timing diagram of an operation waveform when the circuit shown in FIG. 4 is reversely scanned;
  • Figure 7 is a detailed circuit diagram of the circuit of Figure 4 applied to the m-stage before the bidirectional register;
  • Figure 8 is a detailed circuit diagram of the circuit of Figure 4 applied to the last m stages of the bidirectional register
  • FIG. 9 is a schematic structural diagram of an embodiment of a bidirectional shift register of the present invention.
  • FIG. 10 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 2 is a schematic diagram of the circuit principle of an embodiment of the bidirectional shift register unit of the present invention.
  • the bidirectional shift register unit 20 of the present embodiment includes:
  • the pull-up circuit 201 is configured to convert the input first clock signal CK into a scan signal G(N) outputted by the stage;
  • the pull-up control circuit 202 includes a forward pull-up sub-circuit 2021 and a reverse pull-up sub-circuit 2022.
  • the forward pull-up sub-circuit 2021 is used to pull up the potential of the control terminal 2012 of the pull-up circuit 201 during forward scanning, and pull up in reverse.
  • the sub-circuit 2022 is configured to pull up the potential of the control terminal 2012 of the pull-up circuit 201 during reverse scanning;
  • a pull-down circuit 203 for pulling down the potential of the pull-up circuit control terminal 2012 and the scan signal G(N) outputted by the current stage in the pull-down phase;
  • the pull-down maintaining circuit 204 is configured to continuously pull down the potential of the pull-up circuit control terminal 2012 and the scan signal G(N) outputted by the stage in the pull-down phase.
  • the input signal of the pull-up circuit 201 is the first clock signal CK, and the control terminal 2012 input signal is Q (N);
  • the input signal of the forward pull-up sub-circuit 2021 is the forward voltage signal VDD_F
  • the input signal of the control terminal is the first control signal ST(Nm/2)
  • the output signal is used to control the potential of Q(N)
  • the input signal of the pull-up sub-circuit 2022 is the reverse voltage signal VDD_R
  • the control terminal input signal is the second control signal ST(N+m/2
  • the output signal is used to control the potential of Q(N)
  • the pull-down circuit 203 is input signal.
  • the control terminal input signal is at least one CN, the output signal is used to pull down the potentials of Q(N) and G(N); the pull-down sustain circuit 204 input signal is the low level signal VSS, and the control terminal The input signal is at least one LC, and the output signal is used to continuously pull down the potentials of Q(N) and G(N) during the pull-down phase.
  • the Q(N) potential is pulled up by the pull-up control circuit 202, and the pull-up circuit 201 converts the first clock signal CK into the scan signal G(N) output of the stage output.
  • the pull-down circuit 203 pulls down the Q(N) and G(N) potentials, while the pull-down sustain circuit 204 continues to pull down the potentials of Q(N) and G(N), thereby causing forward and reverse scans.
  • the bidirectional shift register unit can correctly output the scan signal G(N) outputted by the current stage, thereby implementing bidirectional scanning and improving circuit flexibility.
  • FIG. 3 is a schematic diagram showing the circuit principle of another embodiment of the bidirectional shift register unit of the present invention.
  • the bidirectional shift register unit 30 of the present embodiment is based on the bidirectional shift register unit 20 shown in FIG. 2.
  • the pull-down circuit 203 further includes: a first pull-down circuit 2031 and a second pull-down circuit 2032; The other parts of the circuit of the register unit 30 are the same as those in FIG. 2 and will not be described again here.
  • the first pull-down circuit 2031 is configured to pull down the potential of the scan signal G(N) outputted by the current stage in the pull-down phase;
  • the second pull-down circuit 2032 includes a forward pull-down sub-circuit 20321 and a reverse pull-down sub-circuit 20322;
  • the forward pull-down sub-circuit 20321 is configured to pull down the potential of the control terminal 2012 of the pull-up circuit 201 during the pull-down phase of the forward scan
  • the reverse pull-down sub-circuit 20322 is used to pull down the pull-up during the pull-down phase of the reverse scan.
  • Circuit 201 controls the potential of terminal 2012.
  • the input signals of the first pull-down circuit 2031, the forward pull-down sub-circuit 20321, and the reverse pull-down sub-circuit 20322 are all low.
  • the first pull-down circuit 2031 control terminal input signal is the second clock signal XCK, the output signal is used to control the potential of the output scan signal G(N) of the current stage;
  • the control input signal of the forward pull-down sub-circuit 20321 is The third control signal ST(N+m), the output signal of which is used to control the potential of Q(N);
  • the control input signal of the reverse pull-down sub-circuit 20322 is the fourth control signal ST(Nm), and the output signal is used for control The potential of Q(N).
  • the first pull-down circuit 2031 pulls down the potential of G(N), and the forward pull-down sub-circuit 20321 pulls down the potential of Q(N); in the pull-down phase of the reverse scan, the first pull-down The circuit 2031 pulls down the potential of G(N), and the reverse pull-down sub-circuit 20322 pulls down the potential of Q(N), so that the pull-down phases of the forward and reverse scans, the potentials of Q(N) and G(N) are both It can be pulled down correctly, which enables two-way scanning and improves circuit flexibility.
  • FIG. 4 is a detailed circuit diagram of an embodiment of a bidirectional shift register unit of the present invention.
  • the forward pull-up sub-circuit 2021 includes a first switch tube T11_a, wherein the control of the first switch tube T11_a The first end of the first switch T11_a is coupled to the forward voltage signal VDD_F, the output end of the first switch T11_a is coupled to the control end 2012 of the pull-up circuit 201;
  • the reverse pull-up sub-circuit 2022 includes a second switch tube T11_b, the control end of the second switch tube T2 is coupled to the second control signal ST(N+m/2), and the input end of the second switch tube T11_b is coupled to the reverse voltage signal.
  • VDD_R the output end of the second switching transistor T11_b is coupled to the control terminal 2012 of the pull-up circuit 201;
  • the forward voltage signal VDD_F is a high level signal VGH
  • the reverse voltage signal VDD_R is a low level signal VSS
  • the forward voltage signal VDD_F is a low level signal VSS
  • reverse The voltage signal VDD_R is a high level signal VGH.
  • the pull-down circuit 203 includes a first pull-down circuit 2031 and a second pull-down circuit 2032.
  • the first pull-down circuit 2031 includes a third switch T31, and the control end of the third switch T31 is coupled to the second.
  • the clock signal XCK the input end of the third switch T31 is coupled to the low level signal VSS, the output end of the third switch T31 is coupled to the scan signal G(N) outputted by the stage; and the second pull down circuit 2032 includes a forward pull down Sub-circuit 20321 and reverse pull-down sub-circuit 20322.
  • the forward pull-down sub-circuit 20321 includes a fourth switch T41_a, the control end of the fourth switch T41_a is coupled to the third control signal ST(N+m), and the input end of the fourth switch T41_a is coupled to the low-level signal VSS.
  • the output end of the fourth switch tube T41_a is coupled to the control end 2012 of the pull-up circuit 201;
  • the reverse pull-down sub-circuit 20322 includes a fifth switch tube T41_b, and the control end of the fifth switch tube T41_b is coupled to the fourth control signal ST(Nm)
  • the input end of the fifth switch T41_b is coupled to the low level signal VSS, and the output end of the fifth switch T41_b is coupled to the control end 2012 of the pull-up circuit 201; wherein, the second clock signal XCK and the first clock signal CK phase Complementary.
  • the pull-up circuit 201 includes a sixth switch tube T21 and a bootstrap capacitor Cb, and the control ends of the sixth switch tube T21 are respectively coupled to the pull-up control circuit 202, the pull-down circuit 203, and the pull-down maintaining circuit 204, and the sixth switch tube T21
  • the input end is coupled to the first clock signal CK
  • the output end of the sixth switch T21 is coupled to the scan signal G(N) outputted by the current stage; as shown in FIG. 2, the control ends of the sixth switch T21 are respectively coupled Switch tubes T11_a, T11_b, T41_a, T41_b, T42 , the output of T43, and the control terminals of switch tubes T52, T54, T62, T64.
  • the bootstrap capacitor Cb is coupled between the control terminal and the output terminal of the sixth switch transistor T21 for boosting the potential of the control terminal Q(N) of the sixth switch transistor T21.
  • the pull-up circuit 201 further includes a seventh switch tube T22.
  • the control end of the seventh switch tube T22 is coupled to the control end of the sixth switch tube T21.
  • the input end of the seventh switch tube T22 is coupled to the first clock.
  • the signal CK, the output end of the seventh switch T22 is coupled to the downlink signal ST(N) outputted by the stage for converting the first clock signal CK into the downlink signal ST(N).
  • the pull-down maintaining circuit 204 includes a first pull-down maintaining sub-circuit 2041 and a second pull-down maintaining sub-circuit 2042, and the first pull-down maintaining sub-circuit 2041 and the second pull-down maintaining sub-circuit 2042 are respectively used according to the fifth stage in the pull-down phase.
  • the control signal LC1 and the sixth control signal LC2 continuously pull down the potential of the scan signal G(N) outputted by the control terminal 2012 of the pull-up circuit 201 and the current stage; wherein the phases of the fifth control signal LC1 and the sixth control signal LC2 are complementary, And the potential of the two is changed every 100 frames, and when the pull-down continuous circuit 204 is working, the fifth control signal LC1 And the frequency of the sixth control signal LC2 is lower than the input pull-up circuit 201
  • the first clock signal CK may be a time interval of 10 frames or 20 frames, which is determined according to actual needs, and is not specifically limited herein.
  • the first pull-down maintaining sub-circuit 2041 includes an eighth switching tube T42, a tenth switching tube T32, a twelfth switching tube T54, a fourteenth switching tube T52, a sixteenth switching tube T53, and a 18 switch tube T51;
  • the second pull-down maintaining sub-circuit 2042 includes a ninth switch tube T43, an eleventh switch tube T33, and a thirteenth switch tube T64, which are mirrored with respect to the switch tubes of the first pull-down maintaining sub-circuit 2041,
  • a first control point P (N) a control terminal of the ninth switch tube T43 and the eleventh switch tube T33, and a thirteenth switch
  • the output ends of the tube T64 and the seventeenth switch tube T63 are coupled to the second control point K(N), the output of the fourteenth switch tube T52, the eighteenth switch tube T51, and the control of the sixteenth switch tube T53.
  • the terminals are coupled to the third control point S(N), and the output ends of the fifteenth switch tube T62, the nineteenth switch tube T61, and the control end of the seventeenth switch tube T63 are coupled to each other at the fourth control point T ( N), the input end of the eighteenth switch tube T51, the control end, and the input end of the sixteenth switch tube T53 are coupled to the fifth control signal LC1, the input end of the nineteenth switch tube T61, the control end, and the seventeenth The input end of the switch tube T63 is coupled to the sixth control signal LC2.
  • the first clock input signal of the current stage is CK8, and the bidirectional shift register unit is positively pulling up the sub-circuit 2021 during forward scanning.
  • the input terminal 20211 input signal VDD_F is a high level signal VGH
  • the input terminal 20221 of the reverse pull-up sub-circuit 2022 inputs the signal VDD_R to a low level signal VSS
  • the first control signal ST(N-4) is high level
  • the switch tube T11_a is turned on, and the high level signal VGH pulls up the potential of the control terminal 2012 of the pull-up circuit 201, that is, Q(N) is at a high level, and enters a pull-up phase.
  • the switch tube T21 is turned on, and the first clock signal is turned on.
  • the output scan signal G(N) of this stage is also low level, and there is a voltage difference between the bootstrap capacitor Cb, and the bootstrap capacitor Cb is charged;
  • the first clock signal CK8 is high level,
  • the first control signal ST(N-4) becomes a low level
  • the second control signal ST(N+4) is also at a low level
  • the switching tubes T11_a, T11_b are turned off, and the switching tubes T21 and T22 are turned on, and the output is turned on.
  • the level output scan signal G(N) and the down signal ST(N) are at a high level.
  • the bootstrap capacitor Cb is further advanced.
  • the pull-up phase Q(N) is high level
  • the switch tubes T52, T54, T62, T64 are open
  • the fourth control point T(N) is pulled low by the low level signal VSS
  • the switch tubes T32, T33, T42, T43, T53, T63 are all turned off, so that the pull-up phase, the pull-down continuous circuit 204 does not affect Q The potentials of (N) and G(N).
  • the switch transistor T31 When the first clock signal CK8 becomes a low level, the complementary signal XCK becomes a high level, the switch transistor T31 is turned on, and enters a pull-down phase, and the output scan signal G(N) of the current stage is pulled low by the low level signal VSS.
  • the bootstrap capacitor Cb When the bootstrap capacitor Cb is discharged, the Q(N) potential starts to decrease.
  • the switch T41_a When the third control signal ST(N+8) is high, the switch T41_a is turned on, and the Q(N) potential is pulled by the low level signal VSS.
  • the pull-down continuous circuit 204 starts to work, the sixth control signal LC2 is a high level signal, and in the second pull-down continuous sub-circuit 2042, the switch tube T61 is turned on, and the fourth control point T(N) potential is pulled high.
  • the switch tube T63 is turned on, the potential of the second control point K(N) is pulled high, and the switch tubes T33, T43 are turned on, then the control signal Q(N) of the control terminal 2012 of the pull-up circuit 201 and the output scan signal G of the current stage are output.
  • (N) is continuously pulled low by the low level signal VSS; wherein, when the fifth control signal LC1 is at a high level, the first pull-down continuation sub-circuit 2041 starts to operate, and its operation process and the second pull-down continuation sub-circuit 2042 Similar, it will not be repeated here.
  • the first clock signal CK1 CK CK8 is also used as an example.
  • the first clock signal input to the current stage is CK1.
  • the bidirectional shift register unit is in the forward scan mode when the reverse scan is performed.
  • the input terminal 20211 of the input terminal 20211 is a low level signal VSS
  • the input terminal 20221 of the reverse pull-up sub-circuit 2022 is a high level signal VGH
  • the second control signal ST(N+4) is high.
  • the switch tube T11_b is turned on, and the high level signal VGH pulls up the potential of the control terminal 2012 of the pull-up circuit 201, that is, Q(N) is at a high level, and enters a pull-up phase.
  • the switch tube T21 is turned on, and the first clock is turned on.
  • the signal CK1 is at a low level
  • the output scan signal G(N) of the current stage is also at a low level, and a voltage difference exists between the bootstrap capacitor Cb, and the bootstrap capacitor Cb is charged;
  • the first clock signal CK1 is high level
  • the second control signal ST(N+4) becomes a low level
  • the first control signal ST(N-4) is also at a low level
  • the switch tubes T11_a, T11_b are turned off, and the switch tubes T21 and T22 are turned on, and the output is
  • the output scan signal G(N) and the down signal ST(N) of this stage are at a high level.
  • the bootstrap capacitor Cb The potential of Q(N) is pulled up step by step to ensure that the first clock signal CK1 is in a high level phase, and the switching tubes T21 and T22 are all in an open state, so that the current output scan signal G(N) and the down signal ST(N) are output. At this stage, it is also in a high state, that is, the output scan signal G(N) of this stage is normally output.
  • the pull-up phase Q(N) is high level
  • the switch tubes T52, T54, T62, T64 are open
  • the fourth control point T(N) is pulled low by the low level signal VSS
  • the switch tubes T32, T33, T42, T43, T53, T63 are all turned off, so that the pull-up phase, the pull-down continuous circuit 204 does not affect Q The potentials of (N) and G(N).
  • the switch transistor T31 When the first clock signal CK1 becomes a low level, the complementary signal XCK becomes a high level, the switch transistor T31 is turned on, and enters a pull-down phase, and the output scan signal G(N) of the current stage is pulled low by the low level signal VSS. When the bootstrap capacitor Cb is discharged, the Q(N) potential begins to decrease. When the fourth control signal ST(N-8) is high, the switch T41_a is turned on, and the Q(N) potential is pulled by the low level signal VSS.
  • the pull-down continuous circuit 204 starts to work, the sixth control signal LC2 is a high level signal, and in the second pull-down continuous sub-circuit 2042, the switch tube T61 is turned on, and the fourth control point T(N) potential is pulled high.
  • the switch tube T63 is turned on, the potential of the second control point K(N) is pulled high, and the switch tubes T33, T43 are turned on, then the control signal Q(N) of the control terminal 2012 of the pull-up circuit 201 and the output scan signal G of the current stage are output.
  • (N) is continuously pulled low by the low level signal VSS; wherein, when the fifth control signal LC1 is at a high level, the first pull-down continuation sub-circuit 2041 starts to operate, and its operation process and the second pull-down continuation sub-circuit 2042 Similar, it will not be repeated here.
  • the potentials of the control signals LC1 and LC2 are alternately changed, so that the first pull-down continuation sub-circuit 2041 and the second pull-down continuation sub-circuit 2042 operate alternately to continuously pull down during the pull-down phase.
  • the potential of the signal point Q(N) and the output horizontal scanning line G(N) reduces the long-term switching of the switch tube in DC Bad effects in the Stress state.
  • all of the switching transistors are thin film transistors, the control terminals of which are the gates of the thin film transistors, the input terminals are the sources of the thin film transistors, and the output terminals are the drains of the thin film transistors.
  • the input end of the switch tube may also be the drain of the thin film transistor, and the output end may be the source of the thin film transistor.
  • the switch tube may also be other types of transistors. limited.
  • the first m-level bidirectional shift register unit first control signal ST (Nm/2) portion does not exist, and the fourth control signal ST (Nm) There is no existence. Therefore, as shown in FIG. 7, the first m-level bidirectional shift register unit first control signal adopts a first initial signal STV_F, and the fourth control signal adopts a second initial signal STV_R; similarly, as shown in FIG.
  • the second control signal of the last m-level bidirectional shift register unit adopts a second initial signal STV_R, and the third control signal adopts a first initial signal STV_F; wherein the operation of the circuit shown in FIG. 7 and FIG. 8 can be referred to FIG. The working process of the circuit is not repeated here.
  • the forward pull-up sub-circuit and the reverse pull-up sub-circuit by using the forward pull-up sub-circuit and the reverse pull-up sub-circuit, the potential of the control terminal of the pull-up circuit is pulled up during the forward/reverse scan, and the pull-up circuit is used to pull down the pull-up circuit control terminal in the pull-down phase. And the potential of the scan signal outputted by the current stage, so that the bidirectional shift register unit can cause the pull-up circuit to convert the clock signal into the output scan signal of the stage in the forward scan and the reverse scan, thereby implementing bidirectional scanning. Improve circuit flexibility.
  • FIG. 9 is a schematic structural diagram of an embodiment of a bidirectional shift register according to the present invention.
  • the bidirectional shift register 50 of the present embodiment includes a plurality of cascaded bidirectional shift register units 501, and the bidirectional shift register unit 501 can refer to the bidirectional shift register unit of FIG. 2 or FIG.
  • the specific circuit refer to the detailed circuit of the bidirectional shift register unit shown in FIG. 4, which is not repeated here.
  • the bidirectional shift register unit 501 can be set according to the number of actual scan signals, which is not specifically limited herein.
  • the first control signal of the first m-stage bidirectional shift register unit 501 is the first initial signal STV_F.
  • the fourth control signal of the first m-stage bidirectional shift register unit 501 is the second initial signal STV_R; the second control signal of the last m-stage bidirectional shift register unit 501 is the second initial signal STV_R, and finally the m-level bidirectional shift register
  • the third control signal of the unit 501 is the first initial signal STV_F; the circuit and the control signals of the intermediate bidirectional shift register unit 501 can refer to the circuit shown in FIG. 4, and will not be repeated here.
  • the number of the first clock signal can be set according to actual requirements, and is not specifically limited herein.
  • the working process of the first m-stage bidirectional shift register unit 501 and the last m-level bidirectional shift register unit 501 in the bidirectional shift register 50 can refer to the working process of the bidirectional shift register unit in FIG. Repeat again.
  • the bidirectional shift register includes a plurality of cascaded bidirectional shift register units, and each of the bidirectional shift register units uses a forward pull-up sub-circuit and a reverse pull-up sub-circuit to implement forward/reverse
  • the potential of the control terminal of the pull-up circuit is pulled up, and the pull-down circuit is used to pull down the potential of the scan signal of the pull-up circuit control terminal and the output of the current stage in the pull-down phase, thereby causing the bidirectional shift register unit to scan forward and reverse.
  • the pull-up circuit can convert the clock signal into the output scan signal of the stage, thereby realizing bidirectional scanning and improving circuit flexibility.
  • FIG. 10 is a schematic structural view of an embodiment of a display panel of the present invention.
  • the display panel 80 of the present embodiment includes at least a bidirectional shift register 801.
  • the structure and operation of the bidirectional shift register 801 can be referred to the bidirectional shift register of FIG. 9, and will not be repeated here.
  • the display panel of the present embodiment may be a panel of a type such as a liquid crystal panel or a plasma panel, and is not specifically limited herein.
  • the display panel 80 may further include a TFT substrate, a liquid crystal layer, or the like, as needed, and is not specifically limited herein.
  • the display panel includes at least a bidirectional shift register including a plurality of cascaded bidirectional shift register units, each of the bidirectional shift register units utilizing a forward pull-up sub-circuit and a reverse pull-up
  • the sub-circuit realizes pulling up the potential of the control terminal of the pull-up circuit during the forward/reverse scan, and pulling down the potential of the scan signal of the pull-up circuit control end and the output of the current stage in the pull-down phase by the pull-down circuit, thereby making the bidirectional shift
  • the bit register unit enables the pull-up circuit to convert the clock signal to the output scan signal of the stage during forward scanning and reverse scanning, thereby realizing bidirectional scanning and improving display flexibility.

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Abstract

公开了一种双向移位寄存器单元、双向移位寄存器及显示面板。该双向移位寄存器单元包括：上拉电路（201），用于将输入的第一时钟信号（CK）转换为本级输出的扫描信号（G（N））；上拉控制电路（202），包括正向上拉子电路（2021）和反向上拉子电路（2022），分别用于在正向扫描或反向扫描时，拉高上拉电路控制端（Q（N））的电位；下拉电路（203）和下拉维持电路（204），分别用于在下拉阶段拉低和持续拉低上拉电路控制端（Q（N））和本级输出的扫描信号（G（N））的电位。该移位寄存器单元能够实现双向扫描。

Description

双向移位寄存器单元、双向移位寄存器及显示面板
【技术领域】
本发明涉及显示器技术领域，特别是涉及一种双向移位寄存器单元、双向移位寄存器及显示面板。
【背景技术】
目前，用于液晶显示面板的移位寄存器由多个移位寄存器单元级联而成，每一条扫描线与一个移位寄存器单元连接，通过移位寄存器逐行输出单脉冲信号到扫描线，实现逐行扫描。
本发明的发明人在对现有技术的移位寄存器电路和其工作过程的研究中发现，现有技术的移位寄存器仅能以某一特定方向进行单向扫描，缺乏灵活性。如图1所示的8个时钟信号的8CK移位寄存器电路为例，按照第N 级移位寄存器单元控制对显示区域第N 级水平扫描线G（N）充电，该第N 级移位寄存器单元包括上拉控制电路101，上拉电路102，下传电路103，自举电容104，下拉电路105，下拉维持电路一106和下拉维持电路二107。该电路工作时，由于上拉控制电路101、上拉电路102和下拉电路105的输入信号存在先后时序关系，因此，该8CK移位寄存器电路只能实现单向扫描，灵活性不高。
【发明内容】
本发明主要解决的技术问题是提供一种双向移位寄存器单元、双向移位寄存器及显示面板，能够解决现有移位寄存器只能单向扫描的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种双向移位寄存器单元，包括：上拉电路，用于将输入的第一时钟信号转换为本级输出的扫描信号；上拉控制电路，包括正向上拉子电路和反向上拉子电路，正向上拉子电路用于在正向扫描时，拉高上拉电路控制端的电位，反向上拉子电路用于在反向扫描时，拉高上拉电路控制端的电位；下拉电路，用于在下拉阶段拉低上拉电路控制端和本级输出的扫描信号的电位；下拉维持电路，用于在下拉阶段持续拉低上拉电路控制端和本级输出的扫描信号的电位；下拉电路包括第一下拉电路和第二下拉电路；第一下拉电路用于在下拉阶段拉低本级输出的扫描信号的电位；第二下拉电路包括正向下拉子电路和反向下拉子电路，正向下拉子电路用于在正向扫描的下拉阶段，拉低上拉电路控制端的电位，反向下拉子电路用于在反向扫描的下拉阶段，拉低上拉电路控制端的电位；下拉维持电路包括第一下拉维持子电路和第二下拉维持子电路，第一下拉维持子电路和第二下拉维持子电路用于在下拉阶段分别根据第五控制信号和第六控制信号持续拉低上拉电路控制端和本级输出的扫描信号的电位；其中，第五控制信号和第六控制信号的相位互补，并且二者的电位每一预设时长变换一次。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种双向移位寄存器，包括多个级联的双向移位寄存器单元；双向移位寄存器单元包括：上拉电路，用于将输入的第一时钟信号转换为本级输出的扫描信号；上拉控制电路，包括正向上拉子电路和反向上拉子电路，正向上拉子电路用于在正向扫描时，拉高上拉电路控制端的电位，反向上拉子电路用于在反向扫描时，拉高上拉电路控制端的电位；下拉电路，用于在下拉阶段拉低上拉电路控制端和本级输出的扫描信号的电位；下拉维持电路，用于在下拉阶段持续拉低上拉电路控制端和本级输出的扫描信号的电位；其中，第一时钟信号的个数为m，前m级寄存器单元的第一控制信号为第一初始信号STV_F，前m级寄存器单元的第四控制信号为第二初始信号STV_R；最后m级寄存器单元的第二控制信号为第二初始信号STV_R，最后m级寄存器单元的第三控制信号为第一初始信号STV_F。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示面板，包括双向移位寄存器，该双向寄存器包括多个级联的双向移位寄存器单元；双向移位寄存器单元包括：上拉电路，用于将输入的第一时钟信号转换为本级输出的扫描信号；上拉控制电路，包括正向上拉子电路和反向上拉子电路，正向上拉子电路用于在正向扫描时，拉高上拉电路控制端的电位，反向上拉子电路用于在反向扫描时，拉高上拉电路控制端的电位；下拉电路，用于在下拉阶段拉低上拉电路控制端和本级输出的扫描信号的电位；下拉维持电路，用于在下拉阶段持续拉低上拉电路控制端和本级输出的扫描信号的电位；其中，第一时钟信号的个数为m，前m级寄存器单元的第一控制信号为第一初始信号STV_F，前m级寄存器单元的第四控制信号为第二初始信号STV_R；最后m级寄存器单元的第二控制信号为第二初始信号STV_R，最后m级寄存器单元的第三控制信号为第一初始信号STV_F。
本发明的有益效果是：区别于现有技术的情况，本发明的双向移位寄存器单元中，利用正向上拉子电路和反向上拉子电路，实现在正向/反向扫描时，拉高上拉电路控制端的电位，利用下拉电路在下拉阶段拉低上拉电路控制端和本级输出的扫描信号的电位，从而使得该双向移位寄存器单元在正向扫描和反向扫描时，均能够使得上拉电路将时钟信号转换为本级输出扫描信号，从而实现双向扫描，提高电路灵活性。
【附图说明】
图1是本发明现有技术8CK移位寄存器电路示意图；
图2是本发明双向移位寄存器单元一实施方式的电路原理示意图；
图3是本发明双向移位寄存器单元另一实施方式的电路原理示意图；
图4是本发明双向移位寄存器单元一实施方式的详细电路示意图；
图5是图4所示电路正向扫描时的工作波形时序示意图；
图6是图4所示电路反向扫描时的工作波形时序示意图；
图7是图4所示电路应用于双向寄存器前m级时的详细电路示意图；
图8是图4所示电路应用于双向寄存器最后m级时的详细电路示意图；
图9是本发明双向移位寄存器一实施方式的结构示意图；
图10是本发明显示面板一实施方式的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图2，图2是本发明双向移位寄存器单元一实施方式的电路原理示意图。如图2所示，本实施方式双向移位寄存器单元20包括：
上拉电路201，用于将输入的第一时钟信号CK转换为本级输出的扫描信号G（N）；
上拉控制电路202，包括正向上拉子电路2021和反向上拉子电路2022，正向上拉子电路2021用于在正向扫描时，拉高上拉电路201控制端2012的电位，反向上拉子电路2022用于在反向扫描时，拉高上拉电路201控制端2012的电位；
下拉电路203，用于在下拉阶段拉低上拉电路控制端2012和本级输出的扫描信号G（N）的电位；
下拉维持电路204，用于在下拉阶段持续拉低上拉电路控制端2012和本级输出的扫描信号G（N）的电位。
具体地，如图2所示，以m个第一时钟信号CK1~CKm为例，上拉电路201的输入信号为第一时钟信号CK，其控制端2012输入信号为Q（N）；上拉控制电路202中，正向上拉子电路2021输入信号为正向电压信号VDD_F，其控制端输入信号为第一控制信号ST（N-m/2），输出信号用于控制Q（N）的电位，反向上拉子电路2022输入信号为反向电压信号VDD_R，其控制端输入信号为第二控制信号ST（N+m/2），输出信号用于控制Q（N）的电位；下拉电路203输入信号为低电平信号VSS，其控制端输入信号至少为一个CN，输出信号用于拉低Q（N）和G（N）的电位；下拉维持电路204输入信号为低电平信号VSS，控制端输入信号至少为一个LC，输出信号用于在下拉阶段持续拉低Q（N）和G（N）的电位。
在正向/反向扫描的上拉阶段，Q（N）电位被上拉控制电路202拉高，上拉电路201将第一时钟信号CK转换为本级输出的扫描信号G（N）输出，在下拉阶段，下拉电路203则拉低Q（N）和G（N）电位，而下拉维持电路204持续拉低Q（N）和G（N）的电位，从而使得正向和反向扫描时，该双向移位寄存器单元均能够正确输出本级输出的扫描信号G（N），进而实现双向扫描，提高电路的灵活性。
请参阅图3，图3是本发明双向移位寄存器单元另一实施方式的电路原理示意图。本实施方式双向移位寄存器单元30是在图2所示双向移位寄存器单元20的基础上，下拉电路203进一步包括：第一下拉电路2031和第二下拉电路2032；本实施方式双向移位寄存器单元30其他部分电路与图2中相同，此处不再赘述。
第一下拉电路2031用于在下拉阶段拉低本级输出的扫描信号G（N）的电位；
第二下拉电路2032包括正向下拉子电路20321和反向下拉子电路20322；
其中，正向下拉子电路20321用于在正向扫描的下拉阶段，拉低上拉电路201控制端2012的电位，反向下拉子电路20322用于在反向扫描的下拉阶段，拉低上拉电路201控制端2012的电位。
具体地，如图3所示，以m个第一时钟信号CK1~CKm为例，第一下拉电路2031、正向下拉子电路20321和反向下拉子电路20322的输入信号均为低电平信号VSS，第一下拉电路2031控制端输入信号为第二时钟信号XCK，其输出信号用于控制本级输出扫描信号G（N）的电位；正向下拉子电路20321的控制端输入信号为第三控制信号ST（N+m），其输出信号用于控制Q（N）的电位；反向下拉子电路20322控制端输入信号为第四控制信号ST（N-m），其输出信号用于控制Q（N）的电位。
在正向扫描的下拉阶段，第一下拉电路2031拉低G（N）的电位，正向下拉子电路20321拉低Q（N）的电位；在反向扫描的下拉阶段，第一下拉电路2031拉低G（N）的电位，反向下拉子电路20322拉低Q（N）的电位，从而使得正向和反向扫描的下拉阶段，Q（N）和G（N）的电位均能够被正确拉低，进而实现双向扫描，提高电路的灵活性。
请参阅图4，图4是本发明双向移位寄存器单元一实施方式的详细电路示意图。
具体地，如图4所示，在一个应用例中，以m个第一时钟信号CK1~CKm为例，正向上拉子电路2021包括第一开关管T11_a，其中，第一开关管T11_a的控制端耦接第一控制信号ST（N-m/2），第一开关管T11_a的输入端耦接正向电压信号VDD_F，第一开关管T11_a的输出端耦接上拉电路201的控制端2012；
反向上拉子电路2022包括第二开关管T11_b，第二开关管T2的控制端耦接第二控制信号ST（N+m/2），第二开关管T11_b的输入端耦接反向电压信号VDD_R，第二开关管T11_b的输出端耦接上拉电路201的控制端2012；
其中，正向扫描时，正向电压信号VDD_F为高电平信号VGH，反向电压信号VDD_R为低电平信号VSS；反向扫描时，正向电压信号VDD_F为低电平信号VSS，反向电压信号VDD_R为高电平信号VGH。
如图4所示，下拉电路203包括第一下拉电路2031和第二下拉电路2032；其中，第一下拉电路2031包括第三开关管T31，第三开关管T31的控制端耦接第二时钟信号XCK，第三开关管T31的输入端耦接低电平信号VSS，第三开关管T31的输出端耦接本级输出的扫描信号G（N）；第二下拉电路2032包括正向下拉子电路20321和反向下拉子电路20322。
正向下拉子电路20321包括第四开关管T41_a，第四开关管T41_a的控制端耦接第三控制信号ST（N+m），第四开关管T41_a的输入端耦接低电平信号VSS，第四开关管T41_a的输出端耦接上拉电路201的控制端2012；反向下拉子电路20322包括第五开关管T41_b，第五开关管T41_b的控制端耦接第四控制信号ST（N-m），第五开关管T41_b的输入端耦接低电平信号VSS，第五开关管T41_b的输出端耦接上拉电路201的控制端2012；其中，第二时钟信号XCK和第一时钟信号CK相位互补。
进一步地，上拉电路201包括第六开关管T21和自举电容Cb，第六开关管T21的控制端分别耦接上拉控制电路202、下拉电路203和下拉维持电路204，第六开关管T21的输入端耦接第一时钟信号CK，第六开关管T21的输出端耦接本级输出的扫描信号G（N）；具体如图2所示，第六开关管T21的控制端分别耦接开关管T11_a、T11_b、T41_a、T41_b、T42 、T43的输出端，以及开关管T52、T54、T62、T64的控制端。
自举电容Cb耦接于第六开关管T21的控制端和输出端之间，用于拉高第六开关管T21控制端控制信号Q（N）的电位。
如图4所示，上拉电路201进一步包括第七开关管T22，第七开关管T22的控制端耦接第六开关管T21的控制端，第七开关管T22的输入端耦接第一时钟信号CK，第七开关管T22的输出端耦接本级输出的下传信号ST（N），用于将第一时钟信号CK转换为下传信号ST（N）。
进一步地，下拉维持电路204包括第一下拉维持子电路2041和第二下拉维持子电路2042，第一下拉维持子电路2041和第二下拉维持子电路2042用于在下拉阶段分别根据第五控制信号LC1和第六控制信号LC2持续拉低上拉电路201控制端2012和本级输出的扫描信号G（N）的电位；其中，第五控制信号LC1和第六控制信号LC2的相位互补，并且二者的电位每100帧变换一次，并且在下拉持续电路204工作时，第五控制信号LC1 和第六控制信号LC2 的频率低于输入上拉电路201 的第一时钟信号CK。当然，在其他实施方式中，控制信号LC1、LC2的电位变化时间可以是10帧或20帧等时间间隔，具体视实际需求而定，此处不做具体限定。
具体如图4所示，第一下拉维持子电路2041包括第八开关管T42、第十开关管T32、第十二开关管T54、第十四开关管T52、第十六开关管T53和第十八开关管T51；第二下拉维持子电路2042包括相对于第一下拉维持子电路2041各开关管镜像设置的第九开关管T43、第十一开关管T33、第十三开关管T64、第十五开关管T62、第十七开关管T63和第十九开关管T61；其中，开关管T32、T33、T42、T43、T52、T54、T62和T64的输入端均耦接低电平信号VSS，开关管T42~T43的输出端耦接第七开关管T22的控制端，开关管T32~T33的输出端耦接本级输出扫描信号G（N），开关管T52、T54、T62、T64的控制端耦接第七开关管T22的控制端，第八开关管T42和第十开关管T32的控制端，以及第十二开关管T54、第十六开关管T53的输出端相互耦接于第一控制点P（N），第九开关管T43和第十一开关管T33的控制端，以及第十三开关管T64、第十七开关管T63的输出端相互耦接于第二控制点K（N），第十四开关管T52、第十八开关管T51的输出端以及第十六开关管T53的控制端相互耦接于第三控制点S（N），第十五开关管T62、第十九开关管T61的输出端以及第十七开关管T63的控制端相互耦接于第四控制点T（N），第十八开关管T51的输入端、控制端以及第十六开关管T53的输入端耦接于第五控制信号LC1，第十九开关管T61的输入端、控制端以及第十七开关管T63的输入端耦接于第六控制信号LC2。
结合图4和图5所示，以8个第一时钟信号CK1~CK8，本级输入第一时钟信号是CK8为例，该双向移位寄存器单元在正向扫描时，正向上拉子电路2021的输入端20211输入信号VDD_F为高电平信号VGH，反向上拉子电路2022的输入端20221输入信号VDD_R为低电平信号VSS，第一控制信号ST（N-4）高电平来临时，开关管T11_a打开，高电平信号VGH拉高上拉电路201控制端2012的电位，即Q（N）为高电平，进入上拉阶段，此时，开关管T21打开，而第一时钟信号CK8为低电平，则本级输出扫描信号G（N）也为低电平，自举电容Cb两端存在电压差，自举电容Cb充电；当第一时钟信号CK8高电平来临时，第一控制信号ST（N-4）变为低电平，第二控制信号ST（N+4）也为低电平，开关管T11_a、T11_b关闭，开关管T21、T22打开，则输出的本级输出扫描信号G（N）和下传信号ST（N）为高电平，此时，自举电容Cb进一步拉高Q（N）的电位，保证第一时钟信号CK8高电平阶段，开关管T21、T22均处于打开状态，从而使得本级输出扫描信号G（N）和下传信号ST（N）在此阶段也处于高电平状态，即本级输出扫描信号G（N）正常输出。
同时，上拉阶段Q（N）为高电平，开关管T52、T54、T62、T64打开，第一控制点P（N）、第二控制点K（N）、第三控制点S（N）和第四控制点T（N）均被低电平信号VSS拉低，则开关管T32、T33、T42、T43、T53、T63均关闭，从而使得上拉阶段，下拉持续电路204不影响Q（N）和G（N）的电位。
当第一时钟信号CK8变为低电平时，其互补信号XCK变为高电平，开关管T31打开，进入下拉阶段，本级输出扫描信号G（N）被低电平信号VSS拉低，此时，自举电容Cb放电，Q（N）电位开始下降，当第三控制信号ST（N+8）高电平来临时，开关管T41_a打开，Q（N）电位被低电平信号VSS拉低，此时，下拉持续电路204开始工作，第六控制信号LC2为高电平信号，第二下拉持续子电路2042中，开关管T61打开，则第四控制点T（N）电位被拉高，开关管T63打开，第二控制点K（N）电位被拉高，则开关管T33、T43打开，则上拉电路201的控制端2012的控制信号Q（N）和本级输出扫描信号G（N）的电位持续被低电平信号VSS拉低；其中，当第五控制信号LC1为高电平时，第一下拉持续子电路2041开始工作，其工作过程与第二下拉持续子电路2042类似，此处不再重复。
结合图4和图6所示，同样以8个第一时钟信号CK1~CK8，本级输入第一时钟信号是CK1为例，该双向移位寄存器单元在反向扫描时，正向上拉子电路2021的输入端20211输入信号VDD_F为低电平信号VSS，反向上拉子电路2022的输入端20221输入信号VDD_R为高电平信号VGH，第二控制信号ST（N+4）高电平来临时，开关管T11_b打开，高电平信号VGH拉高上拉电路201控制端2012的电位，即Q（N）为高电平，进入上拉阶段，此时，开关管T21打开，而第一时钟信号CK1为低电平，则本级输出扫描信号G（N）也为低电平，自举电容Cb两端存在电压差，自举电容Cb充电；当第一时钟信号CK1高电平来临时，第二控制信号ST（N+4）变为低电平，第一控制信号ST（N-4）也为低电平，开关管T11_a、T11_b关闭，开关管T21、T22打开，则输出的本级输出扫描信号G（N）和下传信号ST（N）为高电平，此时，自举电容Cb进一步拉高Q（N）的电位，保证第一时钟信号CK1高电平阶段，开关管T21、T22均处于打开状态，从而使得本级输出扫描信号G（N）和下传信号ST（N）在此阶段也处于高电平状态，即本级输出扫描信号G（N）正常输出。
同时，上拉阶段Q（N）为高电平，开关管T52、T54、T62、T64打开，第一控制点P（N）、第二控制点K（N）、第三控制点S（N）和第四控制点T（N）均被低电平信号VSS拉低，则开关管T32、T33、T42、T43、T53、T63均关闭，从而使得上拉阶段，下拉持续电路204不影响Q（N）和G（N）的电位。
当第一时钟信号CK1变为低电平时，其互补信号XCK变为高电平，开关管T31打开，进入下拉阶段，本级输出扫描信号G（N）被低电平信号VSS拉低，此时，自举电容Cb放电，Q（N）电位开始下降，当第四控制信号ST（N-8）高电平来临时，开关管T41_a打开，Q（N）电位被低电平信号VSS拉低，此时，下拉持续电路204开始工作，第六控制信号LC2为高电平信号，第二下拉持续子电路2042中，开关管T61打开，则第四控制点T（N）电位被拉高，开关管T63打开，第二控制点K（N）电位被拉高，则开关管T33、T43打开，则上拉电路201的控制端2012的控制信号Q（N）和本级输出扫描信号G（N）的电位持续被低电平信号VSS拉低；其中，当第五控制信号LC1为高电平时，第一下拉持续子电路2041开始工作，其工作过程与第二下拉持续子电路2042类似，此处不再重复。
在正向扫描和反向扫描的下拉阶段，控制信号LC1和LC2的电位均交替变化，使得第一下拉持续子电路2041和第二下拉持续子电路2042交替工作，以在下拉阶段持续拉低信号点Q（N）和输出水平扫描线G（N）的电位，减轻开关管长期处于DC Stress状态时的不良影响。
本实施方式中，所有开关管均为薄膜晶体管，其控制端均为薄膜晶体管的栅极，输入端均为薄膜晶体管的源极，输出端均为薄膜晶体管的漏极。当然，在其他实施方式中，开关管的输入端也可以是薄膜晶体管的漏极，而输出端可以是薄膜晶体管的源极，此外，开关管也可以是其他类型的晶体管，此处不做具体限定。
此外，本实施方式的双向移位寄存器单元在应用于双向移位寄存器时，前m级双向移位寄存器单元第一控制信号ST（N-m/2）部分不存在，而第四控制信号ST（N-m）不存在，因此，如图7所示，前m级双向移位寄存器单元第一控制信号采用第一初始信号STV_F，第四控制信号采用第二初始信号STV_R；类似地，如图8所示，最后m级双向移位寄存器单元的第二控制信号采用第二初始信号STV_R，第三控制信号采用第一初始信号STV_F；其中，图7和图8所示电路的工作过程可以参考图4所示电路的工作过程，此处不再重复。
上述实施方式中，利用正向上拉子电路和反向上拉子电路，实现在正向/反向扫描时，拉高上拉电路控制端的电位，利用下拉电路在下拉阶段拉低上拉电路控制端和本级输出的扫描信号的电位，从而使得该双向移位寄存器单元在正向扫描和反向扫描时，均能够使得上拉电路将时钟信号转换为本级输出扫描信号，从而实现双向扫描，提高电路灵活性。
请参阅图9，图9是本发明双向移位寄存器一实施方式的结构示意图。如图9所示，本实施方式的双向移位寄存器50包括：多个级联的双向移位寄存器单元501，该双向移位寄存器单元501可以参考图2或图3中的双向移位寄存器单元，其具体电路可以参考图4所示双向移位寄存器单元的详细电路，此处不再重复。其中，双向移位寄存器单元501可以根据实际扫描信号个数设置，此处不做具体限定。
具体地，在一个应用例中，结合图7和图8所示，以m第一时钟信号CK1~CKm为例，前m级双向移位寄存器单元501的第一控制信号为第一初始信号STV_F，前m级双向移位寄存器单元501的第四控制信号为第二初始信号STV_R；最后m级双向移位寄存器单元501的第二控制信号为第二初始信号STV_R，最后m级双向移位寄存器单元501的第三控制信号为第一初始信号STV_F；中间各级双向移位寄存器单元501的电路与各控制信号可参考图4所示电路，此处不再重复。其中，第一时钟信号的个数可以根据实际需求设置，此处不做具体限定。
其中，该双向移位寄存器50中，前m级双向移位寄存器单元501和最后m级双向移位寄存器单元501的工作过程可参考图4中的双向移位寄存器单元的工作过程，此处不再重复。
本实施方式中，双向移位寄存器包括多个级联的双向移位寄存器单元，每个双向移位寄存器单元中，利用正向上拉子电路和反向上拉子电路，实现在正向/反向扫描时，拉高上拉电路控制端的电位，利用下拉电路在下拉阶段拉低上拉电路控制端和本级输出的扫描信号的电位，从而使得该双向移位寄存器单元在正向扫描和反向扫描时，均能够使得上拉电路将时钟信号转换为本级输出扫描信号，从而实现双向扫描，提高电路灵活性。
请参阅图10，图10是本发明显示面板一实施方式的结构示意图。如图10所示，本实施方式的显示面板80至少包括双向移位寄存器801，该双向移位寄存器801的结构和工作过程可以参考图9中的双向移位寄存器，此处不再重复。
本实施方式的显示面板可以是液晶面板、等离子面板等类型的面板，此处不做具体限定。
当然，在其他实施方式中，显示面板80视具体需求还可以包括TFT基板、液晶层等结构，此处不做具体限定。
本实施方式中，显示面板至少包括双向移位寄存器，该双向移位寄存器包括多个级联的双向移位寄存器单元，每个双向移位寄存器单元中，利用正向上拉子电路和反向上拉子电路，实现在正向/反向扫描时，拉高上拉电路控制端的电位，利用下拉电路在下拉阶段拉低上拉电路控制端和本级输出的扫描信号的电位，从而使得该双向移位寄存器单元在正向扫描和反向扫描时，均能够使得上拉电路将时钟信号转换为本级输出扫描信号，从而实现双向扫描，提高显示灵活性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种双向移位寄存器单元，其中，包括：
    上拉电路，用于将输入的第一时钟信号转换为本级输出的扫描信号；
    上拉控制电路，包括正向上拉子电路和反向上拉子电路，所述正向上拉子电路用于在正向扫描时，拉高所述上拉电路控制端的电位，所述反向上拉子电路用于在反向扫描时，拉高所述上拉电路控制端的电位；
    下拉电路，用于在下拉阶段拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    下拉维持电路，用于在所述下拉阶段持续拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    所述下拉电路包括第一下拉电路和第二下拉电路；
    所述第一下拉电路用于在下拉阶段拉低所述本级输出的扫描信号的电位；
    所述第二下拉电路包括正向下拉子电路和反向下拉子电路，所述正向下拉子电路用于在正向扫描的下拉阶段，拉低所述上拉电路控制端的电位，所述反向下拉子电路用于在反向扫描的下拉阶段，拉低所述上拉电路控制端的电位；
    所述下拉维持电路包括第一下拉维持子电路和第二下拉维持子电路，所述第一下拉维持子电路和第二下拉维持子电路用于在下拉阶段分别根据第五控制信号和第六控制信号持续拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    其中，所述第五控制信号和所述第六控制信号的相位互补，并且二者的电位每一预设时长变换一次。
  2. 根据权利要求1所述的寄存器单元，其中，
    所述正向上拉子电路包括第一开关管，所述第一开关管的控制端耦接第一控制信号，所述第一开关管的输入端耦接正向电压信号，所述第一开关管的输出端耦接所述上拉电路的控制端；
    所述反向上拉子电路包括第二开关管，所述第二开关管的控制端耦接第二控制信号，所述第二开关管的输入端耦接反向电压信号，所述第二开关管的输出端耦接所述上拉电路的控制端；
    其中，正向扫描时，所述正向电压信号为高电平信号，所述反向电压信号为低电平信号；反向扫描时，所述正向电压信号为低电平信号，所述反向电压信号为高电平信号。
  3. 根据权利要求2所述的寄存器单元，其中，
    所述第一下拉电路包括第三开关管，所述第三开关管的控制端耦接第二时钟信号，所述第三开关管的输入端耦接低电平信号，所述第三开关管的输出端耦接所述本级输出的扫描信号；
    所述正向下拉子电路包括第四开关管，所述第四开关管的控制端耦接第三控制信号，所述第四开关管的输入端耦接低电平信号，所述第四开关管的输出端耦接所述上拉电路的控制端；
    所述反向下拉子电路包括第五开关管，所述第五开关管的控制端耦接第四控制信号，所述第五开关管的输入端耦接低电平信号，所述第五开关管的输出端耦接所述上拉电路的控制端；
    其中，所述第二时钟信号和所述第一时钟信号相位互补。
  4. 根据权利要求3所述的寄存器单元，其中，
    所述上拉电路至少包括第六开关管和自举电容，所述第六开关管的控制端分别耦接所述上拉控制电路、所述下拉电路和所述下拉维持电路，所述第六开关管的输入端耦接所述第一时钟信号，所述第六开关管的输出端耦接所述本级输出的扫描信号；
    所述自举电容耦接于所述第六开关管的控制端和输出端之间，用于拉高所述第六开关管控制端的电位；
    所述上拉电路进一步包括第七开关管，所述第七开关管的控制端耦接所述第六开关管的控制端，所述第七开关管的输入端耦接所述第一时钟信号，所述第七开关管的输出端耦接本级输出的下传信号，进一步用于将所述第一时钟信号转换为所述下传信号；
    所述第一时钟信号的个数为m，第N级寄存器单元的所述下传信号为ST（N），第N级寄存器单元的所述第一控制信号为ST（N-m/2），第N级寄存器单元的所述第二控制信号为ST（N+m/2），第N级寄存器单元的所述第三控制信号为ST（N-m），第N级寄存器单元的所述第四控制信号为ST（N+m）。
  5. 一种双向移位寄存器，其中，包括多个级联的双向移位寄存器单元；
    所述双向移位寄存器单元包括：
    上拉电路，用于将输入的第一时钟信号转换为本级输出的扫描信号；
    上拉控制电路，包括正向上拉子电路和反向上拉子电路，所述正向上拉子电路用于在正向扫描时，拉高所述上拉电路控制端的电位，所述反向上拉子电路用于在反向扫描时，拉高所述上拉电路控制端的电位；
    下拉电路，用于在下拉阶段拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    下拉维持电路，用于在所述下拉阶段持续拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    其中，第一时钟信号的个数为m，前m级所述寄存器单元的第一控制信号为第一初始信号STV_F，前m级所述寄存器单元的第四控制信号为第二初始信号STV_R；
    最后m级所述寄存器单元的第二控制信号为第二初始信号STV_R，最后m级所述寄存器单元的第三控制信号为第一初始信号STV_F。
  6. 根据权利要求5所述的双向移位寄存器，其中，
    所述下拉电路包括第一下拉电路和第二下拉电路；
    所述第一下拉电路用于在下拉阶段拉低所述本级输出的扫描信号的电位；
    所述第二下拉电路包括正向下拉子电路和反向下拉子电路，所述正向下拉子电路用于在正向扫描的下拉阶段，拉低所述上拉电路控制端的电位，所述反向下拉子电路用于在反向扫描的下拉阶段，拉低所述上拉电路控制端的电位。
  7. 根据权利要求6所述的双向移位寄存器，其中，
    所述正向上拉子电路包括第一开关管，所述第一开关管的控制端耦接第一控制信号，所述第一开关管的输入端耦接正向电压信号，所述第一开关管的输出端耦接所述上拉电路的控制端；
    所述反向上拉子电路包括第二开关管，所述第二开关管的控制端耦接第二控制信号，所述第二开关管的输入端耦接反向电压信号，所述第二开关管的输出端耦接所述上拉电路的控制端；
    其中，正向扫描时，所述正向电压信号为高电平信号，所述反向电压信号为低电平信号；反向扫描时，所述正向电压信号为低电平信号，所述反向电压信号为高电平信号。
  8. 根据权利要求7所述的双向移位寄存器，其中，
    所述第一下拉电路包括第三开关管，所述第三开关管的控制端耦接第二时钟信号，所述第三开关管的输入端耦接低电平信号，所述第三开关管的输出端耦接所述本级输出的扫描信号；
    所述正向下拉子电路包括第四开关管，所述第四开关管的控制端耦接第三控制信号，所述第四开关管的输入端耦接低电平信号，所述第四开关管的输出端耦接所述上拉电路的控制端；
    所述反向下拉子电路包括第五开关管，所述第五开关管的控制端耦接第四控制信号，所述第五开关管的输入端耦接低电平信号，所述第五开关管的输出端耦接所述上拉电路的控制端；
    其中，所述第二时钟信号和所述第一时钟信号相位互补。
  9. 根据权利要求8所述的双向移位寄存器，其中，
    所述上拉电路至少包括第六开关管和自举电容，所述第六开关管的控制端分别耦接所述上拉控制电路、所述下拉电路和所述下拉维持电路，所述第六开关管的输入端耦接所述第一时钟信号，所述第六开关管的输出端耦接所述本级输出的扫描信号；
    所述自举电容耦接于所述第六开关管的控制端和输出端之间，用于拉高所述第六开关管控制端的电位。
  10. 根据权利要求9所述的双向移位寄存器，其中，
    所述上拉电路进一步包括第七开关管，所述第七开关管的控制端耦接所述第六开关管的控制端，所述第七开关管的输入端耦接所述第一时钟信号，所述第七开关管的输出端耦接本级输出的下传信号，进一步用于将所述第一时钟信号转换为所述下传信号。
  11. 根据权利要求10所述的双向移位寄存器，其中，
    所述第一时钟信号的个数为m，第N级寄存器单元的所述下传信号为ST（N），第N级寄存器单元的所述第一控制信号为ST（N-m/2），第N级寄存器单元的所述第二控制信号为ST（N+m/2），第N级寄存器单元的所述第三控制信号为ST（N-m），第N级寄存器单元的所述第四控制信号为ST（N+m）。
  12. 根据权利要求5所述的双向移位寄存器，其中，
    所述下拉维持电路包括第一下拉维持子电路和第二下拉维持子电路，所述第一下拉维持子电路和第二下拉维持子电路用于在下拉阶段分别根据第五控制信号和第六控制信号持续拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    其中，所述第五控制信号和所述第六控制信号的相位互补，并且二者的电位每一预设时长变换一次。
  13. 一种显示面板，其中，包括双向移位寄存器，所述双向寄存器包括多个级联的双向移位寄存器单元；
    所述双向移位寄存器单元包括：
    上拉电路，用于将输入的第一时钟信号转换为本级输出的扫描信号；
    上拉控制电路，包括正向上拉子电路和反向上拉子电路，所述正向上拉子电路用于在正向扫描时，拉高所述上拉电路控制端的电位，所述反向上拉子电路用于在反向扫描时，拉高所述上拉电路控制端的电位；
    下拉电路，用于在下拉阶段拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    下拉维持电路，用于在所述下拉阶段持续拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    其中，第一时钟信号的个数为m，前m级所述寄存器单元的第一控制信号为第一初始信号STV_F，前m级所述寄存器单元的第四控制信号为第二初始信号STV_R；最后m级所述寄存器单元的第二控制信号为第二初始信号STV_R，最后m级所述寄存器单元的第三控制信号为第一初始信号STV_F。
  14. 根据权利要求13所述的显示面板，其中，
    所述下拉电路包括第一下拉电路和第二下拉电路；
    所述第一下拉电路用于在下拉阶段拉低所述本级输出的扫描信号的电位；
    所述第二下拉电路包括正向下拉子电路和反向下拉子电路，所述正向下拉子电路用于在正向扫描的下拉阶段，拉低所述上拉电路控制端的电位，所述反向下拉子电路用于在反向扫描的下拉阶段，拉低所述上拉电路控制端的电位。
  15. 根据权利要求14所述的显示面板，其中，
    所述正向上拉子电路包括第一开关管，所述第一开关管的控制端耦接第一控制信号，所述第一开关管的输入端耦接正向电压信号，所述第一开关管的输出端耦接所述上拉电路的控制端；
    所述反向上拉子电路包括第二开关管，所述第二开关管的控制端耦接第二控制信号，所述第二开关管的输入端耦接反向电压信号，所述第二开关管的输出端耦接所述上拉电路的控制端；
    其中，正向扫描时，所述正向电压信号为高电平信号，所述反向电压信号为低电平信号；反向扫描时，所述正向电压信号为低电平信号，所述反向电压信号为高电平信号。
  16. 根据权利要求15所述的显示面板，其中，
    所述第一下拉电路包括第三开关管，所述第三开关管的控制端耦接第二时钟信号，所述第三开关管的输入端耦接低电平信号，所述第三开关管的输出端耦接所述本级输出的扫描信号；
    所述正向下拉子电路包括第四开关管，所述第四开关管的控制端耦接第三控制信号，所述第四开关管的输入端耦接低电平信号，所述第四开关管的输出端耦接所述上拉电路的控制端；
    所述反向下拉子电路包括第五开关管，所述第五开关管的控制端耦接第四控制信号，所述第五开关管的输入端耦接低电平信号，所述第五开关管的输出端耦接所述上拉电路的控制端；
    其中，所述第二时钟信号和所述第一时钟信号相位互补。
  17. 根据权利要求16所述的显示面板，其中，
    所述上拉电路至少包括第六开关管和自举电容，所述第六开关管的控制端分别耦接所述上拉控制电路、所述下拉电路和所述下拉维持电路，所述第六开关管的输入端耦接所述第一时钟信号，所述第六开关管的输出端耦接所述本级输出的扫描信号；
    所述自举电容耦接于所述第六开关管的控制端和输出端之间，用于拉高所述第六开关管控制端的电位。
  18. 根据权利要求17所述的显示面板，其中，
    所述上拉电路进一步包括第七开关管，所述第七开关管的控制端耦接所述第六开关管的控制端，所述第七开关管的输入端耦接所述第一时钟信号，所述第七开关管的输出端耦接本级输出的下传信号，进一步用于将所述第一时钟信号转换为所述下传信号。
  19. 根据权利要求18所述的显示面板，其中，
    所述第一时钟信号的个数为m，第N级寄存器单元的所述下传信号为ST（N），第N级寄存器单元的所述第一控制信号为ST（N-m/2），第N级寄存器单元的所述第二控制信号为ST（N+m/2），第N级寄存器单元的所述第三控制信号为ST（N-m），第N级寄存器单元的所述第四控制信号为ST（N+m）。
  20. 根据权利要求13所述的显示面板，其中，
    所述下拉维持电路包括第一下拉维持子电路和第二下拉维持子电路，所述第一下拉维持子电路和第二下拉维持子电路用于在下拉阶段分别根据第五控制信号和第六控制信号持续拉低所述上拉电路控制端和所述本级输出的扫描信号的电位；
    其中，所述第五控制信号和所述第六控制信号的相位互补，并且二者的电位每一预设时长变换一次。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331418B (zh) * 2017-07-31 2020-06-19 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路及显示装置
CN107578756B (zh) * 2017-10-16 2020-04-14 深圳市华星光电技术有限公司 一种goa电路
CN107808650B (zh) * 2017-11-07 2023-08-01 深圳市华星光电半导体显示技术有限公司 Goa电路
CN107863079A (zh) * 2017-11-29 2018-03-30 武汉华星光电技术有限公司 一种goa电路嵌入式触控显示面板
CN108847193A (zh) * 2018-06-20 2018-11-20 深圳市华星光电半导体显示技术有限公司 Goa电路及具有该goa电路的液晶显示装置
US10810923B2 (en) * 2018-07-18 2020-10-20 Shenzhen China Star Optoelectronics Technology Co., Ltd. GOA circuit and display panel and display device including the same
CN108962171B (zh) 2018-07-27 2020-02-18 深圳市华星光电半导体显示技术有限公司 Goa电路及具有该goa电路的液晶显示装置
CN109064961B (zh) * 2018-07-30 2020-04-28 深圳市华星光电技术有限公司 显示面板goa电路
CN109119041B (zh) * 2018-09-25 2020-05-22 深圳市华星光电技术有限公司 Goa电路结构
CN109616068A (zh) * 2019-01-04 2019-04-12 深圳市华星光电半导体显示技术有限公司 Goa扫描电路和液晶显示装置
CN111081196B (zh) * 2019-12-24 2021-06-01 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN111292699B (zh) * 2020-03-31 2021-03-16 Tcl华星光电技术有限公司 双向输出goa电路及无缝拼接屏
CN111540327B (zh) * 2020-05-21 2021-12-03 武汉华星光电技术有限公司 Goa电路及显示面板
CN114067759B (zh) * 2020-07-31 2022-12-23 滁州惠科光电科技有限公司 一种显示面板的栅极驱动电路及其驱动方法和显示装置
CN115641803B (zh) * 2022-11-02 2025-07-25 惠州华星光电显示有限公司 栅极驱动电路及显示面板
TWI856700B (zh) * 2023-06-12 2024-09-21 友達光電股份有限公司 顯示器
CN117475950B (zh) * 2023-08-28 2026-01-13 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN117877438A (zh) 2024-02-01 2024-04-12 广州华星光电半导体显示技术有限公司 栅极驱动电路及显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101937718A (zh) * 2010-08-04 2011-01-05 友达光电股份有限公司 双向移位寄存器
CN101989463A (zh) * 2009-08-07 2011-03-23 胜华科技股份有限公司 双向移位寄存器
US20150310929A1 (en) * 2014-04-24 2015-10-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display module, and electronic device
CN106205539A (zh) * 2016-08-31 2016-12-07 深圳市华星光电技术有限公司 一种双向扫描的栅极驱动电路、液晶显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859630A (en) * 1996-12-09 1999-01-12 Thomson Multimedia S.A. Bi-directional shift register
JP4190921B2 (ja) * 2002-04-10 2008-12-03 シャープ株式会社 駆動回路及びそれを備えた表示装置
US6937687B2 (en) * 2003-10-21 2005-08-30 Au Optronics Corporation Bi-directional shift register control circuit
TWI346932B (en) * 2005-08-30 2011-08-11 Chi Mei El Corp Bidirectional shift register
KR101243807B1 (ko) 2006-06-30 2013-03-18 엘지디스플레이 주식회사 쉬프트 레지스터
US8937614B2 (en) 2007-11-06 2015-01-20 Nlt Technologies, Ltd. Bidirectional shift register and display device using the same
JP5224241B2 (ja) * 2007-11-06 2013-07-03 Ｎｌｔテクノロジー株式会社 双方向シフトレジスタ、それを用いた表示装置
KR101481675B1 (ko) 2011-10-04 2015-01-22 엘지디스플레이 주식회사 양 방향 쉬프트 레지스터
TWI460699B (zh) * 2012-04-06 2014-11-11 Innocom Tech Shenzhen Co Ltd 影像顯示系統與雙向移位暫存器電路
CN102945651B (zh) 2012-10-31 2015-02-25 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路和显示装置
CN106023933B (zh) 2016-07-21 2019-02-15 深圳市华星光电技术有限公司 一种goa电路及液晶显示器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989463A (zh) * 2009-08-07 2011-03-23 胜华科技股份有限公司 双向移位寄存器
CN101937718A (zh) * 2010-08-04 2011-01-05 友达光电股份有限公司 双向移位寄存器
US20150310929A1 (en) * 2014-04-24 2015-10-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display module, and electronic device
CN106205539A (zh) * 2016-08-31 2016-12-07 深圳市华星光电技术有限公司 一种双向扫描的栅极驱动电路、液晶显示面板

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