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WO2017088265A1 - 一种栅极驱动电路及其显示器 - Google Patents

一种栅极驱动电路及其显示器 Download PDF

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Publication number
WO2017088265A1
WO2017088265A1 PCT/CN2015/099698 CN2015099698W WO2017088265A1 WO 2017088265 A1 WO2017088265 A1 WO 2017088265A1 CN 2015099698 W CN2015099698 W CN 2015099698W WO 2017088265 A1 WO2017088265 A1 WO 2017088265A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
path
path end
gate driving
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/099698
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English (en)
French (fr)
Inventor
王笑笑
杜鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/905,879 priority Critical patent/US10008170B2/en
Publication of WO2017088265A1 publication Critical patent/WO2017088265A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention relates to a display, in particular to a gate driver (Gate driver on Array, GOA) display of the circuit.
  • GOA Gate driver on Array
  • Gate on array Is a commonly used method to reduce costs, it is to make the function of the transistor gate through the thin film transistor-liquid crystal display (TFT-LCD) process on the glass substrate, eliminating the gate side driver integrated circuit (IC), reducing At the same time of cost, it can also achieve no borders and enhance the market competitiveness of products.
  • TFT-LCD thin film transistor-liquid crystal display
  • IC gate side driver integrated circuit
  • the metal traces of the panel and the thin film transistor (TFT) of the pixel switch should be compressed to a small extent as much as possible, which will inevitably lead to pixel charging in the prior art. Insufficient, it will directly affect the display effect of the panel.
  • TFT thin film transistor
  • an embodiment of the present invention provides a gate driving circuit including a plurality of gate driving units, wherein the plurality of gate driving units are coupled in series, and the Nth stage gate driving unit Used to output the Nth stage gate pulse signal at the output.
  • the Nth stage gate driving unit includes: a first switch component including a first control end, a first path end, and a second path end, wherein the first path end and the first control end are coupled to the N-4th a first start pulse signal or a N-4th stage gate pulse signal; a second switch component including a second control terminal, a third path end and a fourth path end, wherein the second control terminal is coupled to the Nth stage precharge a voltage node, the third path end is coupled to the first clock signal, the fourth path end is coupled to the output end, and the third switch component includes a third control end, a fifth path end, and a sixth path end, The third control end is coupled to the second path end, the fifth path end is connected to the first clock signal, the sixth path end is outputting an Nth stage start pulse signal, and the fourth switch component is configured to include a fourth control a fourth, a seventh path end and an eighth path end, wherein the fourth control end and the seventh path end are coupled to the first clock signal; and the fifth switch component includes
  • the gate driving circuit further includes a capacitor, and two ends of the capacitor are respectively coupled to the third control terminal and the output terminal.
  • the first switch component to the thirteenth switch component are all N-type transistors.
  • the first to third switch components are all P-type transistors.
  • the first clock signal and the second clock signal are mutually inverted.
  • a duty ratio of the first clock signal and the second clock signal (duty Ratio) is 50%.
  • the pulse width of the first clock signal when the gate driving circuit is used to drive a two-dimensional (2D) image is twice that of the gate driving circuit for driving three-dimensional (3D)
  • the pulse width of the first clock signal at the time of image is twice that of the gate driving circuit for driving three-dimensional (3D)
  • the pulse width of the first clock signal when the gate driving circuit is used to drive the two-dimensional image is twice that of the gate driving circuit for driving the three-dimensional image.
  • the pulse width of a clock signal is twice that of the gate driving circuit for driving the three-dimensional image.
  • the first clock signal connected to the Nth-level gate driving unit is connected to the (N+1)th gate
  • the phase difference of the first clock signal of the pole drive unit is one quarter of a pulse width of the first clock signal.
  • the first clock signal connected to the Nth-level gate driving unit is connected to the N+1th-level gate
  • the first clock signal of the driving unit has no phase difference
  • the first clock signal has no phase difference
  • a phase difference between the first clock signal connected to the Nth stage gate driving unit and the first clock signal connected to the N+2th stage driving unit is The first clock signal is one-half of a pulse width.
  • the present invention further provides a display comprising a liquid crystal display panel and the above-described gate driving circuit.
  • the liquid crystal display panel is for displaying an image
  • the gate driving circuit is integrated in the liquid crystal display panel.
  • the invention provides a gate driving circuit and a display thereof, through a gate
  • the timing of the waveform is fine-tuned to pre-charge the pixels, which can extend the charging time of each pixel and solve the problem of insufficient charging time of the prior art pixels.
  • each of the two gate driving units shares a set of the starting pulse signal, the gate pulse signal, and the clock pulse signal. Therefore, when displaying the three-dimensional image, every two gate driving units can be At the same time, the gate pulse signal is output to the two gate lines to simultaneously open two rows of pixels. Therefore, the gate driving circuit of the present invention can drive large-size ultra-high resolution for displaying two-dimensional/three-dimensional (2D/3D) images (Ultra Definition, UD) panel.
  • 2D/3D two-dimensional/three-dimensional
  • 1 is a timing diagram of gate pulse signals of the Nth stage to the N+4th stage of the conventional gate driving circuit
  • 2 is a timing diagram of the gate pulse signals of the Nth stage to the N+4th stage of the gate driving circuit of the present invention under two-dimensional (2D) driving;
  • 3 is a timing diagram of gate signal signals of the Nth stage to the N+4th stage of the gate driving circuit of the present invention in three-dimensional (3D) driving;
  • FIG. 4 is a circuit diagram of a gate driving circuit of the present invention.
  • FIG. 5 is a waveform diagram of respective signals for the Nth stage to the N+4th stage driving unit of the gate driving circuit of FIG. 4 under two-dimensional (2D) driving;
  • FIG. 6 is a waveform diagram of respective signals for the Nth stage to the N+4th stage driving unit of the gate driving circuit of FIG. 4 under three-dimensional (3D) driving.
  • Figure 1 It is a timing chart of the gate pulse signals of the Nth stage to the N+4th stage of the conventional gate driving circuit.
  • the first time difference ( ⁇ t) used to turn on the gate drive signal of the pixel-corresponding transistor is about 7.4 ms.
  • FIG. 2 is a timing diagram of the gate signal of the Nth stage to the N+4th stage of the gate driving circuit of the present invention under two-dimensional (2D) driving.
  • the pulse width of the Nth gate pulse signal G(N) to the N+4th gate pulse signal G(N+4) is 4 times the first time difference (4 ⁇ t) to extend the gate turn-on time. Since the pulse width of the Nth gate pulse signal G(N) is 4 times the first time difference ( ⁇ t), the pulse width of the first three quarters of the gate pulse signal G(N) is also 3 times first.
  • the time difference ( ⁇ t) is used as the precharge voltage.
  • Figure 3 A timing diagram of the Nth to Nth-4th gate pulse signals of the gate driving circuit of the present invention under three-dimensional (3D) driving.
  • the frequency of the gate drive circuit output gate pulse signal needs to be doubled to 120HZ.
  • the Nth gate pulse signal G(N) and the N+1th gate pulse signal G(N+1) are simultaneously turned on, and the N+2th gate pulse signal G(N+2) and the N+3 are simultaneously turned on.
  • the stage gate pulse signal G(N+3) is turned on at the same time.
  • the N+4th gate pulse signal G(N+4) and the N+5th gate pulse signal G(N+5) are simultaneously turned on.
  • the pulse width of the N-th gate pulse signal G(N) is twice the first time difference ( ⁇ t). That is to say, there is still half of the pulse width of the gate pulse signal G(N), that is, 1 time of the first time difference ( ⁇ t), which is used as the precharge voltage.
  • FIG. 4 is a circuit diagram of a gate driving unit of a gate driving circuit of the present invention.
  • the gate driving circuit of this embodiment includes a plurality of gate driving units, and the plurality of the gate driving units are coupled in series.
  • the Nth stage gate driving unit SR(N) is used to output the Nth stage gate pulse signal G(N) at the output terminal OUT.
  • the Nth stage gate driving unit SR(N) is configured to be based on the N-4th stage start pulse signal ST(N-4) or the N-4th stage gate pulse signal G(N-4) and the first clock
  • the signal CK1 outputs a gate pulse signal G(N) at the output terminal OUT, where N is a positive integer.
  • the Nth to Nth-7th gate drive units SR(N) ⁇ SR(N+7) are respectively connected to the clock signals CK1-CK8, and are used as the first clock signal, and at the same time
  • the N-stage to N+7-stage gate drive units SR(N) to SR(N+7) are also connected to the second clock signal CKV2 to invert the second clock signal CKV2 to the first clock signal CKV1.
  • the first clock signal CKV1 of the Nth stage gate driving unit SR(N) is the clock signal CK1
  • the second clock signal CKV2 is the clock signal CK5
  • the N+1th stage gate driving unit SR(N+1) The first clock signal CKV1 is the clock signal CK2, the second clock signal CKV2 is the clock signal CK6; the first clock signal CKV1 of the N+2th stage gate driving unit SR(N+2) is the clock signal CK3, the second The clock signal CKV2 is the clock signal CK7, and so on.
  • the clock signal of the gate driving circuit is usually driven by four clock signals having different periods, or six clock signals having different periods, or eight clock signals having different periods.
  • the gate driving circuit is exemplified by eight clock signals CK1-CK8 having different periods.
  • the number and pulse width required for the clock signal can be adjusted according to actual needs.
  • Duty cycle of each clock signal CK1-CK8 (duty Ratio) are both 50%.
  • the waveform of the Nth stage start pulse signal ST(N) is the same as the waveform of the Nth stage gate pulse signal G(N), and the timing difference of the adjacent two clock signals is the first time difference ( ⁇ t).
  • the N-4th stage start pulse signal ST(N-4) is used to pull up the node voltage of the Nth stage precharge voltage node signal pulse Q(N).
  • the gate drive unit of different stages is transmitted in such a manner that the gate drive signal generated by the Nth stage gate drive unit SR(N) transmits and drives the N+4th stage gate drive unit, for example, the first stage gate
  • the gate drive signal G(1) generated by the pole drive unit drives the fifth stage gate drive unit
  • the gate drive signal G(5) is generated by the fifth stage gate drive unit. Drive the ninth stage gate drive unit, and so on.
  • the Nth stage gate driving unit includes a first switch component M1, a second switch component M2, a third switch component M3, a fourth switch component M4, a fifth switch component M5, a sixth switch component M6, and a seventh switch component M7,
  • the first switch component M1 includes a first control end, a first path end and a second path end, and the first path end and the first control end are coupled to the N-4th stage start pulse signal ST(N-4) Or the N-4th gate pulse signal G(N-4).
  • the second switch component M2 includes a second control end, a third path end, and a fourth path end, the second control end is coupled to the Nth stage precharge voltage node Q(n), and the third path end is coupled to the first
  • the clock signal CK1 is connected to the output terminal OUT.
  • the third switch component M3 includes a third control end, a fifth path end and a sixth path end, the third control end is coupled to the second path end, and the fifth path end is coupled to the first clock signal CKV1,
  • the sixth path terminal outputs the Nth stage start pulse signal ST(N).
  • the fifth switch component M5 includes a fifth control terminal, a ninth path end, and a tenth path end, the fifth control terminal receives an Nth stage precharge voltage node Q(N), and the ninth path end is connected to the first The eight-terminal end is connected to the first voltage source Vss.
  • the sixth switch component M6 includes a sixth control end, an eleventh path end, and a twelfth path end, the sixth control end is coupled to the eighth path end, and the eleventh path end is connected to the first clock signal CKV1 The twelfth path end is connected to the first voltage source Vss.
  • the seventh switch component M7 includes a seventh control end, a thirteenth path end, and a fourteenth path end, the seventh control end is coupled to the fifth control end, and the thirteenth path end is connected to the twelfth The connection end, the fourteenth path end is connected to the first voltage source Vss.
  • the eighth switch component M8 includes an eighth control end, a fifteenth path end, and a sixteenth path end, wherein the eighth control end is coupled to the twelfth path end and the thirteenth path end, where the The fifteen-channel end is connected to the third control end, and the sixteenth path end is connected to the output end OUT.
  • the ninth switch component M9 includes a ninth control end, a seventeenth path end and an eighteenth path end, the ninth control end is connected to the eighth control end, and the seventeenth connection end is connected to the output end OUT, The eighteenth path end is connected to the first voltage source Vss.
  • the tenth switch component M10 includes a tenth control end, a nineteenth path end, and a twentieth path end, the tenth control end is coupled to the second clock signal CKV2, and the nineteenth path end is coupled to the output end, The twentieth path end receives the N-4th stage start pulse signal or the Nth stage-4th gate pulse signal.
  • the eleventh switch component M11 includes an eleventh control end, a twenty-first pass end, and a twenty-second pass end, wherein the eleventh control end is coupled to the second clock signal CKV2, and the twenty-first pass end is connected The output terminal OUT is connected to the first voltage source Vss.
  • the twelfth switch component M12 includes a twelfth control end, a twenty-third pass end, and a twenty-fourth pass end, and the twelfth control end is connected to the N+4th start pulse signal or the N+4th stage a gate pulse signal, the twenty-third pass end is connected to the third control end, and the twenty-four pass end is connected to the first voltage source Vss.
  • the thirteenth switch component M13 includes a thirteenth control terminal, a twenty-fifth path end, and a twenty-sixth path end, and the thirteenth control terminal M13 receives the N+4th start pulse signal ST(N+4) or The Nth-th stage gate pulse signal G(N+4), the twenty-fifth path end is connected to the output terminal OUT, and the twenty-sixth path end is connected to the first voltage source Vss. Both ends of the capacitor C1 are respectively coupled to the third control terminal and the output terminal OUT.
  • the first to thirteenth switch components M1 to M13 are N-type transistors.
  • the first to thirteenth switch components M1 to M13 can also be implemented by other switch components, such as P-type transistors.
  • FIG. 4 is a waveform diagram of respective signals for the Nth stage to the N+4th stage driving unit under the two-dimensional (2D) driving of the gate driving circuit of FIG. 4.
  • the first clock signal CKV1 connected to the Nth stage gate driving unit SR(N) is connected to the N+1th stage driving unit SR(N+1).
  • the phase difference of the first clock signal CKV1 is one quarter of the pulse width of the first clock signal CKV1, that is, four times the first time difference ( ⁇ t).
  • the pulse width of the Nth gate pulse signal G(N) is 4 times the first time difference ( ⁇ t)
  • the pulse width of the first three quarters of the gate pulse signal G(N) is also 3 times first.
  • the time difference ( ⁇ t) is used as the precharge voltage.
  • FIG. 4 is a waveform diagram of respective signals for the Nth stage to the N+4th stage driving unit in the three-dimensional (3D) driving of the gate driving circuit of FIG. 4.
  • the clock signal CK1 connected to the Nth stage gate driving unit SR(N) ie, the clock signal CK1 of FIG. 6
  • the first clock signal CKV1 of SR(N+1) ie, the clock signal CK2 of FIG. 6
  • has no phase difference and is connected to the first clock signal CKV1 of the N+2th stage gate driving unit SR(N+2) (ie, The clock signal CK3) of FIG.
  • the phase difference of the signal CKV1 is one-half of the pulse width of the first clock signal CKV1, that is, the first time difference of 2 times. ( ⁇ t).
  • the pulse width of the N-th gate pulse signal G(N) is twice the first time difference ( ⁇ t). Therefore, there is still half of the gate pulse signal G(N) pulse width, that is, 1 time first time difference ( ⁇ t), which is used as the precharge voltage.
  • every two gate drive units such as gate drive units SR(N) and SR(N+1), SR(N+2) and SR(N+3), can simultaneously output gate pulse signals to two A gate line to open two lines of pixels at the same time. Therefore, in this embodiment, the display of the three-dimensional image can also be controlled without changing the output gate pulse signal.
  • the gate drive circuit of the present invention having the gate drive unit as shown in FIG. 4 can be used for a display.
  • the display has a liquid crystal display panel for displaying an image.
  • the gate driving circuit may be integrated on the liquid crystal display panel.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种为栅极阵列的栅极驱动电路及其显示器，包括第一开关组件（M1）至第十三开关组件（M13）以及第一电容（C1）。该栅极驱动电路可形成二维的栅极驱动或三维的栅极驱动，具有延长栅极开启时间之效果。三维的栅极驱动有两个一组结构的脉冲信号，包括第N级起始脉冲信号（ST(N)）、第N级栅极脉冲信号（G(N)），以及第一时钟信号（CK1）至第八时钟信号（CK8），提供画素足够充电时间，达到液晶显示面板较佳的显示效果。

Description

一种栅极驱动电路及其显示器 技术领域
本发明涉及一种显示器，尤指一种使用栅极驱动(Gate driver on array，GOA)电路的显示器。
 背景技术
在液晶面板低成本高品质是产业技术的必要条件。栅极阵列(gate on array, GOA) 是一种常用的降低成本的方法，它是将晶体管栅极的功能通过薄膜晶体管-液晶显示器(TFT—LCD)制程做在玻璃基板上，省掉栅极侧驱动集成电路(IC)，在降低成本的同时，还可以做到无边框，提升产品的市场竞争力。对于目前市面上的超高解析(Ultra Definition, UD)面板，二维(2D)面板的驱动为60HZ，因超高解析(Ultra Definition, UD)面板分辨率较高，为保证较高开口率，面板内各金属走线及画素开关的薄膜晶体管(TFT)，要尽可能压缩到较小范围内，这样势必会导致先前技术中画素充电不足，会直接影响面板的显示效果的问题。
先前技术超高解析(Ultra Definition, UD)面板的产品，具有超高分辨率搭配3D功能，因此大尺寸超高解析(Ultra Definition, UD)产品一般都会搭配三维(3D)功能。三维(3D)的驱动，为保证左右眼各收到60HZ的信号，驱动频率需加倍变为120HZ，由于受带宽的限制，集成电路(gate IC)无法实现频率为120*2160的驱动。
 技术问题
本发明的一个目的在于提供一种栅极驱动电路及其显示器，用来改善现有技术液晶显示面板中画素充电不足的问题。
 技术解决方案
为解决先前技术的上述问题,本发明实施例提供一种栅极驱动电路，包含多个栅极驱动单元，多个所述栅极驱动单元以串联的方式耦接，第N级栅极驱动单元用来在输出端输出第N级栅极脉冲信号。所述第N级栅极驱动单元包括：第一开关组件，包括第一控制端、第一通路端和第二通路端，所述第一通路端和所述第一控制端连结第N-4级起始脉冲信号或第N-4级栅极脉冲信号；第二开关组件，包括第二控制端、第三通路端和第四通路端，所述第二控制端连结于第N级预充电压节点，所述第三通路端连结第一时钟信号，所述第四通路端连结所述输出端；第三开关组件，包括第三控制端、第五通路端和第六通路端，所述第三控制端连结所述第二通路端，所述第五通路端连结所述第一时钟信号，所述第六通路端输出第N级起始脉冲信号；第四开关组件，包括第四控制端、第七通路端和第八通路端，所述第四控制端和所述第七通路端连结所述第一时钟信号；第五开关组件，包括第五控制端、第九通路端和第十通路端，所述第五控制端接收所述第N级预充电压节点，所述第九通路端连接所述第八连接端，所述第十通路端连接第一电压源；第六开关组件，包括第六控制端、第十一通路端和第十二通路端，所述第六控制端连结所述第八通路端，所述第十一通路端连接所述第一时钟信号，所述第十二通路端连接所述第一电压源；第七开关组件，包括第七控制端、第十三通路端和第十四通路端，所述第七控制端连结所述第五控制端，所述第十三通路端连接所述第十二连接端，所述第十四通路端连接所述第一电压源；第八开关组件，包括第八控制端、第十五通路端和第十六通路端，所述第八控制端连结所述第十二通路端以及所述第十三通路端，所述第十五通路端连结所述第三控制端，所述第十六通路端连结所述输出端；第九开关组件，包括第九控制端、第十七通路端和第十八通路端，所述第九控制端是连结所述第八控制端，所述第十七连接端连接所述输出端，所述第十八通路端连接所述第一电压源；第十开关组件，包括第十控制端、第十九通路端和第二十通路端，所述第十控制端连结第二时钟信号，所述第十九通路端连结所述输出端，所述第二十通路端接收所述第N-4级起始脉冲信号或所述第N-4级栅极脉冲信号；第十一开关组件，包括第十一控制端、第二十一通路端和第二十二通路端，所述第十一控制端连结所述第二时钟信号，所述第二十一通路端连接所述输出端，所述第二十二通路端连接所述第一电压源；第十二开关组件，包括第十二控制端、第二十三通路端和第二十四通路端，所述第二十三通路端连结所述第三控制端，所述第十二控制端连接第N+4级起始脉冲信号或第N+4级栅极脉冲信号，所述第二十四通路端连接所述第一电压源；以及第十三开关组件，包括第十三控制端、第二十五通路端和第二十六通路端，所述第十三控制端接收所述第N+4级起始脉冲信号或所述第N+4级栅极脉冲信号，所述第二十五通路端连结所述输出端，所述第二十六通路端连接所述第一电压源。其中，N为正整数。
依据本发明的实施例，所述栅极驱动电路另包括电容，所述电容的两端分别连结所述第三控制端和所述输出端。
依据本发明的实施例，所述第一开关组件到所述第十三开关组件均为N型晶体管。
依据本发明的实施例，所述第一开关组件到所述第十三开关组件均为P型晶体管。
依据本发明的实施例，所述第一时钟信号和所述第二时钟脉冲信号互为反相。
依据本发明的实施例，所述第一时钟信号和所述第二时钟脉冲信号的占空比(duty ratio)为50%。
依据本发明的实施例，所述栅极驱动电路用以驱动二维(2D)影像时的所述第一时钟信号的脉宽是两倍于所述栅极驱动电路用以驱动三维(3D)影像时的所述第一时钟信号的脉宽。
依据本发明的实施例，所述栅极驱动电路用以驱动二维影像时的所述第一时钟信号的脉宽是两倍于所述栅极驱动电路用以驱动三维影像时的所述第一时钟信号的脉宽。
依据本发明的实施例，所述栅极驱动电路用以驱动二维影像时，连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+1级栅极驱动单元的所述第一时钟信号的相位差为所述第一时钟信号脉宽的四分之一。
依据本发明的实施例，所述栅极驱动电路用以驱动三维影像时，连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+1级栅极驱动单元的所述第一时钟信号没有相位差，连接于所述第N+2级栅极驱动单元的所述第一时钟信号与连接于所述第N+3级栅极驱动单元的所述第一时钟信号没有相位差。
依据本发明的实施例，连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+2级栅极驱动单元的所述第一时钟信号的相位差为所述第一时钟信号脉宽的二分之一。
依据本发明的实施例，本发明另提供一种显示器，包括液晶显示面板和上述的所述栅极驱动电路。所述液晶显示面板用于显示图像，且所述栅极驱动电路集成在所述液晶显示面板中。
 有益效果
本发明提供一种栅极驱动电路及其显示器，通过对栅极(gate) 波形的时序进行微调，以对画素进行预充电，可以延长每个画素的充电时间，解决先前技术画素的充电时间不足的问题。此外，本发明栅极驱动电路中，每两个栅极驱动单元共享一组起始脉冲信号、栅极脉冲信号以及时钟脉冲信号，因此，在显示三维影像时，每两个栅极驱动单元可同时输出栅极脉冲信号至两条栅极线，以同时打开两行的画素。所以可以本发明栅极驱动电路可驱动用于显示二维/三维(2D/3D)影像的大尺寸超高解析(Ultra Definition, UD)面板。
附图说明
图1 为传统栅极驱动电路的第N级到第N+4级栅极脉冲信号的时序图；
图2为本发明栅极驱动电路在二维(2D)驱动下的第N级到第N+4级栅极脉冲信号的时序图；
图3 为本发明栅极驱动电路在三维(3D)驱动下的第N级到第N+4级栅极脉冲信号的时序图；
图4 为本发明栅极驱动电路的电路图；
图5 为图4栅极驱动电路在二维(2D)驱动下，用于第N级到第N+4级驱动单元的各个信号的波形图；
图6 为图4栅极驱动电路在三维(3D)驱动下，用于第N级到第N+4级驱动单元的各个信号的波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
请参阅图1，图1 为传统栅极驱动电路的第N级到第N+4级栅极脉冲信号的时序图。对于驱动频率为60HZ的传统大尺寸超高解析(Ultra Definition, UD)面板而言，用来开启画素对应晶体管的栅极驱动信号的第一时间差(Δt)约为7.4ms。
请参阅图1和图2，图2为本发明栅极驱动电路在二维(2D)驱动下的第N级到第N+4级栅极脉冲信号的时序图。本实施例在显示二维影像时，第N级栅极脉冲信号G(N)到第N+4级栅极脉冲信号G(N+4)的脉宽是 4倍的第一时间差(4Δt)，用来延长栅极(gate)开启时间。因为第N级栅极脉冲信号G(N)的脉宽为4倍第一时间差(Δt)，因此前四分之三的栅极脉冲信号G(N)的脉宽，亦即3倍第一时间差(Δt)，是做为预充电压。
请参阅图1-图3，图3 为本发明栅极驱动电路在三维(3D)驱动下的第N级到第N+4级栅极脉冲信号的时序图。相较图2，若显示面板切换为三维(3D)模式，为保证左右眼各收到60HZ的信号，栅极驱动电路输出栅极脉冲信号的频率需加倍为120HZ。第N级栅极脉冲信号G(N)和第N+1级栅极脉冲信号G(N+1)同时打开，第N+2级栅极脉冲信号G(N+2)和第N+3级栅极脉冲信号G(N+3)同时打开。第N+4级栅极脉冲信号G(N+4)和第N+5级栅极脉冲信号G(N+5)同时打开。在显示三维影像时，第N级栅极脉冲信号G(N)的脉宽为2倍第一时间差(Δt)。也就是说，仍有一半的栅极脉冲信号G(N)的脉宽，亦即1倍第一时间差(Δt)，是做为预充电压。
请参阅图4，图4为本发明栅极驱动电路的栅极驱动单元的电路图。本实施例的栅极驱动电路包括多个栅极驱动单元，多个所述栅极驱动单元以串联的方式耦接。第N级栅极驱动单元SR(N)用来在输出端OUT输出第N级栅极脉冲信号G(N)。第N级栅极驱动单元SR(N)用来依据第N-4级起始脉冲信号ST(N-4)或是第N-4级栅极脉冲信号G(N-4)和第一时钟信号CK1在输出端OUT输出栅极脉冲信号G(N)，其中N为正整数。在本实施例中，第N级到第N+7级栅极驱动单元SR(N)~SR(N+7)分别连接时钟信号CK1-CK8，并将其做为第一时钟信号，同时第N级到第N+7级栅极驱动单元SR(N)~SR(N+7)还连接第二时钟信号CKV2，将第二时钟信号CKV2反相于第一时钟信号CKV1。举例来说，第N级栅极驱动单元SR(N)的第一时钟信号CKV1就是时钟信号CK1，第二时钟信号CKV2就是时钟信号CK5；第N+1级栅极驱动单元SR(N+1)的第一时钟信号CKV1就是时钟信号CK2，第二时钟信号CKV2就是时钟信号CK6；第N+2级栅极驱动单元SR(N+2)的第一时钟信号CKV1就是时钟信号CK3，第二时钟信号CKV2就是时钟信号CK7，以此类推。
由于大尺寸的面板线路中，电阻结合电容的延迟(RC Delay)比较严重，因此栅极驱动电路的时钟信号通常采用四个具有不同周期的时钟信号、或者六个具有不同周期的时钟信号、或者八个具有不同周期的时钟信号来驱动。在本实施例中，栅极驱动电路是以八个具有不同周期的时钟信号CK1-CK8为例。在实际设计中，时钟信号所需的数量和脉宽可根据实际不同需求进行调整。每一时钟信号CK1-CK8的占空比(duty ratio)都为50%。第N级起始脉冲信号ST(N)波形与所述第N级栅极脉冲信号G(N)波形相同，相邻两个时钟信号的时序差为第一时间差(Δt)。第N-4级起始脉冲信号ST(N-4)用于拉高第N级预充电压节点信号脉冲Q(N)的节点电压。不同级的栅极驱动单元传递方式为，第N级栅极驱动单元SR(N)产生的栅极驱动信号会传递并驱动第N+4级栅极驱动单元，举例来说，第一级栅极驱动单元产生的栅极驱动信号G(1)会驱动第五级栅极驱动单元，再由第五级栅极驱动单元产生栅极驱动信号G(5) 驱动第九级栅极驱动单元，以此类推。
第N级栅极驱动单元包括第一开关组件M1、第二开关组件M2、第三开关组件M3、第四开关组件M4、第五开关组件M5、第六开关组件M6、第七开关组件M7、第八开关组件M8、第九开关组件M9、第十开关组件M10、第十一开关组件M11、第十二开关组件M12、第十三开关组件M13以及电容C1。第一开关组件M1包括第一控制端、第一通路端和第二通路端，所述第一通路端和所述第一控制端连结第N-4级起始脉冲信号ST(N-4)或第N-4级栅极脉冲信号G(N-4)。第二开关组件M2包括第二控制端、第三通路端和第四通路端，所述第二控制端连结于第N级预充电压节点Q(n)，所述第三通路端连结第一时钟信号CK1，所述第四通路端连结输出端OUT。第三开关组件M3包括第三控制端、第五通路端和第六通路端，所述第三控制端连结所述第二通路端，所述第五通路端连结第一时钟信号CKV1，所述第六通路端输出第N级起始脉冲信号ST(N)。第五开关组件M5包括第五控制端、第九通路端和第十通路端，所述第五控制端接收第N级预充电压节点Q(N)，所述第九通路端连接所述第八连接端，所述第十通路端连接第一电压源Vss。第六开关组件M6包括第六控制端、第十一通路端和第十二通路端，所述第六控制端连结所述第八通路端，所述第十一通路端连接第一时钟信号CKV1，所述第十二通路端连接第一电压源Vss。第七开关组件M7包括第七控制端、第十三通路端和第十四通路端，所述第七控制端连结所述第五控制端，所述第十三通路端连接所述第十二连接端，所述第十四通路端连接第一电压源Vss。第八开关组件M8，包括第八控制端、第十五通路端和第十六通路端，所述第八控制端连结所述第十二通路端以及所述第十三通路端，所述第十五通路端连结所述第三控制端，所述第十六通路端连结输出端OUT。第九开关组件M9包括第九控制端、第十七通路端和第十八通路端，所述第九控制端是连结所述第八控制端，所述第十七连接端连接输出端OUT，所述第十八通路端连接第一电压源Vss。第十开关组件M10包括第十控制端、第十九通路端和第二十通路端，所述第十控制端连结第二时钟信号CKV2，所述第十九通路端连结所述输出端，所述第二十通路端接收所述第N-4级起始脉冲信号或所述第N-4级栅极脉冲信号。第十一开关组件M11包括第十一控制端、第二十一通路端和第二十二通路端，所述第十一控制端连结第二时钟信号CKV2，所述第二十一通路端连接输出端OUT，所述第二十二通路端连接第一电压源Vss。第十二开关组件M12包括第十二控制端、第二十三通路端和第二十四通路端，所述第十二控制端连接第N+4级起始脉冲信号或第N+4级栅极脉冲信号，所述第二十三通路端连结所述第三控制端，所述第二十四通路端连接第一电压源Vss。第十三开关组件M13包括第十三控制端、第二十五通路端和第二十六通路端，第十三控制端M13接收第N+4级起始脉冲信号ST(N+4)或第N+4级栅极脉冲信号G(N+4)，所述第二十五通路端连结输出端OUT，所述第二十六通路端连接第一电压源Vss。电容C1的两端分别连结所述第三控制端和输出端OUT。
在本实施例中，第一开关组件至第十三开关组件M1～M13为N型晶体管。当然，第一开关组件至第十三开关组件M1～M13也可以采用其他的开关组件而实现，例如P型晶体管。
以下以第一开关组件M1至第十三开关组件M13为N型晶体管为例来具体地介绍本发明的具体实施方式及其工作原理。
请参阅图5，图5 为图4栅极驱动电路在二维(2D)驱动下，用于第N级到第N+4级驱动单元的各个信号的波形图。栅极驱动电路用以驱动二维影像时，连接于第N级栅极驱动单元SR(N)的第一时钟信号CKV1与连接于第N+1级栅极驱动单元SR(N+1)的第一时钟信号CKV1的相位差为第一时钟信号CKV1脉宽的四分之一，也就是4倍的第一时间差(Δt)。因为第N级栅极脉冲信号G(N)的脉宽为4倍第一时间差(Δt)，因此前四分之三的栅极脉冲信号G(N)的脉宽，亦即3倍第一时间差(Δt)，是做为预充电压。
请参阅图6，图6 为图4栅极驱动电路在三维(3D)驱动下，用于第N级到第N+4级驱动单元的各个信号的波形图。当栅极驱动电路用以驱动三维影像时，连接于第N级栅极驱动单元SR(N)的时钟信号CK1(即图6的时钟信号CK1)与连接于第N+1级栅极驱动单元SR(N+1)的第一时钟信号CKV1(即图6的时钟信号CK2)没有相位差，连接于第N+2级栅极驱动单元SR(N+2)的第一时钟信号CKV1(即图6的时钟信号CK3)与连接于第N+3级栅极驱动单元SR(N+3)的所述第一时钟信号CKV1(即图6的时钟信号CK4)没有相位差。连接于第N级栅极驱动单元SR(N)的第一时钟信号CKV1(即图6的时钟信号CK1)与连接于第N+2级栅极驱动单元SR(N+2)的第一时钟信号CKV1(即图6的时钟信号CK3)的相位差为第一时钟信号CKV1脉宽的二分之一，也就是2倍的第一时间差 (Δt)。在显示三维影像时，第N级栅极脉冲信号G(N)的脉宽为2倍第一时间差(Δt)。因此仍有一半的栅极脉冲信号G(N)的脉宽，亦即1倍第一时间差(Δt)，是做为预充电压。此外，每两个栅极驱动单元，例如栅极驱动单元SR(N)和SR(N+1)、SR(N+2)和SR(N+3)，可同时输出栅极脉冲信号至两条栅极线，以同时打开两行的画素。因此本实施例也可以在不改变输出栅极脉冲信号的前提下，控制三维影像的显示。
本发明具有如图4所示的栅极驱动单元的栅极驱动电路可用于一显示器。该显示器具有液晶显示面板，用于显示图像。所述栅极驱动电路可集成在所述液晶显示面板上。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种栅极驱动电路，包含多个栅极驱动单元，多个所述栅极驱动单元以串联的方式耦接，第N级栅极驱动单元用来在输出端输出第N级栅极脉冲信号，所述第N级栅极驱动单元包括：
    第一开关组件，包括第一控制端、第一通路端和第二通路端，所述第一通路端和所述第一控制端连结第N-4级起始脉冲信号或第N-4级栅极脉冲信号；
    第二开关组件，包括第二控制端、第三通路端和第四通路端，所述第二控制端连结于第N级预充电压节点，所述第三通路端连结第一时钟信号，所述第四通路端连结所述输出端；
    第三开关组件，包括第三控制端、第五通路端和第六通路端，所述第三控制端连结所述第二通路端，所述第五通路端连结所述第一时钟信号，所述第六通路端输出第N级起始脉冲信号；
    第四开关组件，包括第四控制端、第七通路端和第八通路端，所述第四控制端和所述第七通路端连结所述第一时钟信号；
    第五开关组件，包括第五控制端、第九通路端和第十通路端，所述第五控制端接收所述第N级预充电压节点，所述第九通路端连接所述第八连接端，所述第十通路端连接第一电压源；
    第六开关组件，包括第六控制端、第十一通路端和第十二通路端，所述第六控制端连结所述第八通路端，所述第十一通路端连接所述第一时钟信号，所述第十二通路端连接所述第一电压源；
    第七开关组件，包括第七控制端、第十三通路端和第十四通路端，所述第七控制端连结所述第五控制端，所述第十三通路端连接所述第十二连接端，所述第十四通路端连接所述第一电压源；
    第八开关组件，包括第八控制端、第十五通路端和第十六通路端，所述第八控制端连结所述第十二通路端以及所述第十三通路端，所述第十五通路端连结所述第三控制端，所述第十六通路端连结所述输出端；
    第九开关组件，包括第九控制端、第十七通路端和第十八通路端，所述第九控制端是连结所述第八控制端，所述第十七连接端连接所述输出端，所述第十八通路端连接所述第一电压源；
    第十开关组件，包括第十控制端、第十九通路端和第二十通路端，所述第十控制端连结第二时钟信号，所述第十九通路端连结所述输出端，所述第二十通路端接收所述第N-4级起始脉冲信号或所述第N-4级栅极脉冲信号；
    第十一开关组件，包括第十一控制端、第二十一通路端和第二十二通路端，所述第十一控制端连结所述第二时钟信号，所述第二十一通路端连接所述输出端，所述第二十二通路端连接所述第一电压源；
    第十二开关组件，包括第十二控制端、第二十三通路端和第二十四通路端，所述第十二控制端连接第N+4级起始脉冲信号或第N+4级栅极脉冲信号，所述第二十三通路端连结所述第三控制端，所述第二十四通路端连接所述第一电压源；以及
    第十三开关组件，包括第十三控制端、第二十五通路端和第二十六通路端，所述第十三控制端接收所述第N+4级起始脉冲信号或所述第N+4级栅极脉冲信号，所述第二十五通路端连结所述输出端，所述第二十六通路端连接所述第一电压源；
    其中，N为正整数。
  2. 根据权利要求1所述的栅极驱动电路，其另包括电容，所述电容的两端分别连结所述第三控制端和所述输出端。
  3. 根据权利要求1所述的栅极驱动电路，其中所述第一开关组件到所述第十三开关组件均为N型晶体管。
  4. 根据权利要求1所述的栅极驱动电路，其中所述第一开关组件到所述第十三开关组件均为P型晶体管。
  5. 根据权利要求1所述的栅极驱动电路，其中所述第一时钟信号和所述第二时钟脉冲信号互为反相。
  6. 根据权利要求1所述的栅极驱动电路，其中所述第一时钟信号和所述第二时钟脉冲信号的占空比(duty ratio)为50%。
  7. 根据权利要求1所述的栅极驱动电路，其中所述栅极驱动电路用以驱动二维(2D)影像时的所述第一时钟信号的脉宽是两倍于所述栅极驱动电路用以驱动三维(3D)影像时的所述第一时钟信号的脉宽。
  8. 根据权利要求1所述的栅极驱动电路，其中所述栅极驱动电路用以驱动二维影像时的所述第一时钟信号的脉宽是两倍于所述栅极驱动电路用以驱动三维影像时的所述第一时钟信号的脉宽。
  9. 根据权利要求8所述的栅极驱动电路，其中所述栅极驱动电路用以驱动二维影像时，连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+1级栅极驱动单元的所述第一时钟信号的相位差为所述第一时钟信号脉宽的四分之一。
  10. 根据权利要求8所述的栅极驱动电路，其中所述栅极驱动电路用以驱动三维影像时，连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+1级栅极驱动单元的所述第一时钟信号没有相位差，连接于所述第N+2级栅极驱动单元的所述第一时钟信号与连接于所述第N+3级栅极驱动单元的所述第一时钟信号没有相位差。
  11. 根据权利要求10所述的栅极驱动电路，其中连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+2级栅极驱动单元的所述第一时钟信号的相位差为所述第一时钟信号脉宽的二分之一。
  12. 一种显示器，包含：
    液晶显示面板，用于显示图像；以及
    栅极驱动电路，集成在所述液晶显示面板上；
    其中所述栅极驱动电路包含多个栅极驱动单元，多个所述栅极驱动单元以串联的方式耦接，第N级栅极驱动单元用来在输出端输出第N级栅极脉冲信号，所述第N级栅极驱动单元包括：
    第一开关组件，包括第一控制端、第一通路端和第二通路端，所述第一通路端和所述第一控制端连结第N-4级起始脉冲信号或第N-4级栅极脉冲信号；
    第二开关组件，包括第二控制端、第三通路端和第四通路端，所述第二控制端连结于第N级预充电压节点，所述第三通路端连结第一时钟信号，所述第四通路端连结所述输出端；
    第三开关组件，包括第三控制端、第五通路端和第六通路端，所述第三控制端连结所述第二通路端，所述第五通路端连结所述第一时钟信号，所述第六通路端输出第N级起始脉冲信号；
    第四开关组件，包括第四控制端、第七通路端和第八通路端，所述第四控制端和所述第七通路端连结所述第一时钟信号；
    第五开关组件，包括第五控制端、第九通路端和第十通路端，所述第五控制端接收所述第N级预充电压节点，所述第九通路端连接所述第八连接端，所述第十通路端连接第一电压源；
    第六开关组件，包括第六控制端、第十一通路端和第十二通路端，所述第六控制端连结所述第八通路端，所述第十一通路端连接所述第一时钟信号，所述第十二通路端连接所述第一电压源；
    第七开关组件，包括第七控制端、第十三通路端和第十四通路端，所述第七控制端连结所述第五控制端，所述第十三通路端连接所述第十二连接端，所述第十四通路端连接所述第一电压源；
    第八开关组件，包括第八控制端、第十五通路端和第十六通路端，所述第八控制端连结所述第十二通路端以及所述第十三通路端，所述第十五通路端连结所述第三控制端，所述第十六通路端连结所述输出端；
    第九开关组件，包括第九控制端、第十七通路端和第十八通路端，所述第九控制端是连结所述第八控制端，所述第十七连接端连接所述输出端，所述第十八通路端连接所述第一电压源；
    第十开关组件，包括第十控制端、第十九通路端和第二十通路端，所述第十控制端链接第二时钟信号，所述第十九通路端连结所述输出端，所述第二十通路端接收所述第N-4级起始脉冲信号或所述第N-4级栅极脉冲信号；
    第十一开关组件，包括第十一控制端、第二十一通路端和第二十二通路端，所述第十一控制端连结所述第二时钟信号，所述第二十一通路端连接所述输出端，所述第二十二通路端连接所述第一电压源；
    第十二开关组件，包括第十二控制端、第二十三通路端和第二十四通路端，所述第二十三通路端连结所述第三控制端，所述第十二控制端连接第N+4级起始脉冲信号或第N+4级栅极脉冲信号，所述第二十四通路端连接所述第一电压源；以及
    第十三开关组件，包括第十三控制端、第二十五通路端和第二十六通路端，所述第十三控制端接收所述第N+4级起始脉冲信号或所述第N+4级栅极脉冲信号，所述第二十五通路端连结所述输出端，所述第二十六通路端连接所述第一电压源；
    其中，N为正整数。
  13. 根据权利要求12所述的显示器，其另包括电容，所述电容的两端分别连结所述第三控制端和所述输出端。
  14. 根据权利要求12所述的显示器，其中所述第一时钟信号和所述第二时钟脉冲信号互为反相。
  15. 根据权利要求12所述的显示器，其中所述第一时钟信号和所述第二时钟脉冲信号的占空比(duty ratio)为50%。
  16. 根据权利要求12所述的显示器，其中所述栅极驱动电路用以驱动二维(2D)影像时的所述第一时钟信号的脉宽是两倍于所述栅极驱动电路用以驱动三维(3D)影像时的所述第一时钟信号的脉宽。
  17. 根据权利要求12所述的显示器，其中所述栅极驱动电路用以驱动二维影像时的所述第一时钟信号的脉宽是两倍于所述栅极驱动电路用以驱动三维影像时的所述第一时钟信号的脉宽。
  18. 根据权利要求17所述的显示器，其中所述栅极驱动电路用以驱动二维影像时，连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+1级栅极驱动单元的所述第一时钟信号的相位差为所述第一时钟信号脉宽的四分之一。
  19. 根据权利要求17所述的显示器，其中所述栅极驱动电路用以驱动三维影像时，连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+1级栅极驱动单元的所述第一时钟信号没有相位差，连接于所述第N+2级栅极驱动单元的所述第一时钟信号与连接于所述第N+3级栅极驱动单元的所述第一时钟信号没有相位差。
  20. 根据权利要求19所述的显示器，其中连接于所述第N级栅极驱动单元的所述第一时钟信号与连接于所述第N+2级栅极驱动单元的所述第一时钟信号的相位差为所述第一时钟信号脉宽的二分之一。
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