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WO2017206269A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2017206269A1
WO2017206269A1 PCT/CN2016/089601 CN2016089601W WO2017206269A1 WO 2017206269 A1 WO2017206269 A1 WO 2017206269A1 CN 2016089601 W CN2016089601 W CN 2016089601W WO 2017206269 A1 WO2017206269 A1 WO 2017206269A1
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WIPO (PCT)
Prior art keywords
pattern
layer
insulating layer
substrate
source pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/089601
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English (en)
French (fr)
Inventor
周志超
夏慧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/115,254 priority Critical patent/US10461097B2/en
Publication of WO2017206269A1 publication Critical patent/WO2017206269A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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    • H10D86/01—Manufacture or treatment
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si

Definitions

  • the present invention relates to the field of array substrate technology, and in particular, to an array substrate and a method for fabricating the same.
  • the current array substrate In the liquid crystal panel industry, the current array substrate generally adopts a bottom gate structure, and the on-state current of the bottom gate structure is extremely dependent on the aspect ratio of the channel. Due to the limited preparation process conditions of the current array substrate, it is difficult to reduce the length of the channel to the 5 micron level, and increasing the width of the channel sacrifices a certain aperture ratio. Therefore, the aspect ratio of the channel of the prior art array substrate cannot be increased, and thus the on-state current of the bottom gate structure cannot be increased.
  • an array substrate including:
  • a ring-shaped gate pattern disposed on the first insulating layer and surrounding the periphery of the source pattern
  • a second insulating layer covering the annular gate pattern, wherein a side of the source pattern remote from the substrate is at least partially exposed through the first insulating layer and the second insulating layer;
  • a semiconductor pattern disposed in a surrounding area of the annular gate pattern and electrically connected to the exposed portion of the source pattern, the semiconductor pattern and the annular gate pattern being further electrically insulated by the second insulating layer;
  • a pixel electrode disposed on the second insulating layer and electrically connected to a side of the semiconductor pattern remote from the substrate;
  • the first insulating layer includes a buffer layer and a passivation layer, wherein the data line is formed in the buffer layer and covered by the passivation layer;
  • the source pattern includes a first source pattern layer and a second source pattern layer which are stacked, wherein the first source pattern layer and the data line are the same material, and the second source pattern layer and the annular gate pattern are The same material.
  • the array substrate includes a scan line electrically connected to the annular gate pattern, and the second insulating layer further covers the scan line.
  • the semiconductor pattern is in direct contact with the exposed portion of the source pattern.
  • the pixel electrode is in direct contact with a side of the semiconductor pattern remote from the substrate.
  • an array substrate including:
  • a ring-shaped gate pattern disposed on the first insulating layer and surrounding the periphery of the source pattern
  • a second insulating layer covering the annular gate pattern, wherein a side of the source pattern remote from the substrate is at least partially exposed through the first insulating layer and the second insulating layer;
  • a semiconductor pattern disposed in a surrounding area of the annular gate pattern and electrically connected to the exposed portion of the source pattern, the semiconductor pattern and the annular gate pattern being further electrically insulated by the second insulating layer;
  • the pixel electrode is disposed on the second insulating layer and electrically connected to a side of the semiconductor pattern remote from the substrate.
  • the array substrate includes a data line electrically connected to the source pattern, and the first insulating layer includes a buffer layer and a passivation layer, wherein the data lines are formed in the buffer layer and covered by the passivation layer.
  • the source pattern includes a first source pattern layer and a second source pattern layer which are stacked, wherein the first source pattern layer and the data line are the same material, and the second source pattern layer and the annular gate pattern are The same material.
  • the array substrate includes a scan line electrically connected to the annular gate pattern, and the second insulating layer further covers the scan line.
  • the semiconductor pattern is in direct contact with the exposed portion of the source pattern.
  • the pixel electrode is in direct contact with a side of the semiconductor pattern remote from the substrate.
  • Another technical solution adopted by the present invention is to provide a method for preparing an array substrate, which includes:
  • first insulating layer Forming a first insulating layer on the substrate and a source pattern disposed in the first insulating layer, wherein the first insulating layer at least partially exposes a side of the source pattern away from the substrate;
  • a pixel electrode is formed on the second insulating layer, wherein the pixel electrode is electrically connected to a side of the semiconductor pattern remote from the substrate.
  • the step of forming a first insulating layer on the substrate and a source pattern disposed in the first insulating layer includes:
  • a passivation layer is formed on the buffer layer and patterned to form an opening on the passivation layer that at least partially exposes the first source pattern layer.
  • the step of forming a ring-shaped gate pattern on the first insulating layer includes:
  • the step of forming a second conductive layer on the passivation layer and performing a patterning process further includes: forming a substrate; and forming a scan line electrically connected to the annular gate pattern.
  • the array substrate of the present invention comprises: a substrate; a first insulating layer disposed on the substrate; a source pattern disposed in the first insulating layer; a ring-shaped gate a pattern disposed on the first insulating layer and surrounding the periphery of the source pattern; a second insulating layer covering the annular gate pattern, wherein a side of the source pattern away from the substrate passes through the first insulating layer and the second The insulating layer is at least partially exposed; the semiconductor pattern is disposed in the surrounding area of the annular gate pattern and electrically connected to the exposed portion of the source pattern, and the second insulating layer is further electrically connected between the semiconductor pattern and the annular gate pattern
  • the pixel electrode is disposed on the second insulating layer and electrically connected to a side of the semiconductor pattern away from the substrate; compared with the prior art array substrate, the bottom gate structure is adopted, and the annular gate structure is used to increase the groove.
  • the width to length ratio of the track increases
  • FIG. 1 is a cross-sectional view showing an array substrate of a first embodiment of the present invention
  • Figure 2 is a plan view of the data line and source pattern of Figure 1;
  • Figure 3 is a plan view of the passivation layer of Figure 1;
  • Figure 4 is a plan view of the scan line and the annular gate pattern of Figure 1;
  • Figure 5 is a plan view of the second insulating layer of Figure 1;
  • Figure 6 is a plan view of the semiconductor pattern of Figure 1;
  • Figure 7 is a plan view of the pixel electrode of Figure 1;
  • Figure 8 is a cross-sectional view of the annular gate pattern of Figure 1;
  • FIG. 9 is a flow chart showing a method of fabricating an array substrate according to a first embodiment of the present invention.
  • Figure 10 is a schematic view of the preparation of the buffer layer of Figure 9;
  • Figure 11 is a schematic view of the first source pattern layer and the data line prepared in Figure 9;
  • Figure 12 is a schematic view of the preparation of the passivation layer of Figure 9;
  • Figure 13 is a schematic view of the second source pattern layer and the annular gate pattern prepared in Figure 9;
  • Figure 14 is a schematic view of the second insulating layer prepared in Figure 9;
  • Figure 15 is a schematic view of the semiconductor pattern prepared in Figure 9;
  • Figure 16 is a schematic view of the pixel electrode prepared in Figure 9;
  • Figure 17 is a schematic view showing the structure of a display panel according to a first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of an array substrate according to a first embodiment of the present invention.
  • the array substrate disclosed in this embodiment includes: a scan line G, a data line D, a substrate 11, a first insulating layer 12, a source pattern 13, an annular gate pattern 14, a second insulating layer 15, a semiconductor pattern 16, and a pixel.
  • the substrate 11 is preferably a glass substrate.
  • the first insulating layer 12 is disposed on the substrate 11, specifically, the first insulating layer 12 includes a buffer layer 121 and a passivation layer 122, by CVD (Chemical Vapor Deposition, Chemical Vapor Deposition) - Photo - Dry (Dry) - Str (stripping) step, a buffer layer 121 is formed on the substrate 11.
  • the data line D and the source pattern 13 are formed on the substrate 11, and since the pattern of the buffer layer 121 is completely identical to the pattern of the data line D, data is formed.
  • the line D and the source pattern 13 do not need to be additionally provided with a mask.
  • the data line D is electrically connected to the source pattern 13, and the source pattern 13 and the data line D are formed in the buffer layer 121, that is, the source pattern 13 and the data line D are buried in the buffer layer 121.
  • the plane in which the source pattern 13 and the data line D are located with the buffer layer 121 is made flat, the hill climbing is prevented from being disposed when other film layers are disposed, and the source pattern 13 and the data line D can be prevented from being oxidized.
  • a passivation layer 122 is formed on the buffer layer 121 by CVD-Photo-Dry-Str, and the data line D is covered by the passivation layer 122 as shown in FIG.
  • the source pattern 13 includes a first source pattern layer 131 and a second source pattern layer 132.
  • the first source pattern layer 131 and the data line D are the same material, and the second source pattern layer 132 and the ring
  • the gate patterns 14 are the same material.
  • the data line D and the annular gate pattern layer 14 are the same material.
  • a data line D and a first source pattern layer 131 are formed on the substrate 11, and the data line D is electrically connected to the first source pattern layer 131.
  • the first source pattern layer 131 and the data line D are formed in the buffer layer 121.
  • the passivation layer 122 covers the data line D and does not cover the first source pattern layer 131.
  • a scan line G and a ring-shaped gate pattern 14 are formed on the first insulating layer 12 by PVD-Photo-Wet-Str, that is, a scan line G and a ring-shaped gate pattern 14 are formed on the passivation layer 122, and the scan line G is formed. It is electrically connected to the annular gate pattern 14.
  • the annular gate pattern 14 is disposed on the first insulating layer 12 and surrounds the periphery of the source pattern 13, that is, the annular gate pattern 14 surrounds the periphery of the first source pattern layer 131, as shown in FIG. .
  • the second source pattern layer 132 is formed on the first source pattern layer 131.
  • the second insulating layer 15 is formed by PVD-Photo-WET-Str.
  • the second insulating layer 15 covers the annular gate pattern 14 and the scan line G, wherein a side of the source pattern 13 remote from the substrate is at least partially exposed through the first insulating layer 12 and the second insulating layer 15, that is, the second source
  • the pole pattern layer 132 is at least partially exposed through the first insulating layer 12 and the second insulating layer 15, as shown in FIG.
  • the semiconductor pattern 16 is formed on the second source pattern layer 132 by CVD-Photo-Dry-Str.
  • the semiconductor pattern 16 is disposed in the surrounding area of the annular gate pattern 14 and electrically connected to the exposed portion of the source pattern 13.
  • the semiconductor pattern 16 and the annular gate pattern 14 are further electrically connected by the second insulating layer 15.
  • the insulating pattern, that is, the semiconductor pattern 16 is electrically connected to the exposed portion of the second source pattern layer 132, as shown in FIG.
  • the semiconductor pattern 16 is in direct contact with the exposed portion of the source pattern 13, that is, the semiconductor pattern 16 is in direct contact with the exposed portion of the second source pattern layer 132.
  • the material of the semiconductor pattern 16 includes amorphous silicon and IGZO (indium gallium zinc). Oxide, indium gallium zinc oxide) or polysilicon.
  • the semiconductor pattern 16 of the present embodiment is preferably made of an amorphous silicon material, and n+ amorphous silicon, that is, phosphorus-doped amorphous silicon, is directly grown by a CVD process, and the n+ amorphous silicon is cut without a Dry process.
  • the pixel electrode 17 is formed on the semiconductor pattern 16 by PVD-Photo-WET-Str.
  • the pixel electrode 17 is disposed on the second insulating layer 15 and electrically connected to a side of the semiconductor pattern 16 remote from the substrate, as shown in FIG. 7 .
  • the pixel electrode 17 is in direct contact with a side of the semiconductor pattern 16 remote from the substrate.
  • the pixel electrode 17 is preferably an ITO (Indium tin oxide) electrode or a MoTi electrode.
  • the semiconductor pattern 16 has a thickness L and a radius R.
  • the semiconductor pattern 16 has a thickness L of about 0.2 microns.
  • the present invention also provides a method of fabricating an array substrate, which is described in detail based on the array substrate disclosed in the first embodiment. As shown in FIG. 9, the preparation method disclosed in this embodiment includes the following steps:
  • Step S901 forming a first insulating layer 12 and a source pattern 13 disposed in the first insulating layer 12 on the substrate 11, wherein the first insulating layer 12 at least partially exposes a side of the source pattern 13 away from the substrate;
  • Step S902 forming an annular gate pattern 14 on the first insulating layer 12, wherein the annular gate pattern 14 surrounds the periphery of the source pattern 13;
  • Step S903 forming a second insulating layer 15 on the annular gate pattern 14, wherein the second insulating layer 15 at least partially exposes a side of the source pattern 13 away from the substrate 11;
  • Step S904 forming a semiconductor pattern 16 in a surrounding area of the annular gate pattern 14, wherein the semiconductor pattern 16 is electrically connected to the exposed portion of the source pattern 13 and the second insulating layer 15 is formed between the annular gate pattern 14 and the annular gate pattern 14. Electrical insulation
  • Step S905 forming a pixel electrode 17 on the second insulating layer 15, wherein the pixel electrode 17 is electrically connected to a side of the semiconductor pattern 16 remote from the substrate 11.
  • the substrate 11 is preferably a glass substrate.
  • a buffer layer 121 is formed on the substrate 11 and patterned to form a trench 111 corresponding to the source pattern 13 and the data line D on the buffer layer 121 as shown in FIG.
  • a passivation layer 122 is formed on the buffer layer 121 and patterned to form an opening on the passivation layer 122 that at least partially exposes the first source pattern layer 131, as shown in FIG.
  • a second conductive layer 113 is formed on the passivation layer 122 and patterned to form a second source pattern layer 132 in the opening and form the annular gate pattern 14 at the periphery of the opening.
  • the first source pattern layer 131 and the second source pattern layer 132 collectively function as the source pattern 13, as shown in FIG.
  • a scanning line G electrically connected to the annular gate pattern 14 is formed on the passivation layer 122.
  • the second insulating layer 15 covers the annular gate pattern 14 and the scan line G, wherein the side of the source pattern 13 remote from the substrate passes through the first insulating layer 12 and the second The insulating layer 15 is at least partially exposed, that is, the second source pattern layer 132 is at least partially exposed through the first insulating layer 12 and the second insulating layer 15, as shown in FIG.
  • a semiconductor pattern 16 is formed on the second source pattern layer 132 as shown in FIG.
  • the semiconductor pattern 16 is disposed in the surrounding area of the annular gate pattern 14 and electrically connected to the exposed portion of the source pattern 13.
  • the semiconductor pattern 16 and the annular gate pattern 14 are further electrically connected by the second insulating layer 15.
  • the insulating pattern, that is, the semiconductor pattern 16 is electrically connected to the exposed portion of the second source pattern layer 132, as shown in FIG.
  • the semiconductor pattern 16 is in direct contact with the exposed portion of the source pattern 13, that is, the semiconductor pattern 16 is in direct contact with the exposed portion of the second source pattern layer 132.
  • step S905 the pixel electrode 17 is formed on the semiconductor pattern 16, as shown in FIG.
  • the pixel electrode 17 is disposed on the second insulating layer 15 and electrically connected to a side of the semiconductor pattern 16 remote from the substrate, as shown in FIG. 7 .
  • the pixel electrode 17 is in direct contact with a side of the semiconductor pattern 16 remote from the substrate.
  • the semiconductor pattern 16 has a thickness L and a radius R.
  • the semiconductor pattern 16 has a thickness L of about 0.2 ⁇ m.
  • the display panel 170 of the present embodiment includes an array substrate 171, a color filter substrate 172, and a liquid crystal layer 173 disposed between the array substrate 171 and the color filter substrate 172.
  • the array substrate 171 disclosed in this embodiment is the array substrate described in the above embodiments, and details are not described herein again.
  • the array substrate of the present invention includes: a substrate; a first insulating layer disposed on the substrate; a source pattern disposed in the first insulating layer; and a ring-shaped gate pattern disposed on the first insulating layer Surrounding the periphery of the source pattern; the second insulating layer covers the annular gate pattern, wherein a side of the source pattern remote from the substrate is at least partially exposed through the first insulating layer and the second insulating layer; a semiconductor pattern is disposed And electrically connected to the exposed portion of the source pattern, the semiconductor pattern and the annular gate pattern are further electrically insulated by the second insulating layer; the pixel electrode is disposed on the second insulating layer
  • the layer is electrically connected to the side of the semiconductor pattern away from the substrate; compared to the prior art array substrate, the bottom gate structure is adopted, and the annular gate structure is adopted, which can increase the aspect ratio of the channel, thereby improving the on state. Current.

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Abstract

一种阵列基板及其制备方法。该阵列基板包括：第一绝缘层（12）设置于基板（11）上；源极图案（13）设置于第一绝缘层（12）内；环状栅极图案（14）设置于第一绝缘层（12）上且环绕于源极图案（13）的外围；第二绝缘层（15）覆盖于环状栅极图案（14）上；半导体图案（16）设置于环状栅极图案（14）的环绕区域内且与源极图案（13）的外露部分电性连接，半导体图案（16）与环状栅极图案（14）之间进一步由第二绝缘层（15）电性绝缘；像素电极（17）设置于第二绝缘层（15）上且与半导体图案（16）的远离基板（11）的一侧电性连接。通过上述方式，能够增加沟道的宽长比，进而提高开态电流。

Description

阵列基板及其制备方法
【技术领域】
本发明涉及阵列基板技术领域，特别是涉及一种阵列基板及其制备方法。
【背景技术】
在液晶面板工业中，目前的阵列基板通常采用底栅结构，而底栅结构的开态电流极为依赖沟道的宽长比。由于目前的阵列基板的制备工艺条件有限，沟道的长度到达5微米级别已很难再缩小，而增加沟道的宽度会牺牲一定的开口率。因此，现有技术的阵列基板的沟道的宽长比无法增加，进而无法增加底栅结构的开态电流。
【发明内容】
本发明的目的在于提供一种阵列基板及其制备方法，能够解决上述问题。
为实现上述目的，本发明采用的一个技术方案是：提供一种阵列基板，其包括：
基板；
第一绝缘层，设置于基板上；
源极图案，设置于第一绝缘层内；
环状栅极图案，设置于第一绝缘层上且环绕于源极图案的外围；
第二绝缘层，覆盖于环状栅极图案上，其中源极图案的远离基板的一侧经第一绝缘层和第二绝缘层至少部分外露；
半导体图案，设置于环状栅极图案的环绕区域内且与源极图案的外露部分电性连接，半导体图案与环状栅极图案之间进一步由第二绝缘层电性绝缘；
像素电极，设置于第二绝缘层上且与半导体图案的远离基板的一侧电性连接；
与源极图案电性连接的数据线，第一绝缘层包括缓冲层和钝化层，其中数据线形成于缓冲层内，并由钝化层覆盖；
其中，源极图案包括层叠设置的第一源极图案层和第二源极图案层，其中第一源极图案层与数据线为同一材料，第二源极图案层与环状栅极图案为同一材料。
其中，阵列基板包括与环状栅极图案电性连接的扫描线，第二绝缘层进一步覆盖扫描线。
其中，半导体图案与源极图案的外露部分直接接触。
其中，像素电极与半导体图案的远离基板的一侧直接接触。
为实现上述目的，本发明采用的一个技术方案是：提供一种阵列基板，其包括：
基板；
第一绝缘层，设置于基板上；
源极图案，设置于第一绝缘层内；
环状栅极图案，设置于第一绝缘层上且环绕于源极图案的外围；
第二绝缘层，覆盖于环状栅极图案上，其中源极图案的远离基板的一侧经第一绝缘层和第二绝缘层至少部分外露；
半导体图案，设置于环状栅极图案的环绕区域内且与源极图案的外露部分电性连接，半导体图案与环状栅极图案之间进一步由第二绝缘层电性绝缘；
像素电极，设置于第二绝缘层上且与半导体图案的远离基板的一侧电性连接。
其中，阵列基板包括与源极图案电性连接的数据线，第一绝缘层包括缓冲层和钝化层，其中数据线形成于缓冲层内，并由钝化层覆盖。
其中，源极图案包括层叠设置的第一源极图案层和第二源极图案层，其中第一源极图案层与数据线为同一材料，第二源极图案层与环状栅极图案为同一材料。
其中，阵列基板包括与环状栅极图案电性连接的扫描线，第二绝缘层进一步覆盖扫描线。
其中，半导体图案与源极图案的外露部分直接接触。
其中，像素电极与半导体图案的远离基板的一侧直接接触。
为实现上述目的，本发明采用的另一个技术方案是：提供一种阵列基板的制备方法，其包括：
基板；
在基板上形成第一绝缘层以及设置于第一绝缘层内的源极图案，其中第一绝缘层至少部分外露源极图案的远离基板的一侧；
在第一绝缘层上形成环状栅极图案，其中环状栅极图案环绕于源极图案的外围；
在环状栅极图案上形成第二绝缘层，其中第二绝缘层至少部分外露源极图案的远离基板的一侧；
在环状栅极图案的环绕区域内形成半导体图案，其中半导体图案与源极图案的外露部分电性连接且与环状栅极图案之间由第二绝缘层电性绝缘；
在第二绝缘层形成像素电极，其中像素电极与半导体图案的远离基板的一侧电性连接。
其中，在基板上形成第一绝缘层以及设置于第一绝缘层内的源极图案的步骤包括：
在基板上形成缓冲层并进行图案化处理，以在缓冲层上形成与源极图案和数据线对应的沟槽；
在缓冲层上形成第一导电层并进行图案化处理，以在沟槽内形成第一源极图案层和数据线；
在缓冲层上形成钝化层并进行图案化处理，以在钝化层上形成至少部分外露第一源极图案层的开口。
其中，在第一绝缘层上形成环状栅极图案的步骤包括：
在钝化层上形成第二导电层并进行图案化处理，以在开口内形成第二源极图案层并在开口的外围形成环状栅极图案，其中第一源极图案层和第二源极图案层共同作为源极图案。
其中，在钝化层上形成第二导电层并进行图案化处理的步骤进一步包括：基板；形成与环状栅极图案电性连接的扫描线。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板包括：基板；第一绝缘层，设置于基板上；源极图案，设置于第一绝缘层内；环状栅极图案，设置于第一绝缘层上且环绕于源极图案的外围；第二绝缘层，覆盖于环状栅极图案上，其中源极图案的远离基板的一侧经第一绝缘层和第二绝缘层至少部分外露；半导体图案，设置于环状栅极图案的环绕区域内且与源极图案的外露部分电性连接，半导体图案与环状栅极图案之间进一步由第二绝缘层电性绝缘；像素电极，设置于第二绝缘层上且与半导体图案的远离基板的一侧电性连接；相较于现有技术的阵列基板采用底栅结构，采用环状栅极结构，能够增加沟道的宽长比，进而提高开态电流。
【附图说明】
】
图1是本发明第一实施例的阵列基板的剖面图；
图2是图1中数据线与源极图案的平面图；
图3是图1中钝化层的平面图；
图4是图1中扫描线和环状栅极图案的平面图；
图5是图1中第二绝缘层的平面图；
图6是图1中半导体图案的平面图；
图7是图1中像素电极的平面图；
图8是图1中环状栅极图案的剖面图；
图9是本发明第一实施例的阵列基板的制备方法的流程图；
图10是图9中制备缓冲层的示意图；
图11是图9中制备第一源极图案层和数据线的示意图；
图12是图9中制备钝化层的示意图；
图13是图9中制备第二源极图案层和环状栅极图案的示意图；
图14是图9中制备第二绝缘层的示意图；
图15是图9中制备半导体图案的示意图；
图16是图9中制备像素电极的示意图；
图17是本发明第一实施例的显示面板的结构示意图。
【具体实施方式】
请参见图1，图1是本发明第一实施例的阵列基板的剖面图。本实施例所揭示的阵列基板包括：扫描线G、数据线D、基板11、第一绝缘层12、源极图案13、环状栅极图案14、第二绝缘层15、半导体图案16以及像素电极17。
其中，基板11优选为玻璃基板。第一绝缘层12设置在基板11上，具体而言，第一绝缘层12包括缓冲层121和钝化层122，通过CVD （Chemical Vapor Deposition，化学气相沉积）–Photo（曝光）-Dry（干刻）-Str（剥离）步骤，在基板11上形成缓冲层121。
通过PVD（Physical Vapor Deposition，物理气相沉积）-Photo-Wet（湿刻）-Str，在基板11上形成数据线D和源极图案13，由于缓冲层121的图案与数据线D的图案完全一致，因此在形成数据线D和源极图案13时无需额外增加一道光罩。
结合图2所示，数据线D与源极图案13电性连接，源极图案13和数据线D形成于缓冲层121内，即源极图案13和数据线D埋在缓冲层121内，能够使得源极图案13和数据线D与缓冲层121所在的平面平坦，避免设置其他膜层时爬坡，并且能够防止源极图案13和数据线D氧化。
通过CVD-Photo-Dry-Str，在缓冲层121上形成钝化层122，数据线D由钝化层122覆盖，如图3所示。
其中，源极图案13包括层叠设置的第一源极图案层131和第二源极图案层132，第一源极图案层131与数据线D为同一材料，第二源极图案层132与环状栅极图案14为同一材料。优选地，数据线D和环状栅极图案层14为同一材料。
在基板11上形成数据线D和第一源极图案层131，数据线D与第一源极图案层131电性连接，第一源极图案层131和数据线D形成于缓冲层121内。钝化层122覆盖数据线D，并未覆盖第一源极图案层131。
通过PVD-Photo-Wet-Str，在第一绝缘层12上形成扫描线G和环状栅极图案14，即在钝化层122上形成扫描线G和环状栅极图案14，扫描线G与环状栅极图案14电性连接。其中，环状栅极图案14设置于第一绝缘层12上且环绕于源极图案13的外围，即环状栅极图案14环绕于第一源极图案层131的外围，如图4所示。
在第一绝缘层12上形成扫描线G和环状栅极图案14时，在第一源极图案层131上形成第二源极图案层132。
通过PVD-Photo-WET-Str，形成第二绝缘层15。第二绝缘层15覆盖于环状栅极图案14和扫描线G上，其中源极图案13的远离基板的一侧经第一绝缘层12和第二绝缘层15至少部分外露，即第二源极图案层132经第一绝缘层12和第二绝缘层15至少部分外露，如图5所示。
通过CVD-Photo-Dry-Str，在第二源极图案层132上形成半导体图案16。其中，半导体图案16设置于环状栅极图案14的环绕区域内且与源极图案13的外露部分电性连接，半导体图案16与环状栅极图案14之间进一步由第二绝缘层15电性绝缘，即半导体图案16与第二源极图案层132的外露部分电性连接，如图6所示。
具体而言，半导体图案16与源极图案13的外露部分直接接触，即半导体图案16与第二源极图案层132的外露部分直接接触。
其中，半导体图案16的材料包括非晶硅、IGZO（indium gallium zinc oxide，铟镓锌氧化物）或者多晶硅。本实施例的半导体图案16优选采用非晶硅材料，直接通过CVD制程生长n+非晶硅，即掺磷非晶硅，无需Dry制程对n+非晶硅进行切断。
通过PVD-Photo-WET-Str，在半导体图案16上形成像素电极17。像素电极17设置于第二绝缘层15上且与半导体图案16的远离基板的一侧电性连接，如图7所示。其中，像素电极17与半导体图案16的远离基板的一侧直接接触。
其中，像素电极17优选为ITO（Indium tin oxide，氧化铟锡）电极或者MoTi电极。
进一步参见图8所示，半导体图案16的厚度为L，半径为R，通常半导体图案16的厚度L约为0.2微米。例如，半导体图案16的半径R为4微米，则环状栅极图案14的沟道宽比为W/L=2πR/L=120。因此本实施例所揭示的阵列基板的沟道宽比大于或等于120，相对于现有技术的沟道宽比为1-10，能够增加沟道的宽长比，进而提高开态电流，增加充电率。
本发明还提供一种阵列基板的制备方法，其基于第一实施例所揭示的阵列基板进行详细描述。如图9所示，本实施例所揭示的制备方法包括以下步骤：
步骤S901：在基板11上形成第一绝缘层12以及设置于第一绝缘层12内的源极图案13，其中第一绝缘层12至少部分外露源极图案13的远离基板的一侧；
步骤S902：在第一绝缘层12上形成环状栅极图案14，其中环状栅极图案14环绕于源极图案13的外围；
步骤S903：在环状栅极图案14上形成第二绝缘层15，其中第二绝缘层15至少部分外露源极图案13的远离基板11的一侧；
步骤S904：在环状栅极图案14的环绕区域内形成半导体图案16，其中半导体图案16与源极图案13的外露部分电性连接且与环状栅极图案14之间由第二绝缘层15电性绝缘；
步骤S905：在第二绝缘层15形成像素电极17，其中像素电极17与半导体图案16的远离基板11的一侧电性连接。
在步骤S901中，基板11优选为玻璃基板。在基板11上形成缓冲层121并进行图案化处理，以在缓冲层121上形成与源极图案13和数据线D对应的沟槽111，如图10所示。
在缓冲层121上形成第一导电层112并进行图案化处理，以在沟槽111内形成第一源极图案层131和数据线D，如图11所示；
在缓冲层121上形成钝化层122并进行图案化处理，以在钝化层122上形成至少部分外露第一源极图案层131的开口，如图12所示。
在步骤S902中，在钝化层122上形成第二导电层113并进行图案化处理，以在开口内形成第二源极图案层132并在开口的外围形成所述环状栅极图案14，其中第一源极图案层131和第二源极图案层132共同作为源极图案13，如图13所示。
此外，在钝化层122上形成与环状栅极图案14电性连接的扫描线G。
在步骤S903中，如图14所示，第二绝缘层15覆盖于环状栅极图案14和扫描线G上，其中源极图案13的远离基板的一侧经第一绝缘层12和第二绝缘层15至少部分外露，即第二源极图案层132经第一绝缘层12和第二绝缘层15至少部分外露，如图5所示。
在步骤S904中，在第二源极图案层132上形成半导体图案16，如图15所示。其中，半导体图案16设置于环状栅极图案14的环绕区域内且与源极图案13的外露部分电性连接，半导体图案16与环状栅极图案14之间进一步由第二绝缘层15电性绝缘，即半导体图案16与第二源极图案层132的外露部分电性连接，如图6所示。具体而言，半导体图案16与源极图案13的外露部分直接接触，即半导体图案16与第二源极图案层132的外露部分直接接触。
在步骤S905中，在半导体图案16上形成像素电极17，如图16所示。像素电极17设置于第二绝缘层15上且与半导体图案16的远离基板的一侧电性连接，如图7所示。其中，像素电极17与半导体图案16的远离基板的一侧直接接触。
如图8所示，半导体图案16的厚度为L，半径为R，通常半导体图案16的厚度L约为0.2微米。例如，半导体图案16的半径R为4微米，则环状栅极图案14的沟道宽比为W/L=2πR/L=120。因此本实施例所揭示的阵列基板的沟道宽比大于或等于120，相对于现有技术的沟道宽比为1-10，能够增加沟道的宽长比，进而提高开态电流，增加充电率。
本发明还提供一种显示面板，如图17所示，本实施例所揭示的显示面板170包括阵列基板171、彩膜基板172以及设置在阵列基板171和彩膜基板172之间的液晶层173，本实施例所揭示的阵列基板171为上述实施例所描述的阵列基板，在此不再赘述。
综上所述，本发明的阵列基板包括：基板；第一绝缘层，设置于基板上；源极图案，设置于第一绝缘层内；环状栅极图案，设置于第一绝缘层上且环绕于源极图案的外围；第二绝缘层，覆盖于环状栅极图案上，其中源极图案的远离基板的一侧经第一绝缘层和第二绝缘层至少部分外露；半导体图案，设置于环状栅极图案的环绕区域内且与源极图案的外露部分电性连接，半导体图案与环状栅极图案之间进一步由第二绝缘层电性绝缘；像素电极，设置于第二绝缘层上且与半导体图案的远离基板的一侧电性连接；相较于现有技术的阵列基板采用底栅结构，采用环状栅极结构，能够增加沟道的宽长比，进而提高开态电流。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    第一绝缘层，设置于所述基板上；
    源极图案，设置于所述第一绝缘层内；
    环状栅极图案，设置于所述第一绝缘层上且环绕于所述源极图案的外围；
    第二绝缘层，覆盖于所述环状栅极图案上，其中所述源极图案的远离所述基板的一侧经所述第一绝缘层和所述第二绝缘层至少部分外露；
    半导体图案，设置于所述环状栅极图案的环绕区域内且与所述源极图案的外露部分电性连接，所述半导体图案与所述环状栅极图案之间进一步由所述第二绝缘层电性绝缘；
    像素电极，设置于所述第二绝缘层上且与所述半导体图案的远离所述基板的一侧电性连接；
    与所述源极图案电性连接的数据线，所述第一绝缘层包括缓冲层和钝化层，其中所述数据线形成于所述缓冲层内，并由所述钝化层覆盖；
    其中，所述源极图案包括层叠设置的第一源极图案层和第二源极图案层，其中所述第一源极图案层与所述数据线为同一材料，所述第二源极图案层与所述环状栅极图案为同一材料。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括与所述环状栅极图案电性连接的扫描线，所述第二绝缘层进一步覆盖所述扫描线。
  3. 根据权利要求1所述的阵列基板，其中，所述半导体图案与所述源极图案的外露部分直接接触。
  4. 根据权利要求1所述的阵列基板，其中，所述像素电极与所述半导体图案的远离所述基板的一侧直接接触。
  5. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    第一绝缘层，设置于所述基板上；
    源极图案，设置于所述第一绝缘层内；
    环状栅极图案，设置于所述第一绝缘层上且环绕于所述源极图案的外围；
    第二绝缘层，覆盖于所述环状栅极图案上，其中所述源极图案的远离所述基板的一侧经所述第一绝缘层和所述第二绝缘层至少部分外露；
    半导体图案，设置于所述环状栅极图案的环绕区域内且与所述源极图案的外露部分电性连接，所述半导体图案与所述环状栅极图案之间进一步由所述第二绝缘层电性绝缘；
    像素电极，设置于所述第二绝缘层上且与所述半导体图案的远离所述基板的一侧电性连接。
  6. 根据权利要求5所述的阵列基板，其中，所述阵列基板包括与所述源极图案电性连接的数据线，所述第一绝缘层包括缓冲层和钝化层，其中所述数据线形成于所述缓冲层内，并由所述钝化层覆盖。
  7. 根据权利要求5所述的阵列基板，其中，所述源极图案包括层叠设置的第一源极图案层和第二源极图案层，其中所述第一源极图案层与所述数据线为同一材料，所述第二源极图案层与所述环状栅极图案为同一材料。
  8. 根据权利要求5所述的阵列基板，其中，所述阵列基板包括与所述环状栅极图案电性连接的扫描线，所述第二绝缘层进一步覆盖所述扫描线。
  9. 根据权利要求5所述的阵列基板，其中，所述半导体图案与所述源极图案的外露部分直接接触。
  10. 根据权利要求5所述的阵列基板，其中，所述像素电极与所述半导体图案的远离所述基板的一侧直接接触。
  11. 一种阵列基板的制备方法，其中，所述制备方法包括：
    基板；
    在所述基板上形成第一绝缘层以及设置于所述第一绝缘层内的源极图案，其中所述第一绝缘层至少部分外露所述源极图案的远离所述基板的一侧；
    在所述第一绝缘层上形成环状栅极图案，其中所述环状栅极图案环绕于所述源极图案的外围；
    在所述环状栅极图案上形成第二绝缘层，其中所述第二绝缘层至少部分外露所述源极图案的远离所述基板的一侧；
    在所述环状栅极图案的环绕区域内形成半导体图案，其中所述半导体图案与所述源极图案的外露部分电性连接且与所述环状栅极图案之间由所述第二绝缘层电性绝缘；
    在所述第二绝缘层形成像素电极，其中所述像素电极与所述半导体图案的远离所述基板的一侧电性连接。
  12. 根据权利要求11所述的制备方法，其中，所述在所述基板上形成第一绝缘层以及设置于所述第一绝缘层内的源极图案的步骤包括：
    在所述基板上形成缓冲层并进行图案化处理，以在所述缓冲层上形成与所述源极图案和数据线对应的沟槽；
    在所述缓冲层上形成第一导电层并进行图案化处理，以在所述沟槽内形成第一源极图案层和所述数据线；
    在所述缓冲层上形成钝化层并进行图案化处理，以在所述钝化层上形成至少部分外露所述第一源极图案层的开口。
  13. 根据权利要求12所述的制备方法，其中，在所述第一绝缘层上形成环状栅极图案的步骤包括：
    在所述钝化层上形成第二导电层并进行图案化处理，以在所述开口内形成第二源极图案层并在所述开口的外围形成所述环状栅极图案，其中所述第一源极图案层和所述第二源极图案层共同作为所述源极图案。
  14. 根据权利要求13所述的制备方法，其中，在所述钝化层上形成第二导电层并进行图案化处理的步骤进一步包括：
    形成与所述环状栅极图案电性连接的扫描线。
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