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WO2014019252A1 - 液晶显示装置、阵列基板及其制作方法 - Google Patents

液晶显示装置、阵列基板及其制作方法 Download PDF

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Publication number
WO2014019252A1
WO2014019252A1 PCT/CN2012/079928 CN2012079928W WO2014019252A1 WO 2014019252 A1 WO2014019252 A1 WO 2014019252A1 CN 2012079928 W CN2012079928 W CN 2012079928W WO 2014019252 A1 WO2014019252 A1 WO 2014019252A1
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WIPO (PCT)
Prior art keywords
auxiliary electrode
insulating layer
disposed
data line
metal layer
Prior art date
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Ceased
Application number
PCT/CN2012/079928
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English (en)
French (fr)
Inventor
陈政鸿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/641,112 priority Critical patent/US20140036188A1/en
Publication of WO2014019252A1 publication Critical patent/WO2014019252A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display device, an array substrate, and a method of fabricating the same.
  • the manufacturing process of the liquid crystal display panel is generally divided into an Array process, a Cell process, and a Module process.
  • the array process mainly produces a thin film transistor glass substrate (also referred to as an array substrate), which is the first process of the liquid crystal display panel manufacturing process, and the resulting thin film transistor glass substrate has a great influence on the subsequent process, and even Decide whether the LCD panel is good or bad.
  • FIG. 1 is a schematic diagram of a Layout structure of a prior art array substrate
  • FIG. 2 is an array along the array shown in FIG. A cross-sectional view of the AB line cut of the substrate.
  • the five-pass process of the prior art first forms the gate 110 and the scan line of the thin film transistor 140 from the first metal layer (M1) 11.
  • Line or Scan Line 111 and the common electrode 120 then forming a first insulating layer on the first metal layer 11 (Isolator) Layer 12, and forming a semiconductor layer 13 on the first insulating layer 12 corresponding to the first metal layer 11 for forming the gate electrode 110 of the thin film transistor 140; then on the first insulating layer 12 and the semiconductor layer 13 Forming a second metal layer 14 for forming a data line 141, a source 142 and a drain 143 of the thin film transistor 140; and forming a second insulating layer 15 on the second metal layer 14 and the first insulating layer 12; A transparent conductive layer 16 is formed on the second insulating layer 15 for forming a pixel electrode (Pixel) Electrode, referred to as PE) 161.
  • PE pixel electrode
  • FIG. 3 is a schematic diagram of a pixel layout structure of an array substrate for reducing scan line and data line impedance in the prior art.
  • FIG. 3 is an improvement on the basis of the array substrate shown in FIG. 1 and FIG. In order to reduce the impedance of the scan line 110 and the data line 141.
  • FIG. 3 is a view showing that the second metal layer 14 is added to a partial region of the scan line 110 formed by the first metal layer 11 shown in FIG. 1, thereby accelerating the ability of the scan line 110 to transmit a scan signal.
  • the pixel electrode 161 formed by the via hole (VIA) 17 and the transparent conductive layer 16 switches the scanning signal between the first metal layer 11 and the second metal layer 14.
  • FIG. 3 is a schematic diagram of a pixel layout structure of an array substrate for reducing scan line and data line impedance in the prior art.
  • FIG. 3 is an improvement on the basis of the array substrate shown in FIG. 1 and FIG. In order to reduce the impedance of the scan line 110 and the data line
  • the use of the pixel layout method shown in FIG. 3 can achieve the purpose of reducing the impedance of the scan line and the data line without increasing the cost, but it is necessary to pass the via hole 17 and the transparent conductive layer 16 to scan the signal or the data signal. Switching between their respective first metal layers and second metal layers.
  • the transparent conductive layer 16 has a higher resistance and the interface resistance between the transparent conductive layer 16 and the first metal layer 11 or the second metal layer 14 is larger.
  • the effect of using the structure shown in FIG. 3 to reduce the impedance of the scan line and the data line is not good.
  • the structure of the via hole which is increased in a large amount on the pixel electrode reduces the aperture ratio and brightness of the pixel electrode, but instead Will affect the picture quality of the liquid crystal display device.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display device, an array substrate, and a method of fabricating the same, which can reduce the impedance of the scan line and the data line, thereby improving the picture quality of the liquid crystal display device.
  • the present invention adopts a technical solution to provide an array substrate
  • the array substrate includes: a substrate; a first metal layer disposed on the substrate for forming a scan line, a gate of the thin film transistor, and a common electrode; a first insulating layer disposed on the first metal layer; a transparent conductive layer disposed on the first insulating layer to form a source, a drain, and a pixel electrode of the thin film transistor, and the pixel electrode and the thin film transistor a drain connection; a second insulating layer disposed on the transparent conductive layer, the second insulating layer is provided with a first via hole at a position corresponding to a source of the thin film transistor; and a second metal layer is disposed on the second insulating layer Forming a data line, wherein the data line is connected to the source of the thin film transistor through the first via hole; wherein the array substrate further comprises an auxiliary electrode, the auxiliary electrode being at least one of the first metal layer and the second metal layer Forming
  • the auxiliary electrode comprises a first auxiliary electrode and a second auxiliary electrode, the first auxiliary electrode is formed by the first metal layer, and the second auxiliary electrode is formed by the second metal layer, wherein:
  • the first auxiliary electrode is connected to the data line through the second via hole penetrating the first insulating layer and the second insulating layer, so as to reduce the impedance of the data line, the first auxiliary electrode is correspondingly disposed under the data line, and the first An auxiliary electrode is disposed between the scan line and the common electrode along an extending direction of the data line;
  • the second auxiliary electrode is connected to the scan line through the third via hole crossing the first insulating layer and the second insulating layer to reduce the impedance of the scan line, the second auxiliary electrode is correspondingly disposed above the scan line, and the second The auxiliary electrode is disposed between two adjacent data lines along the extending direction of the scanning line.
  • a liquid crystal display device including an array substrate, the array substrate comprising: a substrate; and a first metal layer disposed on the substrate for forming a scan a line, a gate of the thin film transistor, and a common electrode; a first insulating layer disposed on the first metal layer; and a transparent conductive layer disposed on the first insulating layer to form a source, a drain, and a pixel electrode of the thin film transistor And the pixel electrode is connected to the drain of the thin film transistor; the second insulating layer is disposed on the transparent conductive layer, and the second insulating layer is provided with the first via hole at a position corresponding to the source of the thin film transistor; the second metal a layer disposed on the second insulating layer for forming a data line, wherein the data line is connected to the source of the thin film transistor through the first via hole; wherein the array substrate further comprises an auxiliary electrode, the auxiliary electrode is formed by the first
  • the auxiliary electrode is formed by the first metal layer, and the auxiliary electrode is connected to the data line through the second via hole penetrating the first insulating layer and the second insulating layer, so as to reduce the impedance of the data line, and the auxiliary electrode is correspondingly disposed in the Below the data line, and the auxiliary electrode is disposed between the scan line and the common electrode along the extending direction of the data line.
  • the auxiliary electrode is formed by the second metal layer, and the auxiliary electrode is connected to the scan line through the third via hole crossing the first insulating layer and the second insulating layer, so as to reduce the impedance of the scan line, and the auxiliary electrode is correspondingly arranged in the scan. Above the line, and the auxiliary electrode is disposed between two adjacent data lines along the extending direction of the scan line.
  • the auxiliary electrode comprises a first auxiliary electrode and a second auxiliary electrode, the first auxiliary electrode is formed by the first metal layer, and the second auxiliary electrode is formed by the second metal layer, wherein:
  • the first auxiliary electrode is connected to the data line through the second via hole penetrating the first insulating layer and the second insulating layer, so as to reduce the impedance of the data line, the first auxiliary electrode is correspondingly disposed under the data line, and the first An auxiliary electrode is disposed between the scan line and the common electrode along an extending direction of the data line;
  • the second auxiliary electrode is connected to the scan line through the third via hole crossing the first insulating layer and the second insulating layer to reduce the impedance of the scan line, the second auxiliary electrode is correspondingly disposed above the scan line, and the second The auxiliary electrode is disposed between two adjacent data lines along the extending direction of the scanning line.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, the method comprising: providing a substrate; and disposing a first metal layer on the substrate to form a scan line and a film a gate of the transistor and a common electrode; a first insulating layer disposed on the first metal layer; a transparent conductive layer disposed on the first insulating layer to form a source, a drain, and a pixel electrode of the thin film transistor, and a thin film transistor a pole is connected to the pixel electrode; a second insulating layer is disposed on the transparent conductive layer, and a first via hole is disposed at a position of the second insulating layer corresponding to a source of the thin film transistor; and a second layer is disposed on the second insulating layer a metal layer for forming a data line, wherein the data line is connected to a source of the thin film transistor through the first via hole; wherein an auxiliary electrode is further disposed, the auxiliary electrode
  • the step of disposing the first insulating layer on the first metal layer includes:
  • a semiconductor layer is formed on the first insulating layer corresponding to the gate of the thin film transistor, wherein the source and the drain of the thin film transistor are respectively connected to the semiconductor layer.
  • the auxiliary electrode is formed by the first metal layer, the auxiliary electrode is disposed under the data line, and the auxiliary electrode is disposed between the scan line and the common electrode along the extending direction of the data line, by penetrating the first insulating layer and the second The second via of the insulating layer connects the auxiliary electrode and the data line.
  • the auxiliary electrode is formed by the second metal layer, the auxiliary electrode is disposed above the scan line, and the auxiliary electrode is disposed between the two adjacent data lines along the extending direction of the scan line, by penetrating the first insulating layer and the first The third via of the two insulating layers connects the auxiliary electrode and the scan line.
  • the auxiliary electrode comprises a first auxiliary electrode and a second auxiliary electrode, the first auxiliary electrode is formed by the first metal layer, and the second auxiliary electrode is formed by the second metal layer, wherein:
  • a first auxiliary electrode is disposed under the data line, and the first auxiliary electrode is disposed between the scan line and the common electrode along an extending direction of the data line, and penetrates the second conductive layer through the first insulating layer and the second insulating layer The hole connects the first auxiliary electrode and the data line;
  • a second auxiliary electrode is disposed above the scan line, and the second auxiliary electrode is disposed between the two adjacent data lines along the extending direction of the scan line, and passes through the third conductive layer of the first insulating layer and the second insulating layer The via connects the second auxiliary electrode to the scan line.
  • the present invention is formed by providing an auxiliary electrode, and the auxiliary electrode is formed by at least one of a first metal layer and a second metal layer for forming scan lines and data lines Therefore, when transmitting the scan signal or the data signal, the scan signal or the data signal is jointly transmitted by the auxiliary electrode and the scan line or the auxiliary electrode and the data line, thereby widening the path of the signal transmission, thereby reducing the data line or the scan line.
  • the impedance of the liquid crystal display device improves the picture quality.
  • FIG. 1 is a schematic diagram of a pixel layout structure of a prior art array substrate
  • Figure 2 is a cross-sectional view taken along line A-B of the array substrate shown in Figure 1;
  • FIG. 3 is a schematic diagram showing a pixel layout structure of an array substrate for reducing scan line and data line impedance in the prior art
  • FIG. 4 is a schematic diagram showing a pixel layout structure of an array substrate according to the present invention.
  • Figure 5 is a cross-sectional view of the array substrate shown in Figure 4 taken along the line E-F;
  • Figure 6 is a cross-sectional view of the array substrate shown in Figure 4 taken along the line A-B;
  • Figure 7 is a cross-sectional view of the array substrate shown in Figure 4 taken along the line C-D;
  • FIG. 8 is a flow chart of an embodiment of a method for fabricating an array substrate of the present invention.
  • FIG. 9 is a schematic diagram of a five-mask process of the array substrate of FIG.
  • FIG. 4 is a schematic diagram of a pixel layout structure of an array substrate according to the present invention
  • FIG. 5 is a cross-sectional view of the array substrate shown in FIG. 4 taken along a line E-F.
  • FIG. 4 shows only one pixel layout structure on the substrate 50 of the array substrate 500.
  • the pixel layout structure consists of two scanning lines 511 arranged in parallel and two data arranged in parallel.
  • the line 571, the thin film transistor 540, the common electrode 512, and the pixel electrode 543 are composed.
  • the two scanning lines 511 are perpendicular to the two data lines 571 to form a rectangular area, and the pixel electrode 543 is disposed in the rectangular area.
  • the scan line 511 is connected to the gate 510 of the thin film transistor 540
  • the data line 571 is connected to the source 541 of the thin film transistor 540
  • the drain 542 of the thin film transistor 540 is connected to the pixel electrode 543.
  • the common electrode 512 is disposed between the two scan lines 511 and below the pixel electrode 543, and a capacitor structure is formed between the common electrode 512 and the pixel electrode 543.
  • FIG. 5 For the specific location of each component in the array substrate 500, please refer to FIG. 5.
  • the array substrate 500 includes a substrate 50, a first metal layer 51, a first insulating layer 52, a transparent conductive layer 54, a second insulating layer 55, and a second metal layer 57.
  • the first metal layer 51 is disposed on the substrate 50 for forming the gate 510 of the thin film transistor 540, the scan line 511 (shown in FIG. 4), and the common electrode 512.
  • the first insulating layer 52 is disposed on the first metal layer 51.
  • the transparent conductive layer 54 is disposed on the first insulating layer 52.
  • the transparent conductive layer 54 is used to form the source 541, the drain 542 and the pixel electrode 543 of the thin film transistor 540, and the pixel electrode 543 and the drain 542 of the thin film transistor 540. connection.
  • the second insulating layer 55 is disposed on the transparent conductive layer 54, and the second insulating layer 55 is provided with a first via hole 56 at a position corresponding to the source 541 of the thin film transistor 540.
  • the second metal layer 57 is disposed on the second insulating layer 55 corresponding to the source 541 of the thin film transistor 540, and the second metal layer 57 is used to form the data line 571.
  • the data line 571 is connected to the source 541 of the thin film transistor 540 through the first via hole 56.
  • a semiconductor layer 53 is further disposed on the first insulating layer 52 corresponding to the gate 510 of the thin film transistor 540, and the semiconductor layer 53 is connected to the source 541 and the drain 542, wherein the semiconductor layer 53 is opposite to the thin film transistor.
  • 540 acts as a switch. specifically:
  • the gate 510 of the thin film transistor 540 serves as a control electrode.
  • the scan line 511 supplies a scan signal to the gate 510 of the thin film transistor 540
  • the semiconductor layer 53 is turned on, and the thin film transistor 540 is turned on, as an input electrode of the thin film transistor 540.
  • the source 541 and the drain 542 as the output electrode are electrically connected through the semiconductor layer 53; when the gate 510 of the thin film transistor 540 has no input scan signal, the semiconductor layer 53 is not turned on, so that the thin film transistor 540 is turned off, the source
  • the pole 541 and the drain 542 are electrically insulated.
  • the array substrate 50 further includes an auxiliary electrode 501, and the auxiliary electrode 501 is formed by at least one of the first metal layer and the second metal layer.
  • Figure 6 is a cross-sectional view of the array substrate shown in Figure 4 taken along the line A-B;
  • Figure 7 is a cross-sectional view of the array substrate shown in Figure 4 taken along the line C-D.
  • the auxiliary electrode 501 (shown in FIG. 6) includes a first auxiliary electrode 513, and the first auxiliary electrode 513 is disposed between the scan line 511 and the common electrode 512 and corresponds to the lower side of the data line 571.
  • the specific structure of the first auxiliary electrode 513 is shown in FIG. 6 .
  • the first auxiliary electrode 513 is disposed under the data line 571 , specifically, the first auxiliary electrode 513 is disposed under the first insulating layer 52 , and the first auxiliary electrode 513 extends along the data line 571 .
  • the direction is disposed between the scan line 511 and the common electrode 512, and is connected to the data line 571 through the second via hole 58 penetrating the first insulating layer 52 and the second insulating layer 55.
  • the first auxiliary electrode 513 is preferably formed of a first metal layer, whereby the cost of the material can be reduced.
  • the data signal of the data line 571 in addition to being transmitted in the data line 571, in the region where the first auxiliary electrode 513 is disposed, the data signal of the data line 571 can be transmitted to the first auxiliary through the via 58.
  • the electrode 513 is delivered. This broadens the path of data signal conduction. Therefore, the impedance of the data line 571 is reduced, thereby improving the picture quality of the liquid crystal display device.
  • the auxiliary electrode 501 further includes a second auxiliary electrode 572, and the specific structure of the second auxiliary electrode 572 is shown in FIG.
  • the second auxiliary electrode 572 is disposed above the scan line 511 , specifically, the second auxiliary electrode 572 is disposed on the second insulating layer 55 , and the second auxiliary electrode 572 extends along the scan line 511 . It is disposed between two adjacent data lines 571. And the second auxiliary electrode 572 is connected to the scan line 511 through the third via hole 59 penetrating the first insulating layer 52 and the second insulating layer 55.
  • the second auxiliary electrode 572 is preferably formed of a second metal layer, whereby the cost of the material can be reduced.
  • the scanning signal of the scanning line 511 can be transmitted to the third through the third via hole 59.
  • the second auxiliary electrode 572 is transferred. This broadens the path of the scan signal conduction. Therefore, the impedance of the scanning line 511 is reduced, thereby improving the picture quality of the liquid crystal display device.
  • the provision of the second auxiliary electrode 572 above the scanning line 511 and the provision of the first auxiliary electrode 513 under the data line 571 can reduce the impedance of the scanning line 511 and the data line 571, thereby improving the picture quality of the liquid crystal display device. .
  • the auxiliary electrode 501 may be provided only above the scanning line 511 or the auxiliary electrode 501 may be provided only below the data line 571 in consideration of the cost.
  • the auxiliary electrode 501 When the auxiliary electrode 501 is disposed only above the scanning line 511, the auxiliary electrode 501 is formed of a second metal layer, the auxiliary electrode 501 is correspondingly disposed above the scanning line 511, and the auxiliary electrode 501 is disposed along the extending direction of the scanning line 511. Between the two adjacent data lines 571, the auxiliary electrode 501 is connected to the scan line 511 through the third via hole 59 penetrating the first insulating layer 52 and the second insulating layer 55.
  • the structure of the specific auxiliary electrode 501 is as described above.
  • the structure of the second auxiliary electrode 572 is the same and will not be described herein.
  • the auxiliary electrode 501 can also reduce the impedance of the scanning line 511, thereby improving the picture quality of the liquid crystal display device.
  • the auxiliary electrode 501 When the auxiliary electrode 501 is disposed only under the data line 571, the auxiliary electrode 501 is formed of a first metal layer, the auxiliary electrode 501 is disposed below the data line 571, and the auxiliary electrode 501 is disposed along the extending direction of the data line 571. Between the scan line 511 and the common electrode 512. The auxiliary electrode 501 is connected to the data line 571 through the second via hole 58 penetrating the first insulating layer 52 and the second insulating layer 55.
  • the structure of the specific auxiliary electrode 501 is the same as that of the first auxiliary electrode 513 described above, and details are not described herein again.
  • the auxiliary electrode 501 can also reduce the impedance of the scanning line 571, thereby improving the picture quality of the liquid crystal display device.
  • the present invention further provides a liquid crystal display device comprising the array substrate of any of the embodiments shown in FIGS. 4-7.
  • FIG. 8 is a flow chart of an embodiment of a method for fabricating an array substrate according to the present invention
  • FIG. 9 is a schematic diagram of a five-mask process of the array substrate shown in FIG.
  • a method for fabricating an array substrate of the present invention includes the following steps:
  • Step S10 providing a substrate
  • Step S11 disposing a first metal layer on the substrate to form a scan line, a gate of the thin film transistor, and a common electrode;
  • Step S12 providing a first insulating layer on the first metal layer
  • Step S13 providing a transparent conductive layer on the first insulating layer for forming a source, a drain, and a pixel electrode of the thin film transistor, and a drain of the thin film transistor is connected to the pixel electrode;
  • Step S14 providing a second insulating layer on the transparent conductive layer, and providing a first via hole at a position corresponding to the source of the thin film transistor of the second insulating layer;
  • Step S15 disposing a second metal layer on the second insulating layer to form a data line, and the data line is connected to the source of the thin film transistor through the first via hole.
  • a clean, smooth surface glass is provided as the substrate 50 of the array substrate.
  • Main elements such as scanning lines, data lines, pixel electrodes, and thin film transistors are formed on the substrate 50 by performing processes such as plating, etching, and the like on the substrate 50.
  • a first metal layer 51 is disposed on the substrate 50, and the first metal layer 51 is etched to form a gate 510 of the thin film transistor and a scan line 511 (shown in FIG. 4) and a common electrode 512. .
  • the gate 510 of the thin film transistor and the scan line 511 are electrically connected to each other (the connection relationship is not shown) to provide a scan signal to the gate 510 of the thin film transistor through the scan line 511 in a subsequent process.
  • step S12 after the gate electrode 510 of the thin film transistor, the scanning line 511, and the common electrode 512 are formed, the first insulating layer 52 is formed on the gate electrode 510 and the common electrode 512 of the thin film transistor.
  • a semiconductor layer 53 is formed on the first insulating layer 52 corresponding to the gate 510 of the thin film transistor.
  • a transparent conductive layer 54 is disposed on the first insulating layer 52, and the transparent conductive layer 54 is etched to form a source 541, a drain 542, and a pixel electrode 543 of the thin film transistor.
  • the common electrode 512 and the gate 510 of the thin film transistor and the transparent conductive layer 54 are electrically insulated by the first insulating layer 52.
  • the drain electrode 542 of the thin film transistor is connected to the pixel electrode 543 to input a data signal to the pixel electrode 543 through the drain 542 for display in a subsequent process.
  • the source electrode 541 and the drain electrode 542 of the thin film transistor are connected to the semiconductor layer 53, respectively. Among them, the semiconductor layer 53 functions as a switch for the thin film transistor. specifically:
  • the gate 510 of the thin film transistor serves as a control electrode.
  • the scan line 511 supplies a scan signal to the gate 510 of the thin film transistor
  • the semiconductor layer 53 is turned on to turn on the thin film transistor, and the source 541 is used as an input electrode of the thin film transistor.
  • the drain electrode 542 as an output electrode is electrically connected through the semiconductor layer 53; when the gate signal 510 of the thin film transistor is not input with the scan signal, the semiconductor layer 53 is not turned on, so that the thin film transistor is turned off, the source electrode 541 and the drain electrode 542 Electrical insulation.
  • the second insulating layer 55 is disposed on the transparent conductive layer 54.
  • the second insulating layer 55 may be a passivation layer or may be insulated.
  • the insulating layer of the characteristic is not specifically limited herein.
  • the source electrode 541 of the thin film transistor is covered with the second insulating layer 55, and the source electrode 541 serves as an input electrode of the thin film transistor, and it is necessary to input a desired data signal thereto. Therefore, the second insulating layer 55 is dry etched to form the first via hole 56, wherein the first via hole 56 is disposed at a position where the second insulating layer 55 corresponds to the source 541 of the thin film transistor, to facilitate A data signal is input to the source 541.
  • dry etching refers to a technique of performing plasma etching using plasma.
  • the second insulating layer 55 is physically bombarded and chemically reacted by reactive ions in a dry etching manner by reactive ion etching to form a first guide of the source 541 of the corresponding thin film transistor on the second insulating layer 55.
  • Through hole 56 the second insulating layer 55 may also be etched by a dry etching method using physical etching or chemical etching to form the first via hole 56, which is not specifically limited.
  • step S15 a second metal layer 57 is disposed on the second insulating layer 55, and the second metal layer 57 is etched to form a data line 571, and the data line 571 passes through the first via 56 and the source of the thin film transistor.
  • the pole 541 is connected.
  • the scan line 511, the data line 571, the common electrode 512, and the pixel electrode 543 are formed on the substrate 50, and the formed semiconductor layer 53, gate 510, source 541, and drain 542 constitute the substrate. 50 required thin film transistors.
  • the scan line 511 inputs a scan signal to the gate 510 of the thin film transistor
  • the semiconductor layer 53 is turned on
  • the thin film transistor is turned on
  • the source electrode 541 and the drain electrode 542 of the thin film transistor are turned on
  • the data line 571 is turned to the thin film through the via hole 56.
  • the source 541 of the transistor inputs a data signal
  • the data signal is output from the drain 542 to the pixel electrode 543.
  • an auxiliary electrode is further provided, which is formed by at least one of the first metal layer 51 and the second metal layer 57.
  • the specific settings of the auxiliary electrode are divided into the following three cases:
  • the first case is: only reduce the impedance of the data line;
  • the second case is: only reduce the impedance of the scan line
  • the third case is to simultaneously reduce the impedance of the scan lines and data lines.
  • the auxiliary electrode 501 is formed by the first metal layer 51, and when the scanning line 511 is formed in step S11, the auxiliary electrode 501 is further disposed under the data line 571, and the auxiliary electrode 501 is further disposed.
  • the auxiliary electrode 501 is disposed between the scanning line 511 and the common electrode 512 along the extending direction of the data line 571.
  • at least two second conductive openings 58 are further disposed above the auxiliary electrode 501, and the second conductive vias 58 penetrate the first insulating layer 52 and the second insulating layer.
  • the layer 55 and the auxiliary electrode 501 are connected to the data line 571 through the second via 58.
  • the data signal in addition to the data line 571 transmitting the data signal, in the region where the auxiliary electrode 501 is disposed, the data signal is commonly transmitted by the auxiliary electrode 501 and the data line 571, widening the path of the data signal transmission, and reducing The impedance of the data line 571 is reduced.
  • the auxiliary electrode 501 is formed of the second metal layer 57, and after the setting of the second insulating layer 55 is completed in step S14, further on the scanning line 511 At least two third via holes 59 are formed above, and the third via holes 59 penetrate the first insulating layer 52 and the second insulating layer 55. Then, the auxiliary electrode 501 is further disposed above the scan line 511, and the auxiliary electrode 501 is disposed between the two adjacent data lines 571 along the extending direction of the scan line 511, and is connected to the auxiliary electrode 501 through the third via hole 59. Scan line 511.
  • the scanning signal in addition to the scanning line 511 transmitting the scanning signal, in the region where the auxiliary electrode 501 is disposed, the scanning signal is commonly transmitted by the auxiliary electrode 501 and the scanning line 511, broadening the path of the scanning signal transmission, and The impedance of the scan line 511 is reduced.
  • the auxiliary electrode 501 includes a first auxiliary electrode 513 and a second auxiliary electrode 572, wherein the first auxiliary electrode 513 is formed by the first metal layer 51 and the second auxiliary electrode 572 is formed by the second A metal layer 57 is formed.
  • the first auxiliary electrode 513 is disposed under the data line 571, and the first auxiliary electrode 513 is disposed between the scan line 511 and the common electrode 512 along the extending direction of the data line 571. And the first auxiliary electrode 513 and the data line 571 are connected by the second via hole 58 penetrating the first insulating layer 52 and the second insulating layer 55.
  • the specific setting steps are the same as those of the auxiliary electrode 501 described above in the first case, and are not described herein again.
  • the second auxiliary electrode 572 is disposed above the scan line 511, and the second auxiliary electrode 572 is disposed between the two adjacent data lines 571 along the extending direction of the scan line 511. And the second auxiliary electrode 572 and the scan line 511 are connected by the third via hole 59 penetrating the first insulating layer 52 and the second insulating layer 55.
  • the specific setting steps are the same as those of the auxiliary electrode 501 described above in the second case, and are not described herein again.
  • the present invention provides an auxiliary electrode by above the scanning line and/or below the data line, and the material of the auxiliary electrode is formed with at least one of the scanning line or the data line. Therefore, in the scanning signal or the data signal transmission process, the auxiliary electrode is used for transmission, thereby reducing the impedance of the scanning line and/or the data line, thereby improving the picture quality of the liquid crystal display device.

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Description

液晶显示装置、阵列基板及其制作方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种液晶显示装置、阵列基板及其制作方法。
【背景技术】
液晶显示面板的制作过程一般分为阵列（Array）制程、组立（Cell）制程以及模组（Module）制程。其中，阵列制程主要是产生薄膜晶体管玻璃基板（也称为阵列基板），其作为液晶显示面板制作过程的第一道工序，所产生的薄膜晶体管玻璃基板的好坏对后续制程有着重大影响，甚至决定液晶显示面板的好坏。
阵列制程分为五道光罩制程(5PEP)，请一并参考图1与图2，图1为现有技术阵列基板的画素布局(Layout)结构示意图，图2为沿着图1所示的阵列基板的A-B线切割的剖面图。现有技术的五道制程首先由第一金属层(M1)11形成薄膜晶体管140的删极(Gate)110、扫瞄线(Gate Line or Scan Line)111和公共电极120；然后在第一金属层11上形成第一绝缘层（Isolator Layer）12，并在用于形成薄膜晶体管140的栅极110的第一金属层11所对应的第一绝缘层12上形成一层半导体层13；继而在第一绝缘层12以及半导体层13上形成第二金属层14，用于形成数据线141、薄膜晶体管140的源极142和漏极143；并在第二金属层14以及第一绝缘层12上形成第二绝缘层15；最后在第二绝缘层15上形成透明导电层16，用于形成画素电极(Pixel Electrode，简称PE)161。
目前，随着对具有高驱动频率(Frame rate)或解析度(Resolution)的液晶显示装置的画面品质的要求越来越高，因此必须减小扫瞄线111与数据线141的阻抗。
请参阅图3，图3是现有技术中减小扫描线和数据线阻抗的阵列基板的画素布局结构示意图，其中，图3是在图1和图2所示的阵列基板的基础上进行改进，以达到减小扫瞄线110与数据线141阻抗的目的。如图3所示，图3是在图1所示的第一金属层11形成的扫瞄线110的局部区域增加了第二金属层14，以此加快扫描线110传递扫描信号的能力，并透过导通孔(VIA)17与透明导电层16形成的像素电极161将扫描信号在第一金属层11与第二金属层14间进行切换。同理，图3在图1所示的第二金属14形成的数据线141的局部区域增加了第一金属层11，以此加快数据线141传递数据信号的能力，并透过导通孔17与透明导电层16形成的像素电极161将数据线信号在第一金属层11与第二金属层14间进行切换。
使用图3所示的画素布局方式的确可在不增加成本的情况下达到减小扫描线和数据线阻抗的目的，但需要透过导通孔17与透明导电层16才能将扫描信号或数据信号在其各自对应的第一金属层与第二金属层间切换。而透明导电层16具有较高阻值且透明导电层16与第一金属层11或第二金属层14之间的介面电阻较大。
因此，使用图3所示的结构来减小扫描线和数据线阻抗的效果并不佳，进一步的，在像素电极上大量增加的导通孔结构会减小像素电极的开口率与亮度，反而会影响液晶显示装置的画面品质。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示装置、阵列基板及其制作方法，能够减小扫描线和数据线的阻抗，从而提高液晶显示装置的画面品质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，该阵列基板包括：基底；第一金属层，设置在基底上，用以形成扫描线、薄膜晶体管的栅极以及公共电极；第一绝缘层，设置在第一金属层上；透明导电层，设置在第一绝缘层上，用以形成薄膜晶体管的源极、漏极以及像素电极，且像素电极与薄膜晶体管的漏极连接；第二绝缘层，设置在透明导电层上，第二绝缘层在对应于薄膜晶体管的源极的位置处设置有第一导通孔；第二金属层，设置在第二绝缘层上，用以形成数据线，数据线通过第一导通孔与薄膜晶体管的源极连接；其中，阵列基板进一步包括辅助电极，辅助电极由第一金属层和第二金属层中的至少之一者形成，辅助电极由第一金属层形成，辅助电极通过穿透第一绝缘层和第二绝缘层的第二导通孔与数据线连接，用以减小数据线的阻抗，辅助电极对应设置在数据线的下方，且辅助电极沿着数据线的延伸方向设置在扫描线和公共电极之间；辅助电极由第二金属层形成，辅助电极通过穿越第一绝缘层和第二绝缘层的第三导通孔与扫描线连接，用以减小扫描线的阻抗，辅助电极对应设置在扫描线的上方，且辅助电极沿着扫描线的延伸方向设置在两相邻的数据线之间。
其中，辅助电极包括第一辅助电极以及第二辅助电极，第一辅助电极由第一金属层形成，第二辅助电极由第二金属层形成，其中：
第一辅助电极通过穿透第一绝缘层和第二绝缘层的第二导通孔与数据线连接，用以减小数据线的阻抗，第一辅助电极对应设置在数据线的下方，且第一辅助电极沿着数据线的延伸方向设置在扫描线和公共电极之间；
第二辅助电极通过穿越第一绝缘层和第二绝缘层的第三导通孔与扫描线连接，用以减小扫描线的阻抗，第二辅助电极对应设置在扫描线的上方，且第二辅助电极沿着扫描线的延伸方向设置在两相邻的数据线之间。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，其包括一阵列基板，该阵列基板包括：基底；第一金属层，设置在基底上，用以形成扫描线、薄膜晶体管的栅极以及公共电极；第一绝缘层，设置在第一金属层上；透明导电层，设置在第一绝缘层上，用以形成薄膜晶体管的源极、漏极以及像素电极，且像素电极与薄膜晶体管的漏极连接；第二绝缘层，设置在透明导电层上，第二绝缘层在对应于薄膜晶体管的源极的位置处设置有第一导通孔；第二金属层，设置在第二绝缘层上，用以形成数据线，数据线通过第一导通孔与薄膜晶体管的源极连接；其中，阵列基板进一步包括辅助电极，辅助电极由第一金属层和第二金属层中的至少之一者形成，以减小扫描线和/或数据线的阻抗。
其中，辅助电极由第一金属层形成，辅助电极通过穿透第一绝缘层和第二绝缘层的第二导通孔与数据线连接，用以减小数据线的阻抗，辅助电极对应设置在数据线的下方，且辅助电极沿着数据线的延伸方向设置在扫描线和公共电极之间。
其中，辅助电极由第二金属层形成，辅助电极通过穿越第一绝缘层和第二绝缘层的第三导通孔与扫描线连接，用以减小扫描线的阻抗，辅助电极对应设置在扫描线的上方，且辅助电极沿着扫描线的延伸方向设置在两相邻的数据线之间。
其中，辅助电极包括第一辅助电极以及第二辅助电极，第一辅助电极由第一金属层形成，第二辅助电极由第二金属层形成，其中：
第一辅助电极通过穿透第一绝缘层和第二绝缘层的第二导通孔与数据线连接，用以减小数据线的阻抗，第一辅助电极对应设置在数据线的下方，且第一辅助电极沿着数据线的延伸方向设置在扫描线和公共电极之间；
第二辅助电极通过穿越第一绝缘层和第二绝缘层的第三导通孔与扫描线连接，用以减小扫描线的阻抗，第二辅助电极对应设置在扫描线的上方，且第二辅助电极沿着扫描线的延伸方向设置在两相邻的数据线之间。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制作方法，该制作方法包括：提供一基底；在基底上设置第一金属层，用以形成扫描线、薄膜晶体管的栅极以及公共电极；在第一金属层上设置第一绝缘层；在第一绝缘层上设置透明导电层，用以形成薄膜晶体管的源极、漏极以及像素电极，薄膜晶体管的漏极与像素电极连接；在透明导电层上设置第二绝缘层，并且在第二绝缘层对应于薄膜晶体管的源极的位置处设置有第一导通孔；在第二绝缘层上设置第二金属层，用以形成数据线，数据线通过第一导通孔与薄膜晶体管的源极连接；其中，进一步设置辅助电极，辅助电极由第一金属层和第二金属层中的至少之一者形成，以减小扫描线和/或数据线的阻抗。
其中，在第一金属层上设置第一绝缘层的步骤包括：
在薄膜晶体管的栅极对应的第一绝缘层上形成一半导体层，其中，薄膜晶体管的源极和漏极分别与半导体层连接。
其中，辅助电极由第一金属层形成，在数据线的下方设置辅助电极，且辅助电极沿着数据线的延伸方向设置在扫描线和公共电极之间，通过穿透第一绝缘层和第二绝缘层的第二导通孔连接辅助电极与数据线。
其中，辅助电极由第二金属层形成，在扫描线的上方设置辅助电极，且辅助电极沿着扫描线的延伸方向设置在两相邻的数据线之间，通过穿透第一绝缘层和第二绝缘层的第三导通孔连接辅助电极与扫描线。
其中，辅助电极包括第一辅助电极以及第二辅助电极，第一辅助电极由第一金属层形成，第二辅助电极由第二金属层形成，其中：
在数据线的下方设置第一辅助电极，且第一辅助电极沿着数据线的延伸方向设置在扫描线和公共电极之间，通过穿透第一绝缘层和第二绝缘层的第二导通孔连接第一辅助电极与数据线；
在扫描线的上方设置第二辅助电极，且第二辅助电极沿着扫描线的延伸方向设置在两相邻的数据线之间，通过穿透第一绝缘层和第二绝缘层的第三导通孔连接第二辅助电极与扫描线。
本发明的有益效果是：区别于现有技术的情况，本发明通过设置辅助电极，并且该辅助电极由制作扫描线和数据线的第一金属层和第二金属层中的至少之一者形成，使得在传输扫描信号或者数据信号时，扫描信号或者数据信号由辅助电极以及扫描线或者辅助电极以及数据线共同传输，因此，扩宽了信号传输的路径，从而减小了数据线或者扫描线的阻抗，从而提高液晶显示装置的画面品质。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术阵列基板的画素布局结构示意图；
图2是沿着图1所示的阵列基板的A-B线切割的剖面图；
图3是现有技术中减小扫描线和数据线阻抗的阵列基板的画素布局结构示意图；
图4是本发明一种阵列基板的画素布局结构示意图；
图5是图4所示的阵列基板沿着E-F虚线切割的剖面图；
图6是图4所示的阵列基板沿着A-B虚线切割的剖面图；
图7是图4所示的阵列基板沿着C-D虚线切割的剖面图；
图8是本发明阵列基板的制作方法实施例的流程图；
图9是图8的阵列基板的五道光罩制程的示意图。
【具体实施方式】
请一并参阅图4和图5，图4是本发明一种阵列基板的画素布局结构示意图；图5是图4所示的阵列基板沿着E-F虚线切割的剖面图。首先请参阅图4，图4只显示了阵列基板500的基底50上的一个画素布局结构，如图4所示，该画素布局结构由平行设置的两条扫描线511、平行设置的两条数据线571、薄膜晶体管540、公共电极512以及像素电极543组成。
本实施例中，两条扫描线511分别和两条数据线571垂直，以形成一长方形区域，并在该长方形区域内设置像素电极543。其中，扫描线511连接薄膜晶体管540的栅极510，数据线571连接薄膜晶体管540的源极541，并且薄膜晶体管540的漏极542连接像素电极543。其中，在两扫描线511之间并在像素电极543的下方设置公共电极512，公共电极512与像素电极543之间形成一电容结构。其中，阵列基板500中各元件的具体位置请参阅图5。
如图5所示，阵列基板500包括基底50、第一金属层51、第一绝缘层52、透明导电层54、第二绝缘层55以及第二金属层57。
其中，第一金属层51设置在基底50上，用以形成薄膜晶体管540的栅极510、扫描线511（如图4所示）以及公共电极512。第一绝缘层52设置在第一金属层51上。透明导电层54设置在第一绝缘层52上，其中，透明导电层54用以形成薄膜晶体管540的源极541、漏极542以及像素电极543，且像素电极543与薄膜晶体管540的漏极542连接。第二绝缘层55设置在透明导电层54上，并且第二绝缘层55在对应于薄膜晶体管540的源极541的位置处设置有第一导通孔56。第二金属层57设置在对应于薄膜晶体管540的源极541的第二绝缘层55上，并且第二金属层57用以形成数据线571。其中，数据线571通过第一导通孔56与薄膜晶体管540的源极541连接。
本实施例中，在薄膜晶体管540的栅极510对应的第一绝缘层52上进一步设置一半导体层53，并且半导体层53与源极541以及漏极542连接，其中，半导体层53对薄膜晶体管540起到开关的作用。具体地：
薄膜晶体管540的栅极510作为控制电极，当扫描线511向薄膜晶体管540的栅极510提供扫描信号时，半导体层53导通，使薄膜晶体管540处于导通状态，作为薄膜晶体管540的输入电极的源极541和作为输出电极的漏极542通过半导体层53电性连接；当薄膜晶体管540的栅极510没有输入扫描信号时，半导体层53不导通，使薄膜晶体管540处于关闭状态，源极541和漏极542电性绝缘。
进一步的，为了提高液晶显示装置的画面品质，必须减小扫描线511和/或数据线571的阻抗。请一并参考图4、图6和图7，本实施例中，阵列基板50进一步包括辅助电极501，并且该辅助电极501由第一金属层和第二金属层中的至少之一者形成。
图6是图4所示的阵列基板沿着A-B虚线切割的剖面图；图7是图4所示的阵列基板沿着C-D虚线切割的剖面图。请先参阅图4，辅助电极501（图6所示）包括第一辅助电极513，并且第一辅助电极513设置在扫描线511和公共电极512之间并对应于数据线571的下方。其中，第一辅助电极513的具体结构请参阅图6。
如图6所示，第一辅助电极513对应设置在数据线571的下方，具体为第一辅助电极513设置在第一绝缘层52的下方，且第一辅助电极513沿着数据线571的延伸方向设置在扫描线511和公共电极512之间，并且通过穿透第一绝缘层52和第二绝缘层55的第二导通孔58与数据线571连接。本实施例中，第一辅助电极513优选由第一金属层形成，以此可以减小材料的成本。
因此，在数据信号传导的过程，数据信号除了在数据线571中传递外，在设置有第一辅助电极513的区域，可透过导通孔58将数据线571的数据信号输送到第一辅助电极513进行传递。以此拓宽了数据信号传导的路径。因此减小了数据线571的阻抗，从而提高液晶显示装置的画面品质。
请再参阅图4，同理，在扫描线511的上方设置辅助电极501能够减小扫描线511的阻抗，从而提高液晶显示装置的画面品质。因此，辅助电极501进一步包括第二辅助电极572，其中，第二辅助电极572的具体结构请参阅图7。
如图7所示，第二辅助电极572设置在扫描线511的上方，具体为第二辅助电极572设置在第二绝缘层55的上，且第二辅助电极572沿着扫描线511的延伸方向设置在两相邻的数据线571之间。并且第二辅助电极572通过穿透第一绝缘层52和第二绝缘层55的第三导通孔59与扫描线511连接。本实施例中，第二辅助电极572优选由第二金属层形成，以此可以减小材料的成本。
因此，在扫描信号传导的过程，扫描信号除了在扫描线511中传递外，在设置有第二辅助电极572的区域，可透过第三导通孔59将扫描线511的扫描信号输送到第二辅助电极572进行传递。以此拓宽了扫描信号传导的路径。因此减小了扫描线511的阻抗，从而提高了液晶显示装置的画面品质。
承前所述，在扫描线511的上方设置第二辅助电极572以及在数据线571的下方设置第一辅助电极513能够减小扫描线511以及数据线571的阻抗，从而提高液晶显示装置的画面品质。
在其他优选实施例中，考虑到成本的问题，也可以只在扫描线511的上方设置辅助电极501，或者只在数据线571的下方设置辅助电极501。
当只在扫描线511的上方设置辅助电极501时，辅助电极501由第二金属层形成，辅助电极501对应设置在扫描线511的上方，且辅助电极501沿着扫描线511的延伸方向设置在两相邻的数据线571之间，辅助电极501通过穿透第一绝缘层52和第二绝缘层55的第三导通孔59与扫描线511连接，具体的辅助电极501的结构与上述所述的第二辅助电极572的结构相同，在此不再赘述。同理，辅助电极501也可以减小扫描线511的阻抗，从而提高液晶显示装置的画面品质。
当只在数据线571的下方设置辅助电极501时，辅助电极501由第一金属层形成，辅助电极501对应设置在数据线571的下方，且辅助电极501沿着数据线571的延伸方向设置在扫描线511和公共电极512之间。辅助电极501通过穿透第一绝缘层52和第二绝缘层55的第二导通孔58与数据线571连接。具体的辅助电极501的结构与上述所述的第一辅助电极513的结构相同，在此不再赘述。同理，辅助电极501也可以减小扫描线571的阻抗，从而提高液晶显示装置的画面品质。
本发明更提供了一种液晶显示装置，其中，该液晶显示装置包括图4-图7所示的任一实施例的阵列基板。
请一并参阅图8和图9，图8是本发明阵列基板的制作方法实施例的流程图；图9是图8所示的阵列基板的五道光罩制程的示意图。首先参阅图8，本发明阵列基板的制作方法包括以下步骤：
步骤S10：提供一基底；
步骤S11：在基底上设置第一金属层，用以形成扫描线、薄膜晶体管的栅极以及公共电极；
步骤S12：在第一金属层上设置第一绝缘层；
步骤S13：在第一绝缘层上设置透明导电层，用以形成薄膜晶体管的源极、漏极以及像素电极，薄膜晶体管的漏极与像素电极连接；
步骤S14：在透明导电层上设置第二绝缘层，并且在第二绝缘层对应于薄膜晶体管的源极的位置处设置有第一导通孔；
步骤S15：在第二绝缘层上设置第二金属层，用以形成数据线，数据线通过第一导通孔与薄膜晶体管的源极连接。
请一起参阅图9，在步骤S10中，提供一块干净的、表面平滑的玻璃作为阵列基板的基底50。通过在基底50上进行镀膜、蚀刻等工艺，从而在基底50上形成扫描线、数据线、像素电极和薄膜晶体管等主要元件。
在步骤S11中，在基底50上设置第一金属层51，并对第一金属层51进行刻蚀，以形成薄膜晶体管的栅极510和扫描线511（如图4所示）以及公共电极512。其中，薄膜晶体管的栅极510和扫描线511相互电连接（图中未示连接关系），以在后续制程中通过扫描线511向薄膜晶体管的栅极510提供扫描信号。
在步骤S12中，在形成薄膜晶体管的栅极510、扫描线511以及公共电极512后，在薄膜晶体管的栅极510和公共电极512上形成第一绝缘层52。
进一步的，在形成第一绝缘层52后，在薄膜晶体管的栅极510对应的第一绝缘层52上形成一半导体层53。
在步骤S13中，在第一绝缘层52上设置透明导电层54，并对透明导电层54进行刻蚀，以形成薄膜晶体管的源极541、漏极542以及像素电极543。其中，公共电极512和薄膜晶体管的栅极510与透明导电层54之间通过第一绝缘层52电性绝缘。薄膜晶体管的漏极542与像素电极543连接，以在后续制程中通过漏极542向像素电极543输入数据信号进行显示。薄膜晶体管的源极541和漏极542分别与半导体层53连接。其中，半导体层53对薄膜晶体管起到开关的作用。具体地：
薄膜晶体管的栅极510作为控制电极，当扫描线511向薄膜晶体管的栅极510提供扫描信号时，半导体层53导通，使薄膜晶体管处于导通状态，作为薄膜晶体管的输入电极的源极541和作为输出电极的漏极542通过半导体层53电性连接；当薄膜晶体管的栅极510没有输入扫描信号时，半导体层53不导通，使薄膜晶体管处于关闭状态，源极541和漏极542电性绝缘。
在步骤S14中，在完成透明导电层54的设置后，在透明导电层54上设置第二绝缘层55，本实施例中，第二绝缘层55可以是钝化层，也可以是其他具有绝缘特性的绝缘层，在此不做具体限制。
此时，薄膜晶体管的源极541覆上了第二绝缘层55，而源极541作为薄膜晶体管的输入电极，需要对其输入所需的数据信号。因此，需对第二绝缘层55进行干蚀刻以形成第一导通孔56，其中，第一导通孔56设置在第二绝缘层55对应于薄膜晶体管的源极541的位置处，以方便对源极541输入数据信号。
其中，干蚀刻是指利用等离子进行薄膜刻蚀的技术。本实施例中，采用反应离子刻蚀的干蚀刻方式通过活性离子对第二绝缘层55进行物理轰击和化学反应，以在第二绝缘层55上形成对应薄膜晶体管的源极541的第一导通孔56。而在本发明的备选实施例中，也可以利用物理性蚀刻或化学性蚀刻的干蚀刻方式对第二绝缘层55进行蚀刻以形成第一导通孔56，在此不进行具体限制。
在步骤S15中，在第二绝缘层55上设置第二金属层57，并对第二金属层57进行刻蚀以形成数据线571，数据线571通过第一导通孔56与薄膜晶体管的源极541连接。
经过上述步骤后，基底50上已形成了扫描线511、数据线571、公共电极512以及像素电极543，而所形成的半导体层53、栅极510、源极541以及漏极542则构成了基底50所需的薄膜晶体管。在扫描线511向薄膜晶体管的栅极510输入扫描信号时，半导体层53导通，使薄膜晶体管打开，薄膜晶体管的源极541和漏极542接通，数据线571通过导通孔56向薄膜晶体管的源极541输入数据信号，数据信号从漏极542输出至像素电极543。
进一步的，为了提高液晶显示装置的画面品质，必须减小扫描线511和/或数据线571的阻抗。因此，本实施例中，进一步设置辅助电极，该辅助电极由第一金属层51和第二金属层57中的至少之一者形成。其中，辅助电极的具体设置分为以下三种情况：
第一种情况是：只减小数据线的阻抗；
第二种情况是：只减小扫描线的阻抗；
第三种情况是：同时减小扫描线和数据线的阻抗。
其中，第一种情况时请一并参考图6，辅助电极501由第一金属层51形成，并且在步骤S11中形成扫描线511时，在数据线571的下方进一步设置辅助电极501，且该辅助电极501沿着数据线571的延伸方向设置在扫描线511和公共电极512之间。并在步骤S14中完成第二绝缘层55的设置后，进一步在辅助电极501的上方设置至少两个第二导通58，该第二导通孔58穿透第一绝缘层52和第二绝缘层55，并且辅助电极501通过第二导通孔58与数据线571连接。
因此，在数据信号传递过程中，除了数据线571传递数据信号外，在设置有辅助电极501的区域，数据信号由辅助电极501以及数据线571共同传递，拓宽了数据信号传递的路径，并且减小了数据线571的阻抗。
当辅助电极501的设置属于第二种情况时请一起参阅图7，辅助电极501由第二金属层57形成，并且在步骤S14中完成第二绝缘层55的设置后，进一步在扫描线511的上方设置至少两个第三导通孔59，第三导通孔59穿透第一绝缘层52和第二绝缘层55。然后继续在扫描线511的上方设置辅助电极501，且辅助电极501沿着扫描线511的延伸方向设置在两相邻的数据线571之间，并通过第三导通孔59连接辅助电极501与扫描线511。
同理，在扫描信号传递过程中，除了扫描线511传递扫描信号外，在设置有辅助电极501的区域，扫描信号由辅助电极501以及扫描线511共同传递，拓宽了扫描信号传递的路径，并且减小了扫描线511的阻抗。
当辅助电极501的设置是第三种情况 时请一并参阅图6和图7，辅助电极501包括第一辅助电极513以及第二辅助电极572，其中，第一辅助电极513由第一金属层51形成，第二辅助电极572由第二金属层57形成。
其中，第一辅助电极513设置在数据线571的下方，且第一辅助电极513沿着数据线571的延伸方向设置在扫描线511和公共电极512之间。并且通过穿透第一绝缘层52和第二绝缘层55的第二导通孔58连接第一辅助电极513与数据线571。具体的设置步骤与前文所述的辅助电极501是第一种情况时的相同，在此不再赘述。
其中，第二辅助电极572设置在扫描线511的上方，且第二辅助电极572沿着扫描线511的延伸方向设置在两相邻的数据线571之间。并且通过穿透第一绝缘层52和第二绝缘层55的第三导通孔59连接第二辅助电极572与扫描线511。具体的设置步骤与前文所述的辅助电极501是第二种情况时的相同，在此不再赘述。
综上所述，本发明通过在扫描线的上方和/或数据线的下方设置辅助电极，并且辅助电极的材质与扫描线或者数据线的至少之一形成。因此，在扫描信号或者数据信号传递过程中，利用辅助电极进行传递，以此减小扫描线和/或数据线的阻抗，从而提高的液晶显示装置的画面品质。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基底；
    第一金属层，设置在所述基底上，用以形成扫描线、薄膜晶体管的栅极以及公共电极；
    第一绝缘层，设置在所述第一金属层上；
    透明导电层，设置在所述第一绝缘层上，用以形成所述薄膜晶体管的源极、漏极以及像素电极，且所述像素电极与所述薄膜晶体管的漏极连接；
    第二绝缘层，设置在所述透明导电层上，所述第二绝缘层在对应于所述薄膜晶体管的所述源极的位置处设置有第一导通孔；
    第二金属层，设置在所述第二绝缘层上，用以形成数据线，所述数据线通过所述第一导通孔与所述薄膜晶体管的源极连接；
    其中，所述阵列基板进一步包括辅助电极，所述辅助电极由所述第一金属层和第二金属层中的至少之一者形成，所述辅助电极由所述第一金属层形成，所述辅助电极通过穿透所述第一绝缘层和所述第二绝缘层的第二导通孔与所述数据线连接，用以减小所述数据线的阻抗，所述辅助电极对应设置在所述数据线的下方，且所述辅助电极沿着所述数据线的延伸方向设置在所述扫描线和所述公共电极之间；所述辅助电极由所述第二金属层形成，所述辅助电极通过穿透所述第一绝缘层和所述第二绝缘层的第三导通孔与所述扫描线连接，用以减小所述扫描线的阻抗，所述辅助电极对应设置在所述扫描线的上方，且所述辅助电极沿着所述扫描线的延伸方向设置在两相邻的所述数据线之间。
  2. 根据权利要求1所述的阵列基板，其中，所述辅助电极包括第一辅助电极以及第二辅助电极，所述第一辅助电极由所述第一金属层形成，所述第二辅助电极由所述第二金属层形成，其中：
    所述第一辅助电极通过穿透所述第一绝缘层和所述第二绝缘层的第二导通孔与所述数据线连接，用以减小所述数据线的阻抗，所述第一辅助电极对应设置在所述数据线的下方，且所述第一辅助电极沿着所述数据线的延伸方向设置在所述扫描线和所述公共电极之间；
    所述第二辅助电极通过穿越所述第一绝缘层和所述第二绝缘层的第三导通孔与所述扫描线连接，用以减小所述扫描线的阻抗，所述第二辅助电极对应设置在所述扫描线的上方，且所述第二辅助电极沿着所述扫描线的延伸方向设置在两相邻的所述数据线之间。
  3. 一种液晶显示装置，其中，所述液晶显示装置包括一阵列基板，所述阵列基板包括：
    基底；
    第一金属层，设置在所述基底上，用以形成扫描线、薄膜晶体管的栅极以及公共电极；
    第一绝缘层，设置在所述第一金属层上；
    透明导电层，设置在所述第一绝缘层上，用以形成所述薄膜晶体管的源极、漏极以及像素电极，且所述像素电极与所述薄膜晶体管的漏极连接；
    第二绝缘层，设置在所述透明导电层上，所述第二绝缘层在对应于所述薄膜晶体管的所述源极的位置处设置有第一导通孔；
    第二金属层，设置在所述第二绝缘层上，用以形成数据线，所述数据线通过所述第一导通孔与所述薄膜晶体管的源极连接；
    其中，所述阵列基板进一步包括辅助电极，所述辅助电极由所述第一金属层和第二金属层中的至少之一者形成，以减小所述扫描线和/或所述数据线的阻抗。
  4. 根据权利要求3所述的液晶显示装置，其中，所述辅助电极由所述第一金属层形成，所述辅助电极通过穿透所述第一绝缘层和所述第二绝缘层的第二导通孔与所述数据线连接，用以减小所述数据线的阻抗，所述辅助电极对应设置在所述数据线的下方，且所述辅助电极沿着所述数据线的延伸方向设置在所述扫描线和所述公共电极之间。
  5. 根据权利要求3所述的液晶显示装置，其中，所述辅助电极由所述第二金属层形成，所述辅助电极通过穿透所述第一绝缘层和所述第二绝缘层的第三导通孔与所述扫描线连接，用以减小所述扫描线的阻抗，所述辅助电极对应设置在所述扫描线的上方，且所述辅助电极沿着所述扫描线的延伸方向设置在两相邻的所述数据线之间。
  6. 根据权利要求3所述的液晶显示装置，其中，所述辅助电极包括第一辅助电极以及第二辅助电极，所述第一辅助电极由所述第一金属层形成，所述第二辅助电极由所述第二金属层形成，其中：
    所述第一辅助电极通过穿透所述第一绝缘层和所述第二绝缘层的第二导通孔与所述数据线连接，用以减小所述数据线的阻抗，所述第一辅助电极对应设置在所述数据线的下方，且所述第一辅助电极沿着所述数据线的延伸方向设置在所述扫描线和所述公共电极之间；
    所述第二辅助电极通过穿越所述第一绝缘层和所述第二绝缘层的第三导通孔与所述扫描线连接，用以减小所述扫描线的阻抗，所述第二辅助电极对应设置在所述扫描线的上方，且所述第二辅助电极沿着所述扫描线的延伸方向设置在两相邻的所述数据线之间。
  7. 一种阵列基板的制作方法，其中，所述制作方法包括：
    提供一基底；
    在所述基底上设置第一金属层，用以形成扫描线、薄膜晶体管的栅极以及公共电极；
    在所述第一金属层上设置第一绝缘层；
    在所述第一绝缘层上设置透明导电层，用以形成所述薄膜晶体管的源极、漏极以及像素电极，所述薄膜晶体管的漏极与所述像素电极连接；
    在所述透明导电层上设置第二绝缘层，并且在所述第二绝缘层对应于所述薄膜晶体管的所述源极的位置处设置有第一导通孔；
    在所述第二绝缘层上设置第二金属层，用以形成数据线，所述数据线通过所述第一导通孔与所述薄膜晶体管的源极连接；
    其中，进一步设置辅助电极，所述辅助电极由所述第一金属层和所述第二金属层中的至少之一者形成，以减小所述扫描线和/或所述数据线的阻抗。
  8. 根据权利要求7所述的制作方法，其中，所述在所述第一金属层上设置第一绝缘层的步骤包括：
    在所述薄膜晶体管的栅极对应的所述第一绝缘层上形成一半导体层，其中，所述薄膜晶体管的源极和漏极分别与所述半导体层连接。
  9. 根据权利要求8所述的制作方法，其中，所述辅助电极由所述第一金属层形成，在所述数据线的下方设置所述辅助电极，且所述辅助电极沿着所述数据线的延伸方向设置在所述扫描线和所述公共电极之间，通过穿透所述第一绝缘层和所述第二绝缘层的第二导通孔连接所述辅助电极与所述数据线。
  10. 根据权利要求8所述的制作方法，其中，所述辅助电极由所述第二金属层形成，在所述扫描线的上方设置所述辅助电极，且所述辅助电极沿着所述扫描线的延伸方向设置在两相邻的所述数据线之间，通过穿透所述第一绝缘层和所述第二绝缘层的第三导通孔连接所述辅助电极与所述扫描线。
  11. 根据权利要求8所述的制作方法，其中，所述辅助电极包括第一辅助电极以及第二辅助电极，所述第一辅助电极由所述第一金属层形成，所述第二辅助电极由所述第二金属层形成，其中：
    在所述数据线的下方设置所述第一辅助电极，且所述第一辅助电极沿着所述数据线的延伸方向设置在所述扫描线和所述公共电极之间，通过穿透所述第一绝缘层和所述第二绝缘层的第二导通孔连接所述第一辅助电极与所述数据线；
    在所述扫描线的上方设置所述第二辅助电极，且所述第二辅助电极沿着所述扫描线的延伸方向设置在两相邻的所述数据线之间，通过穿透所述第一绝缘层和所述第二绝缘层的第三导通孔连接所述第二辅助电极与所述扫描线。
PCT/CN2012/079928 2012-08-01 2012-08-10 液晶显示装置、阵列基板及其制作方法 Ceased WO2014019252A1 (zh)

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CN106773401A (zh) * 2016-12-28 2017-05-31 深圳市华星光电技术有限公司 阵列基板的制作方法及阵列基板
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