Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/20—Electrodes
  • H10F77/206—Electrodes for devices having potential barriers
  • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
  • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F10/00—Individual photovoltaic cells, e.g. solar cells
  • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
  • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
  • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
  • H10F71/121—The active layers comprising only Group IV materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/30—Coatings
  • H10F77/306—Coatings for devices having potential barriers
  • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/547—Monocrystalline silicon PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the present disclosure relates in general to the fields of photo voltaics. More particularly, the present disclosure relates to the methods, architectures, and apparatus related to high- efficiency back-contact photovoltaic solar cells.
• back contact back junction solar cell architecture (Back Contact / Back Junction or BC/BJ) is capable of achieving very high conversion efficiencies.
• BC/BJ back contact back junction solar cell architecture
• existing back contact, back junction solar cells have patterned emitter junction and cell metallization layers which are formed on the non-sunnyside (backside) and the sunnyside (ironside) has no metallization in order to accomplish an unobstructed, maximum coupling of the sunlight.
• the emitter junction and highly doped base diffusion regions may be formed on the solar cell backside (non-sunny side) to provide contact to majority of the solar cell substrate volume which is base. Further, highly doped base diffusion regions are formed below base metal contact area to reduce contact recombination, and to reduce base metal contact resistance.
• base metal and emitter metal are often patterned and contained within the base and emitter diffusion areas, respectively, such that the base metal never runs on top of the emitter diffusion, even if it is separated by oxide.
• the nested metal approach This is henceforth, referred to as the nested metal approach, where the metal of each kind is nested within its respective diffusion.
• An advantage of the nested approach is that it provides immunity to shunting of the metal to the diffusion of the opposite polarity.
• a disadvantage is that that the minimum metal width of the base dictates the minimum base diffusion width, which in turn, renders the base diffusion to be a relatively larger fraction of the backside of the solar cell, causing a reduction in the emitter fraction and increased electrical shading.
• wafer or silicon absorber have a very high minority carrier lifetime (e.g., > lmillisecond range) to ensure that the minority carriers do not recombine in the base while under the base diffusion.
• the overall manufacturing cost of the solar cell increases due to the higher cost of the higher quality wafers.
• a back contact solar cell comprises a substrate having a light receiving frontside surface and a backside surface for forming patterned emitter and non-nested base regions. Interdigitated doped emitter and base regions are formed on a backside surface of a crystalline semiconductor substrate. A patterned electrically insulating layer stack comprising a combination of at least a doped layer and an undoped capping layer is formed on the patterned doped emitter and base regions.
• a contact metallization pattern is formed comprising emitter metallization electrodes contacting the emitter regions and non-nested base metallization electrodes contacting the base regions wherein the non-nested base metallization electrodes are allowed to go beyond the base regions to overlap at least a portion of said patterned insulator without causing electrical shunts in the solar cell.
• Fig. 1A is a diagram showing a top view of a solar cell backside showing a nested base design
• FIG. IB Fig. 1A is a diagram showing a top view of a solar cell backside showing a non-nested based design
• Fig. 2A is a diagram showing a top view of a solar cell backside showing a uniform distributed contiguous/non-nested base design
• Fig. 2B is a diagram showing a top view of a solar cell backside showing a uniform distributed selective non-contiguous/non-nested base design
• Fig. 3 A is a diagram showing a top view of a solar cell backside showing a uniform base pattern with parallel base design and Fig. 3A' is a corresponding screen print design for forming the pattern of Fig. 3 A;
• Fig. 3B is a diagram showing a top view solar cell backside showing of an alternative uniform base pattern with staggered base design and Fig. 3B' is a corresponding screen print design for forming the pattern of Fig. 3 A;
• Fig. 3C is a diagram showing a top view solar cell backside showing an alternative nonnested base pattern
• Fig. 4 is a diagram showing a top view of a solar cell backside of a non-nested base pattern highlighting exemplary dimensions
• Fig. 5 is a diagram showing a distributed emitter and base laser pattern
• Fig. 6A is a photograph showing selective emitter (SE) and base openings
• Fig. 6B is a photograph showing emitter and base contacts inside selective emitter (SE) and base openings;
• Fig. 7A is a diagram showing laser annealing damage in selective emitter openings
• Fig. 7B is a diagram showing laser annealing damage in selective base openings
• Fig. 7C is a diagram showing laser annealing damage in contacts in selective emitter openings
• Fig. 7D is a diagram showing laser annealing damage in contacts in selective base openings
• Fig. 8A is a photograph showing laser ablation spots before anneal
• Fig. 8B is a photograph showing laser ablation spots after anneal with a 30 nanoseconds
• Fig. 9 is a Minority Carrier Lifetime (MCL) map of a silicon substrate after oxide ablation, specifically showing MCL improvement obtained after laser annealing of ablation spots;
• Fig. 10A is a diagram of a multi-station substrate laser processing tool and Fig. 10B is a diagram of the tool of Fig. 10A holding multi-wafers;
• FIGs. 11 A through 1 II are cross-sectional diagrams showing a solar cell after processing steps during an amorphous silicon mask process flow
• Fig. 12 is a Minority Carrier Lifetime (MCL) map of a silicon substrate after oxide ablation, specifically showing MCL improvement obtained when amorphous silicon is used as a hard mask;
• MCL Minority Carrier Lifetime
• Fig. 13A is a general process flow for the formation of a back-contact back-junction solar cell
• Fig. 13B is a representative manufacturing process flow for forming a back- contact/back-junction cell.
• the disclosed subject matter provides various structures and manufacturing methods for high-efficiency back- junction/back contacted solar cells specifically using thin crystalline semiconductor absorbers such as monocrystalline silicon with the cell absorber layer (or substrate), preferably ranging in thickness from about less than one micron (1 ⁇ ) up to about one hundred microns (100 ⁇ ), and even more particularly ranging in thickness from about one micron (1 ⁇ ) to about fifty microns (50 ⁇ ).
• the cell structures and manufacturing methods provided also apply to thicker crystalline semiconductor substrates or absorbers, ranging in thickness from about 100 ⁇ to about 200 ⁇ (which also includes the thickness range for more conventional CZ or FZ wafer thicknesses).
• the crystalline solar cell substrates may be formed either using chemical-vapor-deposition (CVD) methods including epitaxial growth (such as atmospheric-pressure epitaxy) or other crystalline silicon material formation techniques
• kerfless slicing or exfoliation methods utilization proton implantation, metal-stress-induced exfoliation, or laser.
• Various embodiments of manufacturing methods as it pertains to all aspects of processing very thin crystalline semiconductor solar cell substrates may be extended to other types of materials and to wafer based approaches, including kerfless cleavage methods such as the implantation-assisted wafer cleavage methods.
• Key attributes of various cell embodiments provided include substantially reduced semiconductor (e.g, silicon) material consumption, very low manufacturing cost, high cell efficiency, and relatively high energy yield, thus, improved solar photovoltaic module performance.
• metallization layers one skilled in the art could apply the principles discussed herein to front contact cells, other fabrication materials including alternative semiconductor materials (such as gallium arsenide, germanium, multi-crystalline silicon, etc.), metallization layers comprising metallization stacks, technical areas, and/or embodiments without undue experimentation.
• novel doped region formation embodiments of this invention while applicable to any architecture such as front contacted, back-contact/back junction or even back contact/front junction solar cells, are specifically illustrated in this invention with respect to the back contact/back junction crystalline silicon architecture (hence forth, BC/BJ).
• Non-nested metal allows the heavy base diffusions to be smaller than the width of the base metal, while ensuring that there is no path for breaching the electrically insulator layer, such as oxide, between base metal and the underlying emitter. This is accomplished by ensuring that the dielectric stack separating base metal from the emitter diffusion is free of through-dielectric pin-holes, allowing a non-nested base metal design without causing electrical shunts. In a specific embodiment, this can be realized using several (e.g., at least two) APCVD deposited doped and undoped (capping) dielectric layers.
• silicon dioxide (Si02) layers typically silicon dioxide (Si02) layers, but may also include silicon nitride (SiNx) and/or amorphous silicon (a-Si), and/or aluminum oxide (A1203) layers (doped and/or undoped in each case).
• SiNx silicon nitride
• a-Si amorphous silicon
• A1203 aluminum oxide
• thermal oxide step can be added after, before, or in-between the APCVD dielectric layers to ensure that there are no shunting pinholes, (for more detail see U.S. Pat. App. No. 13/807,631 to which the application claims priority and is incorporated by reference in its entirety).
• the non-nested metallization design can be used either with contiguous base or noncontiguous (discrete base array) base diffusions.
• the base may be a series of straight lines (columns).
• the base metal overlaps with these diffusions, while not necessarily being contained inside the diffusions.
• these diffusions can be isolated islands which only surround where isolated base contacts are required.
• the diffusions can be circular, rectangular or other geometrical shapes, while connected by base metal line to each other.
• An advantage of non-contiguous base diffusions is that it can minimize the base resistance through silicon, while keeping the emitter fraction constant (at a relatively high level), for a given metal pitch.
• the reduction in the base diffusion area while allows a relaxed lifetime of the material for BC/B J cells, increases the distance between base diffusions for a given metal pitch, hence, causing a potential degradation of fill factor of the solar cell through increase in base resistance.
• the enabling embodiments of this invention relax these restrictions and facilitate design and fabrication of high efficiency solar cells.
• This invention allows the non-nested base design architecture to afford effectively lower base resistance through the greater flexibility of non contiguous selective/distributed base diffusion
• the base islands are isolated (discrete base islands), but co-linear (or arranged along columns) being connected by a single base metal line which connects to silicon base periodically through the base contacts inside the isolated base islands.
• this design will be non-nested as the connecting base metal line runs between isolated base diffusion islands, on top of the emitter areas (over the dielectric layer covering doped emitter regions).
• the success of the non-contiguous base pattern design is highly dependent on ability to run non-nested base metal without shunting it. This is ensured by the aforementioned process techniques.
• the distributed base islands under a given Base metal line has more than a single co-linear row (or column); can have two or multiple rows (or columns) with offset island positions.
• the general architecture provides flexibility for getting better electrical performance. The details of the structure and advantages of these noncontiguous schemes are outlined in the subsequent sections.
• a distributed, non-contiguous base diffusion (such as discrete base islands as shown U.S. Pat. App. No. 13/807,631 to which the application claims priority and which is again incorporated by reference in its entirety herein) and contact formation scheme, comprising of novel patterning and diffusion methods, in the context of non-nested metal architectures, where the base metal (defined as the metal contacting the base diffusion area) is free to run over emitter diffusion area (covered by the dielectric layer over the doped emitter regions) on top of a dielectric passivation layer (and vice-versa if desirable) in a robust, shunt-free, manner.
• the design can also be referred to as Spot in Spot (SIS).
• the name derives its origin from the fact that the isolated and non-contiguous contact spot is opened inside the non-contiguous base diffusion area.
• the doped dielectric films are patterned forming non contiguous areas of highly doped regions (n-type or p-type) of the same type as the relatively lightly doped base (n type or p-type).
• the non-contiguous (or discrete islands of) highly doped base structures are placed in a geometrically optimal fashion, while still under the base metal, so as to minimize their distance from each other, thus minimizing the diffusion resistance losses through the lightly doped base.
• the combination of these diffusion patterns and optimized diffusions with doped dielectric films can also serve as good electrical insulators to reduce the risk of electrical shorts or shunts between base and emitter regions of solar cells.
• the base metal is nested inside the base diffusion (specifically put in for contacting to the lightly doped base) to avoid cell shunting.
• This restriction of metallization nesting and the impact of the resulting design rules require a minimum base heavy diffusion area dictated by minimum base metal width. This in turn, reduces the emitter fraction and requires a costly, high lifetime wafer to ensure that the photo excited carriers do not recombine under the long base diffusions and are able to get to the emitter.
• Non nested base allows higher emitter fraction area on the backside, a desirable cell design attribute for achieving high cell efficiencies.
• Non-nesting of the metallization pattern and the resulting enhanced emitter area fraction lead to much less minority carrier recombination losses (as is highly desirable particularly with ultrathin cells with absorber thickness below about 100 microns, preferably below 80 microns, and/or large-area cells with cell area at least 125 mm x 125 mm and preferably 156 mm x 156 mm or larger).
• the non nested base metal is afforded by good dielectric insulation offered from dielectric layers.
• the cell design progression is based on the following constraints.
• the minimum Base and Emitter metal widths are first determined based on the desired metal line resistance requirements, and based on the available resolution of the method utilized to pattern the line width, with picoseconds or femptosecond laser ablation one method of direct patterning. For a given cell size (area) and the maximum thickness of the metal (constrained by cost and stress on to the absorber substrate), the minimum metal line width is determined. This is the case for the conventional single metal level metallization.
• the metal lines touching the cell contacts can be made even more resistive (because they carry electrical currents locally for short distances before they are extracted vertically through vias connected to the second level metal or metal-2 (M2), separated from metal- 1 (Ml) by an interlayer dielectric or electrically insulating backplane), yielding flexibility to go to smaller widths.
• M2 metal- 1
• the proposed non-nested approach overcomes the above constraint and allows a much larger emitter fraction. This results in lowering the lifetime requirement for equivalent efficiency performance, thus, reducing the substrate cost.
• the embodiments of this invention also enables back junction and back contacted architecture to be compatible with thinner substrates which may be grown with modest and not very demanding quality, i.e., not stringently high bulk lifetime without loss in performance.
• An example of this substrate is the epitaxially grown silicon on top of porous silicon which can yield bulk lifetimes in excess of 300 to 500 for n-type epitaxial silicon growth, but typically not in excess of 1 ms.
• Another example is to start with a relatively low lifetime (200 to 500 ⁇ ) CZ wafer and thin it down to between 5 ⁇ to 100 ⁇ in general, but preferably between 20 ⁇ to 80 ⁇ range.
• this invention not only reduces the cost of the conventional back contacted architectures (due to less demanding requirements for the silicon substrate quality), it is paramount for enabling very high efficiency back contact back junction thin mono-crystalline or multi-crystalline solar cells.
• Non-nested architecture can either have a contiguous or a non-contiguous (discrete islands of) base.
• the non-contiguous base also referred to as distributed base or discrete island base design
• dielectric is patterned to form the discrete base diffusion islands sporadically and non-continuously (akin to islands of base diffusion in a contiguous sea of emitter), thus, providing the flexibility of placing these diffusions and the ensuing contact at will according the needs of the high efficiency design.
• Noncontiguous scheme along with the non-nested base allows myriad design possibilities.
• BC/BJ cells are mostly covered with emitter regions on the backside (non sunny side) of the solar cell, with the base diffusion regions intertwined in the sea of emitter. With non-nested and non-contiguous base concept, all the emitter regions can remain continuous with much larger emitter fraction effectively increasing overall carrier collection efficiency of the solar cell.
• Non-nested and non-contiguous base design allows the possibility of increasing emitter fraction area by reducing the highly doped base diffusion areas needed to reduce contact recombination this helps minimize electrical shading without any penalty in diffusion resistances.
• Very thin (e.g., thinner than about 80 micron thick absorber layer) solar cells utilizing the methods and structures of this invention include ultrathin crystalline silicon solar cells with crystalline silicon absorber layers in the thickness range of a few microns to lO's of microns, formed by epitaxial lift-off, chemical etch based thinning of wafers (eg. CZ wafers of starting thickness between 130 microns to 200 microns), proton implant, stress-induced splitting, laser splitting, or other thin silicon slicing techniques.
• step 1 techniques such as atmospheric chemical vapor deposition (APCVD), or patterned screen printing can be used to deposit doped dielectric films. Care has to be taken to ensure that the choice of dielectric films and technique is suitable to ensure good optical quality and good contacts to both n and p-type diffusions in silicon.
• blanket deposition techniques such as APCVD (and/or plasma enhanced CVD)
• high temperature furnace anneal can be used to drive in the dopants. After deposition of the diffusion source dielectrics these films are preferably annealed at a relatively higher temperature (typically between 900°C and 1150°C) to drive the dopant into the silicon substrate. Furnace anneal is critical aspect of forming diffusions.
• dielectric material for base and emitter diffusion comprises of doped APCVD silicon oxide with at least one of the doped dielectric layer having a capping layer of undoped dielectric (p or n-type silicon oxide, referred to as Boron doped glass, BSG for p-type, or phosphorous doped glass, PSG for n-type); these layers are subsequently patterned using pulsed picoseconds (or pulsed femtoseconds) laser, which is able to remove oxide while stopping on silicon without causing significant ablation damage it.
• p or n-type silicon oxide referred to as Boron doped glass, BSG for p-type, or phosphorous doped glass, PSG for n-type
• the patterning of doped APCVD layer of one kind (such as BSG), followed by deposition of APCVD layer of the other dopant type (such as PSG), allows both types of doped layers (BSG and PSG) to be in contact with silicon at pre-specified patterned areas.
• These doped oxide layers serve as the source of Boron and Phosphorous which ultimately diffuses in silicon to form emitter and base diffusions, respectively.
• the fractional area of contact with silicon of each layer is determined by the pattern geometry.
• screen printed dopant paste/inks may be used for forming patterned diffusion.
• a key requirement for these dielectric layers is to electrically isolate absorber layer with diffusions from the metal layer. The metal layer should only contact the absorber where it is intended to do so by opening explicit contact holes.
• the choice of the dielectric material should be such that it is free of pinholes and is conducive to produce a good back mirror in conjunction with the cell metallization layer for optimal light absorption in the solar cell. Presence of pinholes is undesirable as it provide a shunting path for current between the non-nested base metal and the emitter.
• step 2 related to patterning methods for diffusions patterning can be done using blanket deposition followed by laser ablation or using standard lithography/etching techniques.
• the dielectric layer can also be directly patterned using an appropriate dopant paste or liquid using screen printing or stencil printing or inkjet printing (or aerosol jet printing).
• Conventional BC/BJ solar cells Fig 1 have interdigitated nested metal design where emitter and base metal lines are exclusively within the interdigitated emitter and base diffusions respectively.
• the key embodiment of this invention pertains to the formation of non-nested base diffusion patterns in both interdigitated and non-interdigitated emitter and base diffusions. As described in previous section the base diffusion can be either contiguous or non-contiguous.
• non-contiguous base can be utilized for a variety of purposes such as but not limited to reducing base diffusion resistance to gain fill factor, and reducing the base diffusion areas for improving electrical shading.
• contact holes are formed either by laser ablation or by using standard lithography and etch technique.
• Fig 3a, 3b and 3c Various designs within the aforementioned non-contiguous paradigm are shown in Fig 3a, 3b and 3c.
• the emitter fraction area is increased to reduce the current collection loss in the base diffusion areas through reduction in electrical shading.
• Pitch between the base diffusion and contact area percentage can be further optimized to get same diffusion resistance with better current collection ability.
• the design can be altered such as shown in fig 3b and 3 c to further reduce base diffusion resistance, while not compromising electrical shading. This design embodiment is especially advantageous for thin mono crystalline solar cells where fill factor is limited by high base resistances and/or where Front surface field may not be desirable or possible.
• step 3 related to metal deposition and patterning (or direct write deposition of the patterned metal layer)
• several methods can be deployed. This includes techniques such as metal sputtering or evaporation on top of the aforementioned dielectric layer.
• the deposited metal in turn, can be patterned and isolated to form base and emitter metal using techniques such as pico second based laser ablation.
• any of the several direct write techniques such as, but not limited to, screen printing, stencil printing, masked thermal (or arc or plasma) metal spray, inkjet or aerosol printing followed by anneal or activation step can be used to form base and emitter metal.
• the base and emitter pitch can be same, making the metal pattern symmetric for both emitter and base metal which is ideal for optimal solar cell current collection.
• a specific process method is detailed for achieving the non-nested and the non-contiguous solar cell design.
• the method is described in the context of back-contact/back-junction thin mono-crystalline silicon solar cells using epitaxial silicon lift-off methods, it can be used for solar cells of any thickness including standard crystalline silicon wafer-based cells (for example in the thickness range of 100 ⁇ to 200 ⁇ using CZ or FZ wafers).
• a thin doped dielectric layer with a similar dopant type as desired for the emitter is deposited on the substrate using either APCVD, PECVD, thermal diffusion (from gas based dopant sources), or using direct, patterned, writing methods such as screen print, inkjet or aerosol jet printing.
• the dielectric film is etched using picoseconds laser ablation. The etch pattern mirrors the base and emitter regions in silicon (with emitter coming from the patterned layer, and the base coming from the subsequent dielectric film deposition) and can either be contiguous or non-contiguous.
• second dielectric film with the opposite type of dopant (phosphorous) for forming the highly doped base diffusion areas.
• the second dopant layer can be deposited using a direct write method.
• a thermal anneal to activate both types of dopants in one step.
• This anneal is may be an inert gas environment such as in nitrogen or argon, and can optionally be followed by an anneal at the same temperature in an oxygen-containing environment for a short time. The purpose of the oxygen environment is to form a thermal oxide interface through the dielectric layers, once the dopant has been diffused.
• a thin metal (preferably comprising aluminum or an alloy comprising aluminum and silicon) is deposited either using blanket plasma sputtering or evaporation or ion beam deposition. This requires subsequent patterning which can be achieved using a myriad techniques including, but not limited to a pico-second laser ablation using a suitable laser wavelength such as near infrared wavelength.
• a direct write or screen printing or aerosol printing, inkjet printing, and stencil printing of a pre-patterned metal layer (for example, a suitable screen printable aluminum and/or aluminum-silicon alloy paste) can be deployed.
• this metal deposition needs to be followed by sintering or anneal to cure and activate the patterned metal layer.
• the thin silicon layer is then can be attached to a second permanent carrier to continue the remaining cell processes such as texture, passivation and metallization.
• a variation of the above process flow is described in Table 2 below. In this flow, the process flow is identical up to the very last metallization step.
• the copper plating flow is replaced by a dry PVD (such as evaporation and/or plasma sputtering) based metal deposition in conjunction with using laser (can be a pulsed nano-second laser) to isolate and pattern the PVD metal layer.
• PVD Metal e.g., Aluminum with NiV cap
• PVD Metal e.g., Aluminum with NiV cap
• FIG. 5 is a representative pattern of the distributed selective emitter and base openings with contacts centrally located inside these regions.
• Figures 6 A and 6B are SEM micrographs showing selective emitter and selective base openings, and contacts within these openings, respectively. These ablation spots were made using a laser with 10 picoseconds pulse length and UV wavelength. Still, some surface damage can be seen.
• the annealing of the ablated region to reduce or eliminate the damage that occurs during the ablation process.
• the ablated area is annealed using another suitable pulsed laser beam that anneals out the damage.
• each ablation spot is annealed, using synchronized laser triggering from the annealing laser.
• a suitable laser typically has pulse length in the long nanoseconds range, such as preferably in the range of approximately 10 to 500 nanoseconds, and wavelength of 532 nm.
• other lasers with even shorter or longer pulse length and other wavelengths could be used depending on the extent of the ablation laser damage to be annealed.
• Figures 7A and 7B show schematically the spot by spot annealing of damaged silicon in selective emitter (SE) and selective base (SB) ablations while Figs. 7C and 7D, show similar spot by spot annealing of the laser damage in the contact ablation area using laser annealing.
• the corresponding optical micrographs are shown in Fig. 8A and 8B.
• Figure 8A shows the laser ablation spots before laser annealing
• Fig. 8B shows the spots after laser annealing. The elimination of laser damage in the ablation spots by laser annealing can be clearly seen.
• Figure 9 shows the improved effective minority carrier lifetime (MCL) obtained upon laser annealing; one-half of a wafer patterned by laser ablation as compared to the half that did not receive the laser annealing treatment.
• the laser anneal of the ablated regions is carried out with at least one doped oxide layer covering the ablated regions.
• the melting on silicon during laser annealing results in melt incorporation or absorption of p-type (boron, for example) and n-type dopant (phosphorous, for example) from the overlying BSG and PSG films into molten silicon, respectively.
• p-type dopant boron, for example
• n-type dopant phosphorous, for example
• a suitable laser apparatus configuration that is highly cost-effective, is a multi-station platform that provides for parallel processing at different stations.
• Figure 10 shows the configuration of a tool having four stations. The wafer is rotated from one chuck to another where a different step of the ablation/annealing process is carried out. As shown in Fig. 10, the wafer is loaded in station 1 , moved to station 2 for fiducial detection for accuracy of laser ablation patterning and aligned laser annealing. The laser ablation is carried out in station 3 followed by annealing in station 4. It should be noted that this scheme provides for parallel processing on different chucks, the throughput being controlled by the slowest process in this sequence.
• FIG. 10B shows 4 wafers per chuck.
• a scheme where a thin layer of mask material is used to absorb the laser beam during ablation to prevent the laser damage is disclosed herein. Regions so opened (where the mask material is removed) can now be further opened to silicon by wet etching the dielectric layer underneath. In effect, in this scheme the thin layer of mask is patterned first using the ablation laser, the pattern then transferred to silicon by wet etching of the dielectric in the opening.
• any non-conducting film that is resistant to the wet etching used to pattern the dielectric can be used as a mask.
• FIGs 11 A to 1 II schematically outline the solar cell structure in the process steps where a thin layer of amorphous silicon (a-Si) is used as the patterning mask for laser ablation.
• a-Si amorphous silicon
• Figure 12 shows the minority carrier lifetime map of a wafer where the top half did not use the ablation mask scheme, while the lower half used the a-Si mask scheme. No lifetime degradation was seen in the lower half of the wafer.
• the disclosed subject matter may be applied directly to the formation of high-efficiency back-contact, back-junction solar cells utilizing multi-layer backside metallization.
• all back-junction, back-contact solar cells have all metallization (both base and emitter metallization and busbars) positioned on the backside of the cell and may eliminate sunlight shading due to metal runners on the front/sunnyside surface of the cell (optical shading losses of emitter metal fingers and busbars in the case of traditional front-contact solar cells).
• metallization both the base and the emitter contacts
• cell metallization complexity may be increased in some back contact designs as both the base and emitter electrodes have to be contacted on the same side. (However, in some instaces same side base and emitter contacts may simplify solar cell interconnections at the module level).
• an interdigitated metallization scheme requiring high metal pattern fidelity may be used.
• the required thickness of the metallization layer may also significantly increase - for example 30 to 60 microns for a high conductivity metallization layer, such as copper or aluminum, on solar cells with dimensions of 125 mm x 125 mm to 156 mm x 156 mm.
• cell metallization may be partitioned into two metal layers/levels and a backplane material (such as a polymer sheet) may be formed between the two metallization layers to help reduce stress induced from the thicker higher-conductance second metallization level.
• the backplane material separates the two metallization layers and provides structural support to the solar cell substrate allowing for scaling to large area back-contact solar cells.
• each layer - first metallization layer, backplane material, and second metallization layer - may be optimized separately for cost and performance.
• the two metal levels are patterned orthogonally with to each other, with the second (last) metal level having far fewer and coarser fingers than the first (on-cell) metal level.
• the following exemplary back junction back contact solar cell designs and manufacturing processes described herein may utilize two levels of metallization (dual layer metallization) which are separated by an electrically insulating and mechanically supportive backplane layer
• the disclosed subject matter may be applicable in any fabrication embodiment requiring real-time in-situ process laser via drilling end-point detection including multi-level metallization patterns and metallization layers comprising metallization stacks (for example a first level metallization layer of Al/NiV/Sn).
• any combination of the backplane and metallization layers may serve as permanent structural support/reinforcement and provide embedded high-conductivity (aluminum and/or copper) interconnects for a high- efficiency thin crystalline silicon solar cell without significantly compromising solar cell power or adding to solar cell manufacturing cost.
• Laser processes using schemes for producing solar cells with high efficiency, and particularly thin- film crystalline silicon solar cells based sub-50- micron thick silicon substrates, are provided herein.
• Fig. 13A is a general process flow, for example, for the formation of a back-contact back-junction solar cell which may utilize the non-nested base regions.
• Fig. 13A is a general process flow highlighting key processing of a tested thin- crystalline-silicon solar cell manufacturing process using thin epitaxial silicon lift-off processing which substantially reduces silicon usage and eliminates traditional manufacturing steps to create low-cost, high-efficiency, back-junction/back-contact monocrystalline cells.
• the process flow of Fig. 13A shows the fabrication of solar cells having laminated backplanes for smart cell and smart module design formed using a reusable template and epitaxial silicon deposition on a release layer of porous silicon which may utilize and integrate the non-nested base region designs and formation methods as disclosed herein.
• a reusable silicon template typically made of a p-type monocrystalline silicon wafer, onto which a thin sacrificial layer of porous silicon is formed (for example by an electrochemical etch process through a surface modification process in an HF/IPA wet chemistry in the presence of an electrical current).
• the starting material or reusable template may be a single crystalline silicon wafer, for example formed using crystal growth methods such as FZ, CZ, MCZ (Magnetic stabilized CZ), and may further comprise epitaxial layers grown over such silicon wafers.
• the semiconductor doping type may be either p or n and the wafer shape, while most commonly square shaped, may be any geometric or non- geometric shape such as quasi-square or round.
• a thin layer for example a layer thickness in the range of a few microns up to about 70 microns, or a thickness less than approximately 50 microns
• in- situ-doped monocrystalline silicon is formed, also called epitaxial growth.
• the in-situ-doped monocrystalline silicon layer may be formed, for example, by atmospheric-pressure epitaxy using a chemical-vapor deposition or CVD process in ambient comprising a silicon gas such as trichlorosilane or TCS and hydrogen.
• the solar cell base and emitter contact metallization pattern is formed directly on the cell backside, for instance using a thin layer of screen printed or sputtered (PVD) or evaporated aluminum (or aluminum silicon alloy or Al/NiV/Sn stack) material layer.
• This first layer of metallization (herein referred to as Ml) defines the solar cell contact metallization pattern, for example fine-pitch interdigitated back-contact (IBC) conductor fingers defining the base and emitter regions of the IBC cell.
• IBC interdigitated back-contact
• the Ml layer extracts the solar cell current and voltage and transfers the solar cell electrical power to the second level/layer of higher-conductivity solar cell metallization (herein referred to as M2) formed after Ml .
• a very-low-cost backplane layer may be bonded to the thin epi layer for permanent cell support and reinforcement as well as to support the high-conductivity cell metallization of the solar cell.
• the backplane material may be made of a thin (for instance, a thickness in the range of approximately 50 to 250 microns and in some instances in the range of 50 to 150 microns), flexible, and electrically insulating polymeric material sheet such as an inexpensive prepreg material commonly used in printed circuit boards which meets cell process integration and reliability requirements.
• the mostly- processed back-contact, back-junction backplane-reinforced large-area (for instance, a solar cell area of at least 125 mm x 125 mm, 156 mm x 156 mm, or larger) solar cell is then separated and lifted off from the template along the mechanically-weakened sacrificial porous silicon layer (for example through a mechanical release MR process) while the template may be re-used many times to further minimize solar cell manufacturing cost.
• Final cell processing may then be performed on the solar cell sunny-side which is exposed after being released from the template.
• Sunny-side processing may include, for instance, completing frontside texturization and passivation and anti-reflection coating deposition process.
• a higher conductivity M2 layer is formed on the backplane.
• Via holes in some instances up to hundreds or thousands of via holes are drilled into the backplane (for example by laser drilling) and may have diameters in the range of approximately 50 up to 500 microns. These via holes land on pre-specified regions of Ml for subsequent electrical connections between the patterned M2 and Ml layers through conductive plugs formed in these via holes.
• the patterned higher-conductivity metallization layer M2 is formed (for example by plasma sputtering, plating, evaporation, or a combination thereof - using an M2 material comprising aluminum, Al/NIV, Al/NiV/Sn, or copper).
• the patterned M2 layer may be designed orthogonal to Ml - in other words rectangular or tapered M2 fingers are essentially perpendicular to the Ml fingers.
• the M2 layer may have far fewer IBC fingers than the Ml layer (for instance, by a factor of about 10 to 50 fewer M2 fingers). Hence, the M2 layer may be formed in a much coarser pattern with wider IBC fingers than the Ml layer.
• Solar cell busbars may be positioned on the M2 layer, and not on the Ml layer (in other words a busbarless Ml), to eliminate electrical shading losses associated with on-cell busbars.
• both the base and emitter interconnections and busbars may be positioned on the M2 layer on the solar cell backside backplane, electrical access is provided to both the base and emitter terminals of the solar cell on the backplane from the backside of the solar cell.
• the backplane material formed between Ml and M2 may be a thin sheet of a polymeric material with sufficiently low coefficient of thermal expansion (CTE) to avoid causing excessive thermally induced stresses on the thin silicon layer.
• CTE coefficient of thermal expansion
• the backplane material should meet process integration requirements for the backend cell fabrication processes, in particular chemical resistance during wet texturing of the cell frontside and thermal stability during the PECVD deposition of the frontside passivation and ARC layer.
• the electrically insulating backplane material should also meet the module-level lamination process and long-term reliability requirements.
• backplane material choice depends on many considerations including, but not limited to, cost, ease of process integration, reliability, pliability, etc.
• a suitable material choice for the backplane material is prepreg.
• Prepreg sheets are used as building blocks of printed circuit boards and may be made from combinations of resins and CTE-reducing fibers or particles.
• the backplane material may be an inexpensive, low-CTE (typically with CTE ⁇ 10 ppm/°C, or with CTE ⁇ 5 ppm/°C), thin (for example 50 to 250 microns, and more particularly in the range of about 50 to 150 microns) prepreg sheet which is relatively chemically resistant to texturization chemicals and is thermally stable at temperatures up to at least 180°C (or as high as at least 280°C).
• the prepreg sheet may be attached to the solar cell backside while still on the template (before the cell lift off process) using a vacuum laminator. Upon applying heat and pressure, the thin prepreg sheet is permanently laminated or attached to the backside of the processed solar cell. Then, the lift-off release boundary is defined around the periphery of the solar cell (near the template edges), for example by using a pulsed laser scribing tool, and the backplane-laminated solar cell is then separated from the reusable template using a mechanical release or lift-off process.
• Subsequent process steps may include: (i) completion of the texture and passivation processes on the solar cell sunnyside, (ii) completion of the solar cell high conductivity metallization on the cell backside (which may comprise part of the solar cell backplane).
• the high-conductivity metallization M2 layer (for example comprising aluminum, copper, or silver) comprising both the emitter and base polarities is formed on the laminated solar cell backplane.
• prepregs are reinforcing materials pre-impregnated with resin and ready to use to produce composite parts (prepregs may be used to produce composites faster and easier than wet lay-up systems).
• Prepregs may be manufactured by combining reinforcement fibers or fabrics with specially formulated pre-catalyzed resins using equipment designed to ensure consistency. Covered by a flexible backing paper, prepregs may be easily handled and remain pliable for a certain time period (out-life) at room temperature. Further, prepreg advances have produced materials which do not require refrigeration for storage, prepregs with longer shelf life, and products that cure at lower temperatures.
• Prepreg laminates may be cured by heating under pressure. Conventional prepregs are formulated for autoclave curing while low-temperature prepregs may be fully cured by using vacuum bag pressure alone at much lower temperatures.
• Fig. 13B is a representative manufacturing process flow for forming a back- contact/back-junction cell using epitaxial silicon lift-off processing may comprise the following fabrication steps: 1) start with reusable template; 2) form porous silicon on template (for example bilayer porous Si using anodic etch); 3) deposit epitaxial silicon with in-situ doping; 4) perform back-contact/back-junction cell processing while on template including Ml formation; 5) laminate backplane sheet on back-contact cell, laser scribe release border around the backplane into epitaxial silicon layer, and cell release; 7) proceed with performing back-end processes including: wet silicon etch/texture/clean, PECVD sunnyside and trench edge passivation, laser drilling of via holes in backplane, PVD deposition or evaporation of metal (- Al), or plating (Cu) for M2, and final laser ablation to complete M2 patterning.
• back-end processes including: wet silicon etch/texture/clean, PECVD sunnyside and trench edge passivation, laser
• Figs. 13A and 13B result in a solar cell formed on an epitaxially deposited thin silicon film with an exemplary thickness in the range of approximately 10 up to about 100 microns which may be easily and advantageously integrated with the nonnested base designs disclosed herein.

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• 2013
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