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WO2011054280A1 - Dispositif ldmos à plaques de champs multiples et procédé de fabrication - Google Patents

Dispositif ldmos à plaques de champs multiples et procédé de fabrication Download PDF

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Publication number
WO2011054280A1
WO2011054280A1 PCT/CN2010/078342 CN2010078342W WO2011054280A1 WO 2011054280 A1 WO2011054280 A1 WO 2011054280A1 CN 2010078342 W CN2010078342 W CN 2010078342W WO 2011054280 A1 WO2011054280 A1 WO 2011054280A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor body
field plate
field plates
ldmos device
horizontal portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2010/078342
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English (en)
Chinese (zh)
Inventor
陈强
马强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INNOGRATION (HONGKONG) CO Ltd
INNOGRATION (SUZHOU) CO Ltd
INNOGRATION (CAYMAN) CO Ltd
Original Assignee
INNOGRATION (HONGKONG) CO Ltd
INNOGRATION (SUZHOU) CO Ltd
INNOGRATION (CAYMAN) CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INNOGRATION (HONGKONG) CO Ltd, INNOGRATION (SUZHOU) CO Ltd, INNOGRATION (CAYMAN) CO Ltd filed Critical INNOGRATION (HONGKONG) CO Ltd
Publication of WO2011054280A1 publication Critical patent/WO2011054280A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/254—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts

Definitions

  • the present invention relates to a multiple field plate LDMOS device and a method of processing the same.
  • the object of the present invention is to provide a multiple field plate LDMOS
  • the device and its processing method can better alleviate the contradiction between the source-drain breakdown voltage and the optimization requirements of the on-resistance, and improve the performance of the LDMOS device.
  • the technical solution of the present invention is: a multiple field plate LDMOS
  • the device includes a semiconductor body having at least two field plates on the surface thereof, each of the field plates having a horizontal portion parallel to the surface of the semiconductor body, the distance between the horizontal portion of the different field plates and the surface of the semiconductor body is not Wait.
  • all of the field plates are located above the drain drift region of the semiconductor body.
  • the distance between the horizontal portion of the at least two field plates and the surface of the semiconductor body is successively increased. That is, the first field plate is disposed closest to the surface of the semiconductor body, the second field plate is slightly farther, and so on.
  • This successive increment may be a linear increment or a non-uniform increment, but is preferably a uniform linear successive increment.
  • the horizontal portions of the field plates may or may not overlap in the lateral position.
  • a method of processing a multiple field plate LDMOS device comprising the following steps:
  • step 3) Repeat step 3) according to the number of field plates you need to make. For example, when only two field plates need to be processed, there is no need to repeat step 3 ); when it is necessary to process three field plates, repeat step 3), and so on.
  • the advantages of the present invention are: device simulation calculations show that the optimized design of single-field LDMOS devices with the same on-resistance and the optimized design of multiple field plates under the same conditions of all other device structural parameters LDMOS devices, multiple field plate LDMOS devices have higher source-drain breakdown voltages than single-field LDMOS devices (such as dual field plates with grounded LDMOS under the above conditions)
  • the device has a source-drain breakdown voltage of 73V and a grounded single-field LDMOS device with a source-drain breakdown voltage of 61V). This indicates that LDMOS using multiple field plates is required under the same source-drain breakdown voltage requirements.
  • the device can significantly increase the doping concentration of the N-type drift region, and the on-resistance of the device can be significantly improved.
  • FIG. 1 is a schematic structural view of a prior art single field plate LDMOS device
  • FIG. 2 is a schematic structural view of a specific embodiment of the present invention.
  • FIG. 3 is a schematic view showing the connection of a first field plate according to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of connection of a second field plate according to another embodiment of the present invention.
  • Embodiment As shown in FIG. 2, a multiple field plate LDMOS with a source-drain breakdown voltage between 60V and 120V.
  • the device includes a semiconductor body 1 including a lowermost P-type heavily doped substrate 12, a P-type epitaxial layer 13 on a P-type heavily doped substrate 12, and a P-type epitaxial layer 13 formed on the P-type heavily doped source region 15, the P-type doped channel region 16, the N-type doped drain drift region 11 and the N-type heavily doped drain region 18, wherein the P-type heavily doped region 15 and An N-type heavily doped source region 17 is formed at a position where the P-type doped channel region 16 is connected.
  • the source ohmic contact region 111 is disposed on the upper surface of the P-type heavily doped source region 15 and the N-type heavily doped source region 17, and the drain ohmic contact region 110 is disposed on N-type heavily doped drain region 18 upper surface.
  • a gate 19 is also formed on the semiconductor body 1.
  • the surface of the semiconductor body 1 is provided with three field plates 2, each of which has a semiconductor body 1
  • the horizontal portion 21 parallel to the surface, the distance between the horizontal portion 21 of each field plate 2 and the surface of the semiconductor body 1 is uniformly linearly successively increased.
  • the field plate 2 is situated above the drain drift region 11 of the semiconductor body 1.
  • FIG. 3 and FIG. 4 are schematic structural diagrams of another embodiment, the semiconductor body 1
  • the structure is the same as that of the previous embodiment, but the field plate 2 is provided with two, and the horizontal portion 21 of the first field plate 2a is spaced from the surface of the semiconductor body 1 by 0.06 ⁇ m to 0.5. Between microns, the horizontal lateral extension distance is between 0.4 microns and 2 microns.
  • the horizontal portion of the second field plate 2b is at a distance of 0.1 ⁇ m to 1 from the surface of the semiconductor body 1 Between the micrometers (regardless of the value, the horizontal portion of the second field plate is farther from the surface of the semiconductor body 1 than the first field plate), and the horizontal lateral expansion distance is between 0.4 microns and 2 microns.
  • Each field plate 2 may be comprised of a metal or other form of electrical conductor (e.g., doped polysilicon, silicide, etc.) having a thickness between 0.05 microns and 0.5 microns.
  • electrical conductor e.g., doped polysilicon, silicide, etc.
  • the length of the drain drift region 11 is between 2 micrometers and 6 micrometers, and the surface doping concentration of the drift region is 1 to 6E12/cm 2 between.
  • a method of processing a multiple field plate LDMOS device comprising the following steps:
  • step 4) Repeat step 3) according to the number of field plates you need to make.
  • LDMOS with one or more metal interconnects For example, in the case of two field plates in the process, one possible method of grounding the field plate is:
  • the ground connection can also be made through the second metal 5b and the second through hole 4b.
  • the field plates can be connected to different DC voltages or grounded.
  • the grounding effect of each field plate is better.
  • the field plate is generally only grounded, and the connection method of the field plate of the present invention is more flexible.
  • the invention is particularly suitable for use in LDMOS devices with source-drain breakdown voltages greater than 40-50V, which alleviates the contradiction between source-drain breakdown voltage and on-resistance optimization requirements, and improves the performance of LDMOS devices.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un dispositif LDMOS à plaques de champs multiples, ainsi qu'un procédé de fabrication de celui-ci. Le dispositif LDMOS à plaques de champs multiples comprend un corps de semi-conducteur (1) à la surface duquel sont disposées au moins deux plaques de champs (2). Chacune des plaques de champs (2) comprend une partie horizontale (21) qui est parallèle à la surface du corps de semi-conducteur (1). Les distances entre les parties horizontales (21) de différentes plaques de champs (2) et la surface du corps de semi-conducteur (1) sont différentes. En utilisant le dispositif LDMOS à plaques de champs multiples, la concentration de dosage d'une région de dérive de type N peut être visiblement accrue de sorte que la résistance passante du dispositif sous les mêmes exigences de tension de claquage source-drain puisse être visiblement réduite.
PCT/CN2010/078342 2009-11-03 2010-11-02 Dispositif ldmos à plaques de champs multiples et procédé de fabrication Ceased WO2011054280A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200910174438.0 2009-11-03
CN200910174438A CN101707208A (zh) 2009-11-03 2009-11-03 多重场板ldmos器件及其加工方法

Publications (1)

Publication Number Publication Date
WO2011054280A1 true WO2011054280A1 (fr) 2011-05-12

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PCT/CN2010/078342 Ceased WO2011054280A1 (fr) 2009-11-03 2010-11-02 Dispositif ldmos à plaques de champs multiples et procédé de fabrication

Country Status (2)

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CN (1) CN101707208A (fr)
WO (1) WO2011054280A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270664A (zh) * 2011-09-01 2011-12-07 上海先进半导体制造股份有限公司 Ldmos晶体管结构及其形成方法
US9559199B2 (en) 2014-12-18 2017-01-31 Silanna Asia Pte Ltd LDMOS with adaptively biased gate-shield
US11171215B2 (en) 2014-12-18 2021-11-09 Silanna Asia Pte Ltd Threshold voltage adjustment using adaptively biased shield plate

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101707208A (zh) * 2009-11-03 2010-05-12 苏州远创达科技有限公司 多重场板ldmos器件及其加工方法
CN102790088A (zh) * 2012-07-20 2012-11-21 昆山华太电子技术有限公司 一个击穿电压可以调整rf-ldmos器件
CN104183632B (zh) * 2014-08-13 2017-08-29 昆山华太电子技术有限公司 Rf‑ldmos自对准的漏端场板结构及制作方法
CN104241381A (zh) * 2014-09-10 2014-12-24 上海联星电子有限公司 一种射频ldmos器件及其制备方法
US10177225B2 (en) * 2015-08-12 2019-01-08 Mediatek Inc. Electronic component and manufacturing method thereof
CN109980011A (zh) * 2017-12-28 2019-07-05 无锡华润上华科技有限公司 一种半导体器件及其制作方法
US20200144381A1 (en) * 2018-11-07 2020-05-07 Monolithic Power Systems, Inc. Ldmos device with a drain contact structure with reduced size
CN113675262B (zh) * 2020-05-14 2023-12-05 苏州华太电子技术股份有限公司 应用于半导体器件的场板结构及其制作方法和应用
CN114566540A (zh) * 2022-02-11 2022-05-31 华虹半导体(无锡)有限公司 Ldmos器件及其制造方法

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US20040201078A1 (en) * 2003-04-11 2004-10-14 Liping Ren Field plate structure for high voltage devices
JP2005045080A (ja) * 2003-07-24 2005-02-17 Matsushita Electric Ind Co Ltd 半導体装置
CN1947262A (zh) * 2004-02-27 2007-04-11 英飞凌科技股份公司 Ldmos晶体管及其制作方法
CN1950945A (zh) * 2004-05-11 2007-04-18 美商克立股份有限公司 具有多个场板的宽能带隙晶体管
CN101707208A (zh) * 2009-11-03 2010-05-12 苏州远创达科技有限公司 多重场板ldmos器件及其加工方法
CN201540894U (zh) * 2009-11-03 2010-08-04 苏州远创达科技有限公司 多重场板ldmos器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040201078A1 (en) * 2003-04-11 2004-10-14 Liping Ren Field plate structure for high voltage devices
JP2005045080A (ja) * 2003-07-24 2005-02-17 Matsushita Electric Ind Co Ltd 半導体装置
CN1947262A (zh) * 2004-02-27 2007-04-11 英飞凌科技股份公司 Ldmos晶体管及其制作方法
CN1950945A (zh) * 2004-05-11 2007-04-18 美商克立股份有限公司 具有多个场板的宽能带隙晶体管
CN101707208A (zh) * 2009-11-03 2010-05-12 苏州远创达科技有限公司 多重场板ldmos器件及其加工方法
CN201540894U (zh) * 2009-11-03 2010-08-04 苏州远创达科技有限公司 多重场板ldmos器件

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270664A (zh) * 2011-09-01 2011-12-07 上海先进半导体制造股份有限公司 Ldmos晶体管结构及其形成方法
US9559199B2 (en) 2014-12-18 2017-01-31 Silanna Asia Pte Ltd LDMOS with adaptively biased gate-shield
US10192983B2 (en) 2014-12-18 2019-01-29 Silanna Asia Pte Ltd LDMOS with adaptively biased gate-shield
US10636905B2 (en) 2014-12-18 2020-04-28 Silanna Asia Pte Ltd LDMOS with adaptively biased gate-shield
US11171215B2 (en) 2014-12-18 2021-11-09 Silanna Asia Pte Ltd Threshold voltage adjustment using adaptively biased shield plate
US11742396B2 (en) 2014-12-18 2023-08-29 Silanna Asia Pte Ltd Threshold voltage adjustment using adaptively biased shield plate
US12100740B2 (en) 2014-12-18 2024-09-24 Silanna Asia Pte Ltd Threshold voltage adjustment using adaptively biased shield plate

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