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WO2008129774A1 - 抵抗変化型記憶装置 - Google Patents

抵抗変化型記憶装置 Download PDF

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Publication number
WO2008129774A1
WO2008129774A1 PCT/JP2008/000542 JP2008000542W WO2008129774A1 WO 2008129774 A1 WO2008129774 A1 WO 2008129774A1 JP 2008000542 W JP2008000542 W JP 2008000542W WO 2008129774 A1 WO2008129774 A1 WO 2008129774A1
Authority
WO
WIPO (PCT)
Prior art keywords
resistance
voltage
active element
current
limiting active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/000542
Other languages
English (en)
French (fr)
Inventor
Yoshikazu Katoh
Kazuhiko Shimakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to CN2008800082108A priority Critical patent/CN101636792B/zh
Priority to JP2009510754A priority patent/JP5095728B2/ja
Priority to US12/529,103 priority patent/US8094481B2/en
Publication of WO2008129774A1 publication Critical patent/WO2008129774A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

　本発明の抵抗変化型記憶装置（１０）は、第１の電圧を超えると高抵抗状態へ第２の電圧を超えると低抵抗状態へ変化する抵抗変化型素子（１）と、制御装置（４）と、抵抗変化型素子（１）と直列に接続された電圧制限能動素子（２）と、電圧制限能動素子（２）を介して抵抗変化型素子（１）と直列に接続された電流制限能動素子（３）とを備え、制御装置（４）は、高抵抗状態へ変化させる場合に、電流と第１の抵抗値との積が第１の電圧以上となるように電流制限能動素子（３）を制御し、かつ電極間電圧が第２の電圧未満となるように電圧制限能動素子（２）を制御するように構成され、かつ、低抵抗状態へと変化させる場合に、電流と第２の抵抗値との積の絶対値が第２の電圧以上になりかつ電流と第１の抵抗値との積の絶対値が第１の電圧未満となるように電流制限能動素子（３）を制御するように構成されている。
PCT/JP2008/000542 2007-03-13 2008-03-12 抵抗変化型記憶装置 Ceased WO2008129774A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2008800082108A CN101636792B (zh) 2007-03-13 2008-03-12 电阻变化型存储器件
JP2009510754A JP5095728B2 (ja) 2007-03-13 2008-03-12 抵抗変化型記憶装置
US12/529,103 US8094481B2 (en) 2007-03-13 2008-03-12 Resistance variable memory apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-063155 2007-03-13
JP2007063155 2007-03-13

Publications (1)

Publication Number Publication Date
WO2008129774A1 true WO2008129774A1 (ja) 2008-10-30

Family

ID=39875311

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000542 Ceased WO2008129774A1 (ja) 2007-03-13 2008-03-12 抵抗変化型記憶装置

Country Status (4)

Country Link
US (1) US8094481B2 (ja)
JP (1) JP5095728B2 (ja)
CN (1) CN101636792B (ja)
WO (1) WO2008129774A1 (ja)

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US8625328B2 (en) 2009-10-15 2014-01-07 Panasonic Corporation Variable resistance nonvolatile storage device
JP2016021272A (ja) * 2014-06-16 2016-02-04 パナソニックＩｐマネジメント株式会社 抵抗変化型不揮発性記憶装置
JP2020507880A (ja) * 2017-01-20 2020-03-12 ヘフェイ リライアンス メモリー リミティド Ｒｒａｍ 書き込み

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CN102169720B (zh) * 2010-02-25 2014-04-02 复旦大学 一种消除过写、误写现象的电阻随机存储器
US8498141B2 (en) * 2010-03-24 2013-07-30 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
CN102804278B (zh) * 2010-03-30 2014-10-01 松下电器产业株式会社 电阻变化型非易失性存储元件的塑造方法及电阻变化型非易失性存储装置
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US8946046B1 (en) 2012-05-02 2015-02-03 Crossbar, Inc. Guided path for forming a conductive filament in RRAM
US9601692B1 (en) 2010-07-13 2017-03-21 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8274812B2 (en) * 2010-06-14 2012-09-25 Crossbar, Inc. Write and erase scheme for resistive memory device
US9437297B2 (en) 2010-06-14 2016-09-06 Crossbar, Inc. Write and erase scheme for resistive memory device
US8411485B2 (en) 2010-06-14 2013-04-02 Crossbar, Inc. Non-volatile variable capacitive device including resistive memory cell
US9013911B2 (en) 2011-06-23 2015-04-21 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US8569172B1 (en) 2012-08-14 2013-10-29 Crossbar, Inc. Noble metal/non-noble metal electrode for RRAM applications
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US8502185B2 (en) 2011-05-31 2013-08-06 Crossbar, Inc. Switching device having a non-linear element
USRE46335E1 (en) 2010-11-04 2017-03-07 Crossbar, Inc. Switching device having a non-linear element
US9620206B2 (en) 2011-05-31 2017-04-11 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US8619459B1 (en) 2011-06-23 2013-12-31 Crossbar, Inc. High operating speed resistive random access memory
US8946669B1 (en) 2012-04-05 2015-02-03 Crossbar, Inc. Resistive memory device and fabrication methods
US9564587B1 (en) 2011-06-30 2017-02-07 Crossbar, Inc. Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
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US10056907B1 (en) 2011-07-29 2018-08-21 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
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Publication number Priority date Publication date Assignee Title
US8625328B2 (en) 2009-10-15 2014-01-07 Panasonic Corporation Variable resistance nonvolatile storage device
JP2016021272A (ja) * 2014-06-16 2016-02-04 パナソニックＩｐマネジメント株式会社 抵抗変化型不揮発性記憶装置
JP2020507880A (ja) * 2017-01-20 2020-03-12 ヘフェイ リライアンス メモリー リミティド Ｒｒａｍ 書き込み
US10998044B2 (en) 2017-01-20 2021-05-04 Hefei Reliance Memory Limited RRAM write using a ramp control circuit
US11238930B2 (en) 2017-01-20 2022-02-01 Hefei Reliance Memory Limited Method of RRAM WRITE ramping voltage in intervals
US11682457B2 (en) 2017-01-20 2023-06-20 Hefei Reliance Memory Limited Method of RRAM write ramping voltage in intervals
US12327587B2 (en) 2017-01-20 2025-06-10 Hefei Reliance Memory Limited Method of RRAM write ramping voltage in intervals

Also Published As

Publication number Publication date
JP5095728B2 (ja) 2012-12-12
CN101636792A (zh) 2010-01-27
US8094481B2 (en) 2012-01-10
CN101636792B (zh) 2013-03-13
US20100110767A1 (en) 2010-05-06
JPWO2008129774A1 (ja) 2010-07-22

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