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WO2008099700A1 - Transistor à double grille, son procédé de fabrication, et substrat de matrice actif comprenant un transistor à double grille - Google Patents

Transistor à double grille, son procédé de fabrication, et substrat de matrice actif comprenant un transistor à double grille Download PDF

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Publication number
WO2008099700A1
WO2008099700A1 PCT/JP2008/051757 JP2008051757W WO2008099700A1 WO 2008099700 A1 WO2008099700 A1 WO 2008099700A1 JP 2008051757 W JP2008051757 W JP 2008051757W WO 2008099700 A1 WO2008099700 A1 WO 2008099700A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate transistor
double gate
forming
semiconductor layer
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/051757
Other languages
English (en)
Japanese (ja)
Inventor
Hidehito Kitakado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of WO2008099700A1 publication Critical patent/WO2008099700A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un transistor à double grille (100), qui comprend une étape de formation d'une électrode de grille inférieure (110), une étape de formation d'un film d'isolation de première grille (120) recouvrant l'électrode de grille inférieure (110), une étape de formation d'une couche semi-conductrice tournée vers l'électrode de grille inférieure (110) à travers le film d'isolation de première grille (120), une étape d'obtention d'une couche semi-conductrice cristalline (130) par irradiation de la couche semi-conductrice avec un faisceau laser, une étape de formation d'un film (140) d'isolation de seconde grille recouvrant la couche (130) semi-conductrice cristalline, et une étape de formation d'une électrode de grille supérieure (150) tournée vers la couche (130) semi-conductrice cristalline à travers le film (140) d'isolation de seconde grille. L'électrode de grille inférieure (110) a une surface composée d'un oxyde de métal conducteur.
PCT/JP2008/051757 2007-02-16 2008-02-04 Transistor à double grille, son procédé de fabrication, et substrat de matrice actif comprenant un transistor à double grille Ceased WO2008099700A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007035929 2007-02-16
JP2007-035929 2007-02-16

Publications (1)

Publication Number Publication Date
WO2008099700A1 true WO2008099700A1 (fr) 2008-08-21

Family

ID=39689944

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/051757 Ceased WO2008099700A1 (fr) 2007-02-16 2008-02-04 Transistor à double grille, son procédé de fabrication, et substrat de matrice actif comprenant un transistor à double grille

Country Status (1)

Country Link
WO (1) WO2008099700A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010113312A1 (fr) * 2009-04-02 2010-10-07 パイオニア株式会社 Dispositif d'affichage
JP2015130511A (ja) * 2009-07-18 2015-07-16 株式会社半導体エネルギー研究所 半導体装置
WO2017179504A1 (fr) * 2016-04-15 2017-10-19 シャープ株式会社 Transistor à couche mince
JP2021129352A (ja) * 2020-02-12 2021-09-02 シチズン時計株式会社 電気機械変換器
CN113447858A (zh) * 2020-11-11 2021-09-28 重庆康佳光电技术研究院有限公司 电路背板检测装置及检测方法
JP2023014101A (ja) * 2009-09-04 2023-01-26 株式会社半導体エネルギー研究所 発光装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209467A (ja) * 1997-01-24 1998-08-07 Sony Corp 薄膜半導体装置
JP2002033481A (ja) * 2000-07-14 2002-01-31 Sony Corp 薄膜半導体装置
JP2002367905A (ja) * 2001-04-06 2002-12-20 Seiko Epson Corp 薄膜半導体装置の製造方法
JP2003273361A (ja) * 2002-03-15 2003-09-26 Sharp Corp 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209467A (ja) * 1997-01-24 1998-08-07 Sony Corp 薄膜半導体装置
JP2002033481A (ja) * 2000-07-14 2002-01-31 Sony Corp 薄膜半導体装置
JP2002367905A (ja) * 2001-04-06 2002-12-20 Seiko Epson Corp 薄膜半導体装置の製造方法
JP2003273361A (ja) * 2002-03-15 2003-09-26 Sharp Corp 半導体装置およびその製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010113312A1 (fr) * 2009-04-02 2010-10-07 パイオニア株式会社 Dispositif d'affichage
JP2015130511A (ja) * 2009-07-18 2015-07-16 株式会社半導体エネルギー研究所 半導体装置
JP2023014101A (ja) * 2009-09-04 2023-01-26 株式会社半導体エネルギー研究所 発光装置
JP7480255B2 (ja) 2009-09-04 2024-05-09 株式会社半導体エネルギー研究所 発光装置
WO2017179504A1 (fr) * 2016-04-15 2017-10-19 シャープ株式会社 Transistor à couche mince
JP2021129352A (ja) * 2020-02-12 2021-09-02 シチズン時計株式会社 電気機械変換器
JP7408431B2 (ja) 2020-02-12 2024-01-05 シチズン時計株式会社 電気機械変換器
CN113447858A (zh) * 2020-11-11 2021-09-28 重庆康佳光电技术研究院有限公司 电路背板检测装置及检测方法

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