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WO2006000175A1 - Circuit electrique comprenant une structure conductrice en carbone, et procede de production d'une structure conductrice en carbone d'un circuit electrique - Google Patents

Circuit electrique comprenant une structure conductrice en carbone, et procede de production d'une structure conductrice en carbone d'un circuit electrique Download PDF

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Publication number
WO2006000175A1
WO2006000175A1 PCT/DE2005/000905 DE2005000905W WO2006000175A1 WO 2006000175 A1 WO2006000175 A1 WO 2006000175A1 DE 2005000905 W DE2005000905 W DE 2005000905W WO 2006000175 A1 WO2006000175 A1 WO 2006000175A1
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WO
WIPO (PCT)
Prior art keywords
carbon
conductor structure
electrical circuit
layer
circuit according
Prior art date
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Ceased
Application number
PCT/DE2005/000905
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German (de)
English (en)
Inventor
Manfred Engelhardt
Wolfgang HÖNLEIN
Franz Kreupl
Gernot Steinlesberger
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of WO2006000175A1 publication Critical patent/WO2006000175A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49877—Carbon, e.g. fullerenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • An electrical circuit having a carbon conductive pattern and method of fabricating a carbon conductive pattern of an electrical circuit
  • the invention relates to an electrical circuit having a carbon-conductor structure and to a method for producing a carbon-conductor structure of an electrical circuit.
  • 3D integration i. a suitable superimposing or stacking of the individual components or system units of the integrated circuit [1]. This makes it possible to increase the packing density and thus to reduce the space required in a plane.
  • 3D integration is the stacking of different integrated circuits, so-called systems, which are to be integrated on a common chip, whereby a so-called system-on-chip (SoC) is formed.
  • SoC system-on-chip
  • 3D integration is advantageous for some technology systems when stacking parallel processing units, ie, integrated circuits. This is the case, for example, for the technological realization of image processing and pattern recognition on the model of the human brain [2].
  • the properties of the metallization systems, ie the electrical conductor structures and the surrounding dielectric layers, which interconnect individual components of the integrated circuits, are of particular importance.
  • Important properties of a metallization system are the electrical properties, such as the electrical resistance of the individual conductor structures, both the conductor structures within a plane, ie the so-called tracks, as well as the conductor structures, which connect two levels, the so-called vias. Furthermore, the dielectric properties of the insulating dielectric layers between the conductor patterns of the integrated circuit metallization system are also of great importance. In order to keep the RC switching times for signal transmission within the integrated circuit as low as possible, attempts are made to keep both the resistance R and the capacitance C, ie the dielectric constant k of the insulating layers, as low as possible. Thus, " low resistivity materials and low k dielectrics are preferred.
  • the metallization system can be processed easily, reproducibly and inexpensively and has a low probability of failure.
  • vias i.
  • tungsten-based metal wirings or interconnects such as shown in [1] or doped polysilicon such as shown in [2] are used.
  • a disadvantage of forming the vias by means of tungsten technology or polysilicon technology is that in the usual deposition processes of these materials an inhomogeneous sidewall covering occurs, whereby the filling of holes through which the vertical wiring is formed, with high aspect ratios, ie high ratio of height to width of the hole, very difficult.
  • the inhomogeneous sidewall covering leads to voids, so-called voids, within the via.
  • the filling of holes with an aspect ratio between 20 and 50 can be carried out in the case of highly doped polysilicon only in a multi-stage process, whereby the manufacturing process of a 3D integrated circuit is complicated and expensive. If the via is formed of tungsten, good sidewall coverage can be achieved, but will cause great stress, i. a high mechanical load generated.
  • the invention is based on the problem, an electrical circuit having a conductor structure of an alternative To provide material and a method for producing a conductor structure of an alternative material of an electrical circuit, wherein the material of the conductor structure over the known materials has improved electrical properties and it can be easily integrated into conventional process technologies.
  • An electrical circuit has at least one carbon conductor structure which is formed by means of a layer consisting essentially of carbon, which has a specific resistance of less than 1 m ⁇ cm.
  • One method of fabricating a carbon circuit pattern of an electrical circuit on a substrate is to fabricate the carbon conductive pattern on a surface of the substrate in an atmosphere having a hydrogen partial pressure between 1 hectopascal and 6 hectopascals and at a temperature of between 700 ° C and 1000 ° C Celsius, the carbon-conductor structure is formed as a substantially carbon-containing layer by supplying a carbon-containing gas.
  • an aspect of the invention can be seen in that, instead of metallic conductor structures, conductor structures are used which are essentially made of carbon.
  • An advantage of carbon conductor structures are the very good processability of carbon and the possibility of training in simple processes. This means that metallization systems whose conductor structures essentially comprise carbon are formed.
  • Metallization systems according to the invention not only metallization systems with metal Conductor structures understood, but generally systems that serve the electrical contact various components of an integrated electrical circuit and in which at least individual conductor structures may be formed of carbon.
  • a conductor structure is understood in particular to be conductor tracks, ie conductor tracks within a plane or layer or in other words essentially horizontal conductor tracks, and vias, ie electrically conductive connections between two planes or layers or in other words substantially vertical conductors.
  • vias can be formed both between the different levels of 3D integration, as well as within a plane, for example, between two layers of a layer arrangement, which form an electronic circuit, such as a transistor.
  • carbon conductor structures can be designed such that they have a specific resistance which is comparable to that of metals.
  • carbon as the material of the conductor patterns, it can be achieved that for small feature sizes, i. Structure widths of less than 100 nm, the electron scattering processes are reduced in the conductor structure, whereby it does not come to the increase in resistivity, as can be observed in metals, for which at structural widths of less than 100 nm, the resistivity, which for macroscopic Given systems is not achievable.
  • carbon conductor structures acts as a diffusion barrier at the same time.
  • special diffusion barriers such as are used in the use of copper and silicon oxide, and which complicate and slow down the manufacturing process of electrical circuits are not necessary.
  • adhesion promoting layers are in carbon-conductor structures not necessary, since carbon, unlike, for example, copper, adheres to silicon oxide.
  • Such diffusion barriers and adhesion-promoting layers are usually produced from tantalum-based materials when using copper as the material of the conductor structures, which are expensive [3].
  • the entire manufacturing process can thus be shortened in time and cost-effective by saving process steps.
  • the deposition time of a layer of carbon used as the carbon conductor structure is relatively short.
  • a parallel so-called batch process with good reproducibility is possible.
  • the carbon layer has a roughness of, for example, 2 nm + 0.3 nm with an average grain size of 1 nm to 2 nm.
  • a deposited carbon layer can also be structured in a simple manner in order to form a carbon conductor structure. This can be done for example by means of a hydrogen and / or oxygen plasma and / or air plasma.
  • the electrical circuit has at least two subcircuits, wherein the at least two subcircuits are electrically connected to one another by means of the carbon conductor structure.
  • the at least two subcircuits are formed in two different planes, and the carbon conductor structure forms a vertical connection between the two different planes.
  • a via can be formed, which interconnects partial circuits of the electrical circuit, which are arranged in different planes.
  • the carbon conductor structure to form a vertical connection, called a via, is an easy way to form such a via.
  • the carbon-conductor structure can be formed by means of a simple deposition process with optimum edge coverage and very good filling properties.
  • very high aspect ratios i. a ratio of height to width, the Via, possible.
  • holes having aspect ratios of 100 to 200 can be homogeneously filled, i. It is possible to realize aspect ratios which can not be achieved, for example, by means of tungsten or doped polysilicon.
  • the electrical conductivity of a via of carbon is also at least comparable to that of highly doped polysilicon, so that a sufficient conductivity of the vertical connection can be ensured.
  • the subcircuits may in this case be all known integrated circuits, such as memories, transistors, logic gates or diodes.
  • the aspect ratio of the vertical connection is between 50 and 500, preferably between 100 and 400 and particularly preferably between 100 and 200.
  • the individual subcircuits are preferably independent chips, for example logic components, which are electrically conductively connected to one another by means of a carbon conductor structure, it is possible to achieve a highly integrated 3D integration of chips.
  • SoC system-on-chips
  • At least one subcircuit is a biochip.
  • bio-chips in which a carbon ladder structure is formed are particularly advantageous because carbon is biocompatible, i. Biomolecules or cells does not harm.
  • the substantially carbon-based conductor structure is polycrystalline carbon.
  • a polycrystalline carbon layer is understood as meaning a layer which in each case has a graphite-like structure in partial areas. However, it is not a large hexagonal structure formed.
  • the individual partial regions with a graphite-like structure have a size which corresponds to the grain size of the polycrystalline carbon layer and is about 1 nm to 2 nm.
  • the individual subareas with hexagonal graphite structure are interrupted again and again by areas in which no regular graphite structure is present or in which the hexagonal graphite structures have at least one other orientation.
  • the individual subregions with a regular graphite structure can be regarded as "crystalline" areas.
  • the polycrystalline carbon has a plurality of "crystalline” regions. For this reason, the term "polycrystalline carbon" was chosen for the material in the context of this application.
  • the individual crystalline regions, ie the graphite structures generally have a preferred direction, ie layer-like structures of the polycrystalline carbon are formed.
  • the carbon-conductor structure preferably has a specific resistance between 1 ⁇ cm and 100 ⁇ cm, and particularly preferably between 1 ⁇ cm and 5 ⁇ cm.
  • Carbon conductor structures having such resistivities are particularly suitable for use in electrical integrated circuits.
  • the resistance of the carbon-conductor structure is even lower than that of a metallic conductor structure, because, as already mentioned, with metal structures of less than 100 nm, electron scattering processes occur. Due to the low resistance, the RC switching times of the electrical circuits can be reduced.
  • the low specific resistances can be achieved with carbon conductor structures which are doped by means of conventional dopants, such as boron, phosphorus or arsenic, the doping being able to be carried out by means of so-called in-situ doping or implantation.
  • Intercalation by means of metal halides such as arsenic fluoride (AsFs) or antimony fluoride (SbFs) is also possible.
  • AsFs arsenic fluoride
  • SBFs antimony fluoride
  • a specific electrical resistance of up to 1.1 ⁇ cm [4] can be achieved.
  • the resistivities of doped carbon conductor structures are substantially lower than those of highly doped polysilicon, which is commonly used in the prior art for the formation of vertical connections.
  • the carbon-conductor structure also has a better thermal conductivity, which in 3D integrated circuits, the resulting heat can be better dissipated, and thus a chip heating can be counteracted.
  • the carbon conductor structure is doped and / or intercalated.
  • the doped and / or intercalated carbon conductor structure is thermally activated.
  • the thermal activation is a suitable method step in order to favorably influence the properties, for example the specific resistance, of the carbon conductor structure.
  • the thermal activation may be performed by heating a gas located in a chamber in which the electrical circuit is being processed.
  • An alternative possibility is to heat the wafer on which the electrical circuit is processed, for example via an electric heater of the so-called chuck.
  • thermal activation it should be noted that this is not carried out at temperatures so high that components formed in the electrical circuit can be damaged, For example, a doping of trained transistors can be influenced.
  • the carbon conductor pattern may be a carbon trace and / or a via of substantially carbon.
  • a selective activation of the doped and / or intercalated carbon conductor structure is carried out by means of laser.
  • a laser is a particularly suitable means to perform selective activation of the doped and / or intercalated carbon conductor structure, as by means of a laser, selectively selectively thermally treating regions, i. can be heated.
  • the carbonaceous gas may be methane, ethane, alcohol vapor and / or acetylene.
  • These carbonaceous gases are particularly suitable for use in the process for producing a polycrystalline carbon layer and can be used singly or in combination.
  • the temperature is between 900 ° Celsius and 970 ° Celsius and the hydrogen partial pressure is substantially 1 Hectopascal, and so much carbon-containing gas is supplied in forming the carbon conductor structure that a total pressure of between 500 Hectopascals and 700 Hectopascals sets.
  • the temperature is preferably 950 ° Celsius and the total pressure 600 hectopascal.
  • the temperature is between 750 ° C and 850 ° C
  • the hydrogen partial pressure is substantially 3.5 Hectopascals
  • so much carbon-containing gas is supplied in forming the carbon-conductor structure that a partial pressure of the carbon-containing gas is between 8 Hectopascals and 12 Hectopascals.
  • Preferred is the temperature 800 ° Celsius and the partial pressure of the carbonaceous gas 10 hectopascal.
  • the temperature is at least partially maintained by means of a photon heater.
  • Using a photon heater to provide at least a portion of the energy of the heating to the required temperature is advantageous because it has been found that in this case the temperature in the process can be lowered. As a result, a lower power supply is required in carrying out the method and the risk of impairment of already trained subcircuits lowered.
  • the invention provides an alternative to previously used materials for integrated circuit metallization structures or metallization systems.
  • carbon is used instead of the previous use of metals or, in the case of vertical connections, of doped polysilicon.
  • the carbon conductor structures are characterized by very simple and cost-effective production and easy processability, in particular, the time required to form a carbon layer, much lower than the formation of a copper layer in the damascene process and is about 15 minutes.
  • the carbon conductor structures in particular in the case of small structures or with respect to doped polysilicon, have a lower specific resistance than conductor structures made of hitherto customary materials in metallization systems. This makes it possible the switching times of the integrated To scale down circuits, ie to operate the integrated circuits with a faster cycle than is possible today with copper metallizations.
  • the carbon conductor structures both as interconnects within a plane or layer or, in other words, as substantially horizontal conductor structures, as well as so-called vias, ie in the main vertical ⁇ conductor structures can be used.
  • the vias can be either 1 vias of 3D integration, ie vias that connect one level of 3D integration to another level of SD integration, as well as vias that • have different layers within one level of 3D integration a layer arrangement which, for example, forms an electrical circuit, connects to each other.
  • FIG. 1a shows a schematic sectional view of a layer arrangement according to the first partial steps of a method according to a first exemplary embodiment
  • FIG. 1 b shows a schematic sectional view of the layer arrangement from FIG. 1 a after additional partial steps of the method according to the first exemplary embodiment, which serve for structuring the layer arrangement;
  • FIG. 1 c shows a schematic sectional view of the layer arrangement from FIG. 1 b after additional substeps of the method according to the first exemplary embodiment, which serve to form a cover layer;
  • FIG. 1 d shows a schematic sectional view of the layer arrangement from FIG. 1 c after additional substeps of the method according to the first exemplary embodiment, which serve to planarize the cover layer,
  • FIG. 2 a shows a scanning electron micrograph of a hole or via filled with a carbon layer according to the invention
  • Figure 2b is a scanning electron micrograph of the carbon layer of Figure 2a, showing the homogeneity of the carbon layer.
  • Figure 3 is a schematic sectional view of a 3D integrated electrical circuit.
  • FIG. 1a shows a schematic representation of a layer arrangement 100 according to the first partial steps of a method according to a first exemplary embodiment for producing an electrical circuit with carbon conductor structures.
  • the embodiment shown schematically in Fig.l refers to a so-called air-gap structure in which carbon-conductor structures are formed.
  • an air gap structure is understood to mean a layer arrangement in which, for the purpose of reducing the dielectric constant, and thus the parasitic capacitances, of the layer arrangement in subregions the structure, no air, but air-filled or filled with a suitable gas cavity structures, air gaps are provided.
  • some dielectric layers of a layer arrangement are replaced by cavities.
  • Each individual dielectric layer may be formed from one or more different dielectrics and / or the materials of the dielectric layers may be different for different dielectric layers. This reduces the overall permittivity of the air gap structure.
  • the layer arrangement 100 has a first layer 101, which is formed, for example, from silicon oxide.
  • a second layer 102 is formed which essentially comprises carbon as the material and from which carbon conductive structures are subsequently formed.
  • the carbon layer 102 can be formed by various processes, which are described in greater detail two of '.
  • a hydrogen atmosphere with a pressure of 0.001 bar, or 1 hectopascal is generated.
  • a carbon-containing gas such as methane (CH 4 ), ethane (C 2 H 6 ), alcohol vapor (C 2 H 5 OH) or acetylene (C 2 H 4 ) is introduced until a total pressure of about 0.6 bar, or 600 hectopascal, sets.
  • a polycrystalline carbon layer 102 deposits on the surface of the first layer 101 * .
  • the carbonaceous gas is constantly introduced during the deposition process, so that the total pressure remains substantially constant.
  • a hydrogen atmosphere of about 2 Torr to 3 Torr, preferably 2.5 Torr, which corresponds to about 3.33 hectopascal is generated.
  • a so-called photon oven is used, ie a light source which additionally provides energy.
  • a carbon-containing gas for example methane (CH 4 ), ethane (C 2 H 6 ), alcohol vapor (C 2 H 5 OH) or acetylene (C 2 H 4 ) is then in turn introduced into the hydrogen atmosphere until a partial pressure of the carbon-containing gas between 6.5 Torr and 8.5 Torr, preferably 7.5 Torr, which corresponds to about 10 hectopascals, is reached. Under these conditions, a polycrystalline carbon layer separates out. Also in this process, the carbonaceous gas is constantly introduced as long as the conformal deposition is performed.
  • the thickness of the carbon layer 102 can be adjusted in both described processes over the duration of the deposition and at the same time determines the height of the carbon conductor structures.
  • the carbon layer 102 thus deposited has a resistivity of about 1 m ⁇ cm.
  • the carbon layer 102 may be doped or intercalated.
  • the dopants customary in silicon technology such as, for example, boron, phosphorus or arsenic.
  • Intercalation is possible with metal halides such as arsenic fluoride or antimony fluoride. By doping / intercalation specific resistances up to about 1 ⁇ cm are possible.
  • thermal activation is carried out, preferably selectively by means of a laser.
  • a third layer 103 and a fourth layer 104 are subsequently formed on the carbon layer 102, both of which are made of a dielectric material, for example silicon oxide, and which serve to electrically insulate the carbon layer 102.
  • a dielectric material for example silicon oxide
  • silicon nitride may also be used as the dielectric material.
  • a material is used which has selectivity in subsequent etching steps opposite to the other material used and which can be easily separated.
  • the layer assembly 100 is patterned by forming and patterning a photoresist 105 on the fourth layer 104, thereby forming a mask.
  • the fourth layer 104, the third layer 103 and the carbon layer 102 are then etched and patterned using a conventional dry etching process, for example by means of an oxygen plasma and / or hydrogen plasma or air plasma, whereby a trench 106 is formed.
  • the photoresist layer 105 is removed and a fifth layer 107 of a dielectric material is formed.
  • the fifth layer 107 is deposited only selectively on the third layer 103, as a result of which the trench 106, which has been formed by etching back the carbon layer 102, is covered and bridged, whereby a cavity, air gap, is formed.
  • a sixth layer 108 of a dielectric material is subsequently formed. The fifth layer 107 and the sixth layer 108 both serve to cover the trench 106, which thus forms a gap or chamber in the layer assembly 100, an air gap.
  • the fifth layer 107 and the sixth layer 108 serve to isolate and passivate the layer arrangement 100, in particular the carbon layer 102.
  • the generation of self-aligning air gap structures, as shown, for example, in [5], are also performed using a suitable silicon dioxide Stack deposition in a simple manner possible.
  • the fifth layer 107 and the sixth layer 108 are planarized in one method step, preferably by means of chemical mechanical polishing.
  • a planarized surface is formed, on which Subsequently, further levels of metallization or levels can be formed with integrated electrical circuits.
  • a plurality of metallization levels which can be electrically coupled to each other, form one above the other, whereby a 3D integration of the integrated circuits can be achieved.
  • FIG. 2a shows a scanning electron micrograph (SEM image) of a layer arrangement 200 of a hole or via filled with a carbon layer according to the invention.
  • the inventive method fill narrow holes and cavities in a first layer 201 or substrate with a carbon layer 202 and thereby a vertical connection or via between two levels of a 3D integrated circuit.
  • the illustrated hole has a diameter of less than 50 nm.
  • the hole was filled by one of the methods described above for forming a polycrystalline carbon layer.
  • a carbon layer according to the invention With a carbon layer according to the invention, it is possible in a simple manner to form vertical connections which have a high aspect ratio. Aspect ratios between 100 and 400 can be achieved. Furthermore, the carbon layer according to the invention can be deposited even at high aspect ratios with a very homogeneous layer thickness, as can be seen in FIG. 2b, in particular in the detail enlargement, in which it can be seen that the thickness of the carbon layer is the same on both the substrate and the substrate , on the sidewalls of the vertical connections and on the bottoms of the vertical connections, wherein the vertical connections are formed here as narrow holes.
  • FIG. 3 shows a schematic sectional view of an SD-integrated electrical circuit.
  • a 3D integrated circuit 300 has a first wafer 301 on which, in FIG. 3, partial circuits 302 303 and 304, which can represent transistors, for example, are formed.
  • a passivation layer 305 is formed, which separates the first wafer 301 from a second wafer 306 formed on the passivation layer 305.
  • Subcircuits 307, 308 and 309 are also schematically formed on the second wafer 306.
  • Individual components or partial circuits of the two wafers are coupled together by vertical connections 310 and 311 of carbon conductors according to the invention.
  • individual components within a single plane are coupled by carbon conductor structures 312 and 313.
  • at least part of the metallization system of a 3D integrated circuit is formed by conductor structures which essentially comprise carbon as the material.
  • the invention provides an alternative to previously used materials for integrated circuit metallization structures or metallization systems.
  • carbon is used instead of the previous use of metals or, in the case of vertical connections, of doped polysilicon.
  • the carbon conductor structures are characterized by very simple and cost-effective production and easy processability, in particular, the time that is required to form a carbon layer, much less than the formation of a copper layer in Damascus process.
  • the following documents are cited:
  • first layer 201 (substrate) 202 carbon layer

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Abstract

L'invention concerne un circuit électrique comprenant au moins une structure conductrice en carbone se présentant sous la forme d'une couche qui est essentiellement constituée de carbone et qui présente une résistance spécifique inférieure à 1 mOcm.
PCT/DE2005/000905 2004-06-28 2005-05-18 Circuit electrique comprenant une structure conductrice en carbone, et procede de production d'une structure conductrice en carbone d'un circuit electrique Ceased WO2006000175A1 (fr)

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DE102004031128.5 2004-06-28
DE102004031128A DE102004031128A1 (de) 2004-06-28 2004-06-28 Elektrischer Schaltkreis mit einer Kohlenstoff-Leiterstruktur und Verfahren zum Herstellen einer Kohlenstoff-Leiterstruktur eines elektrischen Schaltkreises

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Cited By (1)

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US7978504B2 (en) 2008-06-03 2011-07-12 Infineon Technologies Ag Floating gate device with graphite floating gate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977798B2 (en) 2007-07-26 2011-07-12 Infineon Technologies Ag Integrated circuit having a semiconductor substrate with a barrier layer
US7935634B2 (en) 2007-08-16 2011-05-03 Qimonda Ag Integrated circuits, micromechanical devices, and method of making same
US8598593B2 (en) 2011-07-15 2013-12-03 Infineon Technologies Ag Chip comprising an integrated circuit, fabrication method and method for locally rendering a carbonic layer conductive

Citations (5)

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Publication number Priority date Publication date Assignee Title
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US8199560B2 (en) 2008-06-03 2012-06-12 Infineon Technologies Ag Memory device comprising select gate including carbon allotrope

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