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WO2000045441A2 - Dispositif a semiconducteur a dielectriques multiples - Google Patents

Dispositif a semiconducteur a dielectriques multiples Download PDF

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Publication number
WO2000045441A2
WO2000045441A2 PCT/DE2000/000203 DE0000203W WO0045441A2 WO 2000045441 A2 WO2000045441 A2 WO 2000045441A2 DE 0000203 W DE0000203 W DE 0000203W WO 0045441 A2 WO0045441 A2 WO 0045441A2
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric
gate
semiconductor device
layer
gate dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2000/000203
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German (de)
English (en)
Other versions
WO2000045441A3 (fr
Inventor
Harald Bachhofer
Hans Reisinger
Thomas Peter Haneder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2000045441A2 publication Critical patent/WO2000045441A2/fr
Publication of WO2000045441A3 publication Critical patent/WO2000045441A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered

Definitions

  • the present invention relates to a semiconductor device with a multiple dielectric, in particular an ONO triple dielectric with a semiconductor substrate of a first conductivity type; a first doping region of a second conductivity type provided in the semiconductor substrate; a second doping region of the second conductivity type provided in the semiconductor substrate; a channel region lying between the first and the second doping region; a gate dielectric lying above the channel region and having at least three layers; and a gate connection provided over the gate dielectric.
  • MOS field-effect transistors with ONO triple dielectric (S ⁇ 0 2 - S ⁇ 3 N 4 - S ⁇ 0 2 ) m of silicon semiconductor technology are used as non-volatile memories (EEPROM).
  • EEPROM non-volatile memories
  • Such so-called SONOS transistors have numerous advantages over floating gate transistors. On the one hand, they are characterized by a much lower defect density and a simpler cell structure. On the other hand, a defect in the gate dielectric does not lead to a complete loss of the stored charge, since in contrast to floating gate transistors, the charge is stored in a non-conductive layer.
  • Floating gate transistors can reduce their thickness due to decreasing reliability with thinner tunnel oxide
  • the object on which the present invention is based is to reduce the programming voltages of SONOS transistors even further, or optionally to increase their data retention time or erasure speed.
  • the semiconductor device according to the invention has the advantage over the known approaches that a lower voltage drops across the top layer of the gate dielectric and thus less undesired leakage currents flow there.
  • the idea on which the present invention is based is that a semiconductor device with a multiple dielectric, in particular an ONO triple dielectric, is provided in the gate stack.
  • the bottom layer of the gate Dielectric has a much smaller dielectric constant than the top layer of the gate dielectric.
  • the gate dielectric has a Si 2 layer as the bottom layer and an Si 3 N 4 layer above it.
  • the gate dielectric has a layer made of at least one of the following materials as the top layer: Al 2 0 3 , HfO, Ce0 2 / Zr0 2 , Ta 2 0 5 , Y 2 0 3 , T ⁇ 0 2 .
  • the gate connection has at least one of the following materials: Pt, Au, W, Ir or silicides or TiN or polyk ⁇ stallines p-doped silicon.
  • it is a MOS field-effect transistor using silicon technology.
  • 1 shows a schematic representation of an embodiment of the semiconductor device according to the invention in the form of a MOS field-effect transistor
  • 2 shows the band model of a field-free SONOS structure (flat band state) with p-substrate and n + gate;
  • FIG. 4 shows the state of a SONOS structure with a negative external voltage applied to its gate.
  • Fig. 2 shows the band model of a field-free SONOS structure (flat band state) with p-substrate and n + gate, as known from J. T. Wallmark, J. H. Scott, RCA Rev., Vol. 30, 335-381 (1969).
  • the conduction band is higher in the nitride and the valence band is lower than in the substrate or in the poly gate. Therefore, no charge injection into the nitride will occur without external voltage being applied.
  • FIG. 3 and FIG. 4 characterize the state of a SONOS
  • the lower thickness of the bottom oxide compared to that of the top oxide makes it possible to inject charge carriers preferably from the substrate and not from the gate, as described in more detail below.
  • an inversion layer is formed on the semiconductor surface and electrons can tunnel through the thin botom oxide into the conduction band in the nitride drawn down by the electrical field (1). There they are bound to localized areas of detention and migrate further into the nitride volume by means of the Pool-Frenkel line. This results in the nitride layer being charged with electrons. ge. This results in a shift in the flat ribbon tension in the positive direction. Electrons that drift through the electrical field in the nitride to the top oxide partially tunnel through the top oxide and flow off via the gate (2).
  • holes are injected from the valence band of the polysilicon through the top oxide ms valence band of the nitride (3).
  • the charge projection of holes is much less likely due to the larger oxide thickness and higher potential bamers.
  • (1) and (2) increase. If these current contributions are equal, no additional charge ms of nitride is injected net, i.e. the shift of the flat ribbon tension goes m saturation.
  • perforators tunnel from the valence band of the substrate ms valence band of the nitride (4) and recombine with the already injected electrons and thus lead to the deletion of the stored charge. It is also possible that electrons injected by writing previously ms nitride tunnel back ms substrate (5).
  • the ribbon tension and thus the threshold voltage is shifted in the negative direction. Holes that move in the direction of the top oxide and tunnel through the gate are negligible (6). Rather, electrons can tunnel from the conduction band of the poly-gate nitride (7).
  • the voltage applied In order to reset the threshold voltage to the original value (before writing), the voltage applied must not exceed a certain value. This prevents shorter deletion times.
  • the triple dielectric consists of the layer sequence S ⁇ 0 2 - S ⁇ 3 N - S ⁇ 0 2 .
  • the electric field m bottom and top oxide is therefore the same size.
  • the electric field in the botomium oxide decreases and increases in the top oxide.
  • the Gaussian theorem provides:
  • E ⁇ op-Ox ⁇ d / EBottom-Oxid ⁇ Top-Oxid ' ⁇ Bot om-Oxxd X l
  • E Top _ 0 ⁇ i d the electric field of the top oxide
  • E Bo ttom-o ⁇ id the electric field of the bottom oxide
  • ⁇ Top . 0 ⁇ id the dielectric constant of the top oxide
  • ⁇ Bo ttom-oxide the dielectric constant of the bottom-oxide call.
  • Tunnel currents through the top oxide are described either by Fowler-Nordheim-, modified Fowler-Nordheim- or direct doing no, depending on the existing electrical field and barrier height.
  • the tunnel current is mathematically reduced by 6 orders of magnitude.
  • the thickness of the bottom oxide is particularly important for data retention (retention time). Due to their own field, charge carriers from the nitride tunnel through the thin bottom oxide back into the substrate. If the thickness of the bottom oxide is increased from 2 nm to 3 nm, for example, data storage that is orders of magnitude better is possible. To ensure the same programming times, the voltage has to be raised slightly, but still remains below that of conventional SONOS transistors.
  • FIG. 1 shows a schematic representation of an embodiment of the semiconductor device according to the invention in the form of a MOS field-effect transistor.
  • 10 denote a p-type silicon substrate, 20 an n + Source, 25 a channel region, 30 an n + drain, 40 a bottom oxide, 50 a Si 3 N 4 dielectric, 60 a top oxide, 70 a gate connection and U G a gate supply voltage (substrate 10 lies in this example to ground).
  • a high dielectric constant relative to Si0 2 which forms the bottom dielectric
  • the triple dielectric of such a SONOS transistor thus has the following structure:
  • Si0 2 - Si 3 N 4 - (A1 2 0 3 and / or HfO and / or Ce0 2 and / or Zr0 2 and / or Ta 2 0 5 and / or Y 2 0 3 and / or Ti0 2 ).
  • gate connection 70 Materials with high work functions are preferably used as gate connection 70.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif à semiconducteur présentant des diélectriques multiples, notamment un triple diélectrique ONO, un substrat semiconducteur (10) d'un premier type de conduction; une première zone de dopage (20) prévue sur le substrat semiconducteur (10) et présentant un deuxième type de conduction; une deuxième zone de dopage (30) du deuxième type de conduction, prévue sur le substrat semiconducteur (10); une zone de canal (25) située entre la première et la deuxième zone de dopage (20, 30); un diélectrique de grille (40, 50, 60) situé sur la zone de canal (25) et présentant au moins trois couches; et une borne de grille (70) prévue sur le diélectrique de grille (40, 50, 60). La couche inférieure (40) du diélectrique de grille (40, 50, 60) présente une constante diélectrique sensiblement inférieure à celle de la couche supérieure (60) dudit diélectrique de grille (40, 50, 60).
PCT/DE2000/000203 1999-01-29 2000-01-25 Dispositif a semiconducteur a dielectriques multiples Ceased WO2000045441A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19903598.9 1999-01-29
DE19903598A DE19903598A1 (de) 1999-01-29 1999-01-29 Halbleitervorrichtung mit Mehrfachdielektrikum

Publications (2)

Publication Number Publication Date
WO2000045441A2 true WO2000045441A2 (fr) 2000-08-03
WO2000045441A3 WO2000045441A3 (fr) 2001-03-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/000203 Ceased WO2000045441A2 (fr) 1999-01-29 2000-01-25 Dispositif a semiconducteur a dielectriques multiples

Country Status (2)

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DE (1) DE19903598A1 (fr)
WO (1) WO2000045441A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6914292B2 (en) 2001-11-27 2005-07-05 Infineon Technologies Ag Floating gate field-effect transistor
CN100524767C (zh) * 2002-03-29 2009-08-05 旺宏电子股份有限公司 一种俘获式非易失存储单元及使用其进行数据编程的方法
US7790516B2 (en) 2006-07-10 2010-09-07 Qimonda Ag Method of manufacturing at least one semiconductor component and memory cells

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030062567A1 (en) * 2001-09-28 2003-04-03 Wei Zheng Non volatile dielectric memory cell structure with high dielectric constant capacitive coupling layer
US6717226B2 (en) * 2002-03-15 2004-04-06 Motorola, Inc. Transistor with layered high-K gate dielectric and method therefor
US6812517B2 (en) * 2002-08-29 2004-11-02 Freescale Semiconductor, Inc. Dielectric storage memory cell having high permittivity top dielectric and method therefor
US7135370B2 (en) 2004-07-01 2006-11-14 Freescale Semiconductor, Inc. Dielectric storage memory cell having high permittivity top dielectric and method therefor
DE102005008321B4 (de) * 2005-02-23 2008-09-25 Qimonda Ag Mittels Feldeffekt steuerbares Halbleiterspeicherelement mit verbessertem Einfangdielektrikum

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4250206A (en) * 1978-12-11 1981-02-10 Texas Instruments Incorporated Method of making non-volatile semiconductor memory elements
US4804640A (en) * 1985-08-27 1989-02-14 General Electric Company Method of forming silicon and aluminum containing dielectric film and semiconductor device including said film
JP3635681B2 (ja) * 1994-07-15 2005-04-06 ソニー株式会社 バイアス回路の調整方法、電荷転送装置、及び電荷検出装置とその調整方法
JP2871530B2 (ja) * 1995-05-10 1999-03-17 日本電気株式会社 半導体装置の製造方法
JPH10178170A (ja) * 1996-12-19 1998-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US6015739A (en) * 1997-10-29 2000-01-18 Advanced Micro Devices Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6914292B2 (en) 2001-11-27 2005-07-05 Infineon Technologies Ag Floating gate field-effect transistor
CN100524767C (zh) * 2002-03-29 2009-08-05 旺宏电子股份有限公司 一种俘获式非易失存储单元及使用其进行数据编程的方法
US7790516B2 (en) 2006-07-10 2010-09-07 Qimonda Ag Method of manufacturing at least one semiconductor component and memory cells

Also Published As

Publication number Publication date
WO2000045441A3 (fr) 2001-03-29
DE19903598A1 (de) 2000-08-10

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