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WO2000045441A3 - Dispositif a semiconducteur a dielectriques multiples - Google Patents

Dispositif a semiconducteur a dielectriques multiples Download PDF

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Publication number
WO2000045441A3
WO2000045441A3 PCT/DE2000/000203 DE0000203W WO0045441A3 WO 2000045441 A3 WO2000045441 A3 WO 2000045441A3 DE 0000203 W DE0000203 W DE 0000203W WO 0045441 A3 WO0045441 A3 WO 0045441A3
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric
semiconductor device
gate dielectric
semiconductor substrate
conduction type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2000/000203
Other languages
German (de)
English (en)
Other versions
WO2000045441A2 (fr
Inventor
Harald Bachhofer
Hans Reisinger
Thomas Peter Haneder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2000045441A2 publication Critical patent/WO2000045441A2/fr
Publication of WO2000045441A3 publication Critical patent/WO2000045441A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif à semiconducteur présentant des diélectriques multiples, notamment un triple diélectrique ONO, un substrat semiconducteur (10) d'un premier type de conduction; une première zone de dopage (20) prévue sur le substrat semiconducteur (10) et présentant un deuxième type de conduction; une deuxième zone de dopage (30) du deuxième type de conduction, prévue sur le substrat semiconducteur (10); une zone de canal (25) située entre la première et la deuxième zone de dopage (20, 30); un diélectrique de grille (40, 50, 60) situé sur la zone de canal (25) et présentant au moins trois couches; et une borne de grille (70) prévue sur le diélectrique de grille (40, 50, 60). La couche inférieure (40) du diélectrique de grille (40, 50, 60) présente une constante diélectrique sensiblement inférieure à celle de la couche supérieure (60) dudit diélectrique de grille (40, 50, 60).
PCT/DE2000/000203 1999-01-29 2000-01-25 Dispositif a semiconducteur a dielectriques multiples Ceased WO2000045441A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19903598.9 1999-01-29
DE19903598A DE19903598A1 (de) 1999-01-29 1999-01-29 Halbleitervorrichtung mit Mehrfachdielektrikum

Publications (2)

Publication Number Publication Date
WO2000045441A2 WO2000045441A2 (fr) 2000-08-03
WO2000045441A3 true WO2000045441A3 (fr) 2001-03-29

Family

ID=7895824

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/000203 Ceased WO2000045441A2 (fr) 1999-01-29 2000-01-25 Dispositif a semiconducteur a dielectriques multiples

Country Status (2)

Country Link
DE (1) DE19903598A1 (fr)
WO (1) WO2000045441A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7790516B2 (en) 2006-07-10 2010-09-07 Qimonda Ag Method of manufacturing at least one semiconductor component and memory cells

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030062567A1 (en) * 2001-09-28 2003-04-03 Wei Zheng Non volatile dielectric memory cell structure with high dielectric constant capacitive coupling layer
DE10158019C2 (de) 2001-11-27 2003-09-18 Infineon Technologies Ag Floatinggate-Feldeffekttransistor
US6717226B2 (en) * 2002-03-15 2004-04-06 Motorola, Inc. Transistor with layered high-K gate dielectric and method therefor
US6690601B2 (en) * 2002-03-29 2004-02-10 Macronix International Co., Ltd. Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same
US6812517B2 (en) * 2002-08-29 2004-11-02 Freescale Semiconductor, Inc. Dielectric storage memory cell having high permittivity top dielectric and method therefor
US7135370B2 (en) 2004-07-01 2006-11-14 Freescale Semiconductor, Inc. Dielectric storage memory cell having high permittivity top dielectric and method therefor
DE102005008321B4 (de) * 2005-02-23 2008-09-25 Qimonda Ag Mittels Feldeffekt steuerbares Halbleiterspeicherelement mit verbessertem Einfangdielektrikum

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4250206A (en) * 1978-12-11 1981-02-10 Texas Instruments Incorporated Method of making non-volatile semiconductor memory elements
US4804640A (en) * 1985-08-27 1989-02-14 General Electric Company Method of forming silicon and aluminum containing dielectric film and semiconductor device including said film
EP0692825A2 (fr) * 1994-07-15 1996-01-17 Sony Corporation MISFET analogique avec ajusteur de la tension de seuil
EP0742593A2 (fr) * 1995-05-10 1996-11-13 Nec Corporation Dispositif semi-conducteur avec isolant structure multicouche et méthode de fabrication
JPH10178170A (ja) * 1996-12-19 1998-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US6015739A (en) * 1997-10-29 2000-01-18 Advanced Micro Devices Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4250206A (en) * 1978-12-11 1981-02-10 Texas Instruments Incorporated Method of making non-volatile semiconductor memory elements
US4804640A (en) * 1985-08-27 1989-02-14 General Electric Company Method of forming silicon and aluminum containing dielectric film and semiconductor device including said film
EP0692825A2 (fr) * 1994-07-15 1996-01-17 Sony Corporation MISFET analogique avec ajusteur de la tension de seuil
EP0742593A2 (fr) * 1995-05-10 1996-11-13 Nec Corporation Dispositif semi-conducteur avec isolant structure multicouche et méthode de fabrication
JPH10178170A (ja) * 1996-12-19 1998-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US6015739A (en) * 1997-10-29 2000-01-18 Advanced Micro Devices Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 11 30 September 1998 (1998-09-30) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7790516B2 (en) 2006-07-10 2010-09-07 Qimonda Ag Method of manufacturing at least one semiconductor component and memory cells

Also Published As

Publication number Publication date
DE19903598A1 (de) 2000-08-10
WO2000045441A2 (fr) 2000-08-03

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