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WO1986005637A1 - Circuit de selectivite automatique pour recepteurs fm - Google Patents

Circuit de selectivite automatique pour recepteurs fm Download PDF

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Publication number
WO1986005637A1
WO1986005637A1 PCT/DE1986/000121 DE8600121W WO8605637A1 WO 1986005637 A1 WO1986005637 A1 WO 1986005637A1 DE 8600121 W DE8600121 W DE 8600121W WO 8605637 A1 WO8605637 A1 WO 8605637A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
circuit
circuit according
counter
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE1986/000121
Other languages
German (de)
English (en)
Inventor
Jens Hansen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HuC Elektronik Hansen and Co
Original Assignee
HuC Elektronik Hansen and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HuC Elektronik Hansen and Co filed Critical HuC Elektronik Hansen and Co
Publication of WO1986005637A1 publication Critical patent/WO1986005637A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02—Automatic frequency control
    • H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
    • H03J7/08—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using varactors, i.e. voltage variable reactive diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/001—Details of arrangements applicable to more than one type of frequency demodulator
    • H03D3/003—Arrangements for reducing frequency deviation, e.g. by negative frequency feedback
    • H03D3/005—Arrangements for reducing frequency deviation, e.g. by negative frequency feedback wherein the demodulated signal is used for controlling a bandpass filter

Definitions

  • the invention relates to a circuit for automatic tuning for FM receivers according to the preamble of the main claim.
  • the received signal is converted via one or more mixing stages into intermediate frequency signals which are fed to a demodulator via intermediate frequency filters, in which they are converted into low-frequency signals.
  • intermediate frequency filters in which they are converted into low-frequency signals.
  • the filters In order to keep interference as low as possible, efforts are made to design the filters to be narrow-band (DE-OS 30 48 263), an after-control voltage being derived from the output voltage of the demodulator, which shifts the resonance frequency of the narrow-band intermediate-frequency filter connected upstream of the demodulator in such a way that the respective instantaneous value of the intermediate frequency always within the pass range of the filter. Since these tracking filters are very narrow-band, it is important that the transmitter to be received is very well tuned. Manual tuning is generally not enough for good reception.
  • the invention is therefore based on the object of providing a circuit arrangement for automatic tuning for FM receivers, in particular for receivers with narrow-band tracking filters, which ensures in a precise and simple manner that the carrier lies in the resonance range of the filter.
  • the analog and digital circuit arrangement offers a fast and precise readjustment of the intermediate frequency in the resonance range of the filter or filters in an indirect and direct manner, so that a flawless and sharp reception of the desired transmitter is ensured.
  • the oscillator maintains the frequency value immediately before the shutdown by a storage device and thus does not run out of the set reception area.
  • a device is provided in the stand-by mode, which sweeps the tracking filter by continuously increasing and / or decreasing the oscillator frequency over the permissible frequency tolerance range of the channel.
  • Fig. 1 shows a first embodiment of the circuit configuration of the present invention
  • Fig. 2 shows a second embodiment of the circuit configuration of the present invention.
  • Fig. 3 shows a circuit for gradually changing the oscillator frequency.
  • 10 denotes the mixer stage, to which the received signal indicated by the arrow is supplied, which comes directly from the receive stage or has been converted into intermediate frequency signals via one or more mixer and filter stages.
  • the output of the mixer stage 10 is connected to an IF filter 13, which consists, for example, of several tracking filters.
  • the IF filter 13 is connected to the input of a demodulator 14, at whose output the low-frequency signals are present, which consist of an alternating voltage superimposed on a direct voltage.
  • the output signals of the demodulator 14 are converted in a known manner via a loudspeaker 15 into acoustic signals.
  • the output of the demodulator is also connected to a low-pass filter 16 with a large time constant, which is connected via an inverter 17 to the actual value input of an inverting integral controller 18.
  • the setpoint input of the integral controller 18 is connected to a voltage divider 19 which specifies a fixed DC voltage.
  • the output of the integral regulator 18 is connected to the voltage-controlled oscillator 12 via a sample and hold circuit.
  • the output of the IF filter 13 leads to a rectification circuit 21 which is connected to a threshold switch 22 designed as a Schmitt trigger.
  • the output of the threshold switch 22 is connected to an input of the sasple and hold circuit 20.
  • the operation of the circuit arrangement according to FIG. 1 will be described in the following.
  • the DC voltage contained in the output signal of the demodulator 14, by which the AC component fluctuates, is a measure of the position of the intermediate frequency signal.
  • the low-pass filter 16 with a large time constant filters this DC component out of the output signal of the demodulator 14, which forms the actual value at the integral controller 18 as a DC voltage via the inverter 17.
  • the fixed predetermined target voltage corresponding to the target IF is generated by the voltage divider 19 and the
  • the integral controller 18 supplies a control signal which is fed via the sample and hold circuit 20 to the voltage-controlled oscillator 12, the output frequency of which changes depending on the control signal, as a result of which the frequency of the intermediate frequency signal changes in Direction of the target frequency shifts.
  • This circuit described in this way forms a closed control loop, which has the effect that the intermediate frequency signal is always in the resonance range of the IF filter 13.
  • the IF signal would run out of the resonance range of the IF filter, for example in the case of a field strength reduction due to shadowing, since the control voltage assumes an undefined value due to the noise. After the field strength has increased again (end of shadowing), the previously set transmitter could then no longer be received.
  • the sample and hold circuit 20 is provided.
  • the output signal of the IF filter 13, which is a measure of the field strength, is rectified via the rectifier circuit 21 and fed to the threshold switch 22. If the rectified voltage falls below the threshold value specified by the threshold switch 22, that is to say if the field strength drops below a certain value, the logic output state of the threshold switch 22 changes from 0 to 1 or vice versa.
  • This change in the logic state is communicated to the control input of the sample and hold circuit 20, which stores the control value currently being applied by the integral controller 18 and supplies it to the voltage-controlled oscillator 12 until the field strength increases again and the threshold value switch 22 again changes its logic output state.
  • the intermediate frequency signal remains in the set transmission range even when the field strength is reduced.
  • the DC voltage component of the output signal of the demodulator 14 can change to a small extent due to different tolerances of the components during the lifetime of the receiver, so that the setpoint on the integral controller must be changed accordingly.
  • This is achieved by a potentiometer 23 provided in the voltage divider 19, which allows the setpoint voltage at the input of the controller 18 to be adjusted by a small amount.
  • Another way to compensate for the different tolerances is to change the Operating point of the IF filter, which usually has capacitance diodes.
  • the operating point is set via a voltage divider, which can also be made slightly changeable by providing a variable resistor.
  • the IF filter 13 is shown as a plurality of tracking filters arranged one behind the other, the control or regulation of these tracking filters, as in FIG. 1, not being shown, since it is not the subject of the present application.
  • the output of the IF filter is connected via a limiter amplifier 25 to the counting input of a first counter 26, the output of which is connected to the reset input of a second counter 27, this counter receiving pulses with a predetermined target frequency, which is indicated by arrow 28 .
  • the output of the second counter 27 is connected to the reset input of the first counter 26.
  • the output of the first counter 26 is connected to one input of an AND gate 29, the other input of which is the output of the threshold switch 22. Accordingly, the output of the second counter 27 is connected to a UBD gate 30, which is also connected to the output of the threshold switch 22.
  • the outputs of the AND gates 29, 30 are each connected to a first and a second control input 31, 32 of a programmable divider 33.
  • the divider 33 is part of a PLL circuit 34, which has a phase comparator 35, a low-pass filter 36 and a voltage-controlled oscillator 37 in a known manner.
  • the divider 33 is connected to an input of the phase comparator 35, at the other input of which there is a pulse source 38 which supplies pulses with a low target frequency of the so-called reference frequency.
  • the output of the PLL circuit 34 is optionally connected to the mixer 10 via a further divider 39.
  • the modulated intermediate frequency signal is at the output of the IF filter.
  • This alternating signal is sent to the limiter amplifier 25, at the output of which the intermediate frequency is present as a square-wave signal which is passed to the first counter 26.
  • the second counter 27 receives the pulses 28 with the target frequency for the intermediate frequency signal.
  • the pulses are counted both by the counter 26 for frequency averaging and by the counter 27 during a fixed predetermined counting period which is determined by a predetermined final counter reading, the predetermined final counter readings for both counters being different depending on the target frequency supplied. If the final counter reading is reached, an output pulse is delivered. If, for example, the counter 27 reaches the fixed predetermined reading before the first counter 26, the pulse at the output of the second counter 27 resets the first counter 26. before it reaches the predetermined counter reading. The same applies vice versa when the first counter 26 first runs to the final counter reading.
  • the relevant output signal is passed on via one of the AND gates 29, 30 and reaches one of the control inputs 31, 32 of the programmable divider 33.
  • the divider divides the output frequency of the voltage-controlled oscillator 37 down to the reference frequency, whereby when a pulse is applied to the control input 31, the division factor is increased step by step, ie incremented and when output pulses are applied to the control input 32, the division factor of the divider 33 is reduced by one step, i.e. is decremented.
  • the frequency control of the oscillator 37 by incrementing or decrementing the divider 33 is such that the intermediate frequency is regulated to the target frequency applied to the counter 27.
  • the frequency of the pulse source 38 should be very low. If the reference frequency is low, a low-pass filter with a low cut-off frequency must be selected so that the control time is also relatively long. In order to achieve a faster transient response, a divider 39 can be provided between the PLL circuit 34 and the mixing stage 10. which divides the output frequency of the PLL circuit 34 down. This measure allows a higher frequency to be selected for the reference frequency, so that the settling time of the low pass 36 is shortened.
  • the exemplary embodiment according to FIG. 2 is preferably used for radio in radio receivers in which only noise and no sufficiently high field strength is available in stand-by mode.
  • FIG. 3 A circuit arrangement for implementation is shown in FIG. 3, the circuit serving as an additional circuit to the control circuit according to FIG. 2 and some components from FIG. 2 are also shown here.
  • the threshold switch 22, not shown, is connected to a timer 40, the output of which is connected to the one input of two AND gates 41.
  • At the second inputs of the AND gates 41, 42 are the outputs of two further AND gates 43, 44, one input of which is connected to the output of a divider 45 connected to a pulse source, for example the pulse source 38.
  • a further divider 46 At the other inputs there is the output of a further divider 46 with a smaller division ratio, an inverter 47 being interposed to the AND gate 44.
  • divider 45 At the output of divider 45 there is a pulse train with a higher frequency than the pulse train at the output of divider 46.
  • the outputs of the AND gates 43, 44 each provide one for the other through the divider 46 given time a pulse train. If there is a sufficiently high field strength at the output of the IF filter 13, these pulse sequences are blocked at the AND gates 41, 42. If the field strength is below the value specified by the threshold switch 22 for a period of time specified by the timer 40, the AND gates 41, 42 switch through and the pulse trains pass via the OR gates 48, 49 to the control inputs 31, 32 of the programmable one Divider 33 of the PLL circuit 34.
  • the set channel range is traversed step by step from low frequencies to higher frequencies, while it is traversed step by step from the high frequencies to lower frequencies by the pulse train at the control input 32. If a transmitter is found, the field strength increases and the threshold switch 22 switches off the wobble circuit according to FIG. 3.
  • this circuit according to FIG. 3 can be used not only for radio devices but also for other receivers.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Un circuit de sélectivité automatique est utilisé pour des récepteurs FM, en particulier pour des récepteurs ayant des filtres de retransmission à bande étroite. Ces récepteurs comprennent généralement un étage de changement de fréquence (10) commandé par un oscillateur (12), au moins un filtre (13) pour filtrer les fréquences intermédiaires et un démodulateur (14). La sélectivité est effectuée par une boucle fermée de régulation. Dans un mode de réalisation, il se forme une valeur moyenne de la tension de sortie du démodulateur, qui est comparée à une tension prescrite (U prescrite) qui donne un niveau de référence pour les signaux de fréquence intermédiaire. La fréquence de l'oscillateur est réglée en fonction de la différence entre la valeur moyenne et la tension prescrite. Dans un autre mode de réalisation , il se forme une valeur moyenne de la fréquence intermédiaire, qui est comparée à une fréquence prescrite qui donne le niveau de référence de la fréquence intermédiaire, la fréquence de l'oscillateur étant réglée en fonction de la différence entre la valeur moyenne de la fréquence intermédiaire et la fréquence prescrite.
PCT/DE1986/000121 1985-03-21 1986-03-18 Circuit de selectivite automatique pour recepteurs fm Ceased WO1986005637A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19853510559 DE3510559A1 (de) 1985-03-21 1985-03-21 Schaltung zur automatischen scharfabstimmung fuer fm-empfaenger
DEP3510559.3 1985-03-21

Publications (1)

Publication Number Publication Date
WO1986005637A1 true WO1986005637A1 (fr) 1986-09-25

Family

ID=6266110

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1986/000121 Ceased WO1986005637A1 (fr) 1985-03-21 1986-03-18 Circuit de selectivite automatique pour recepteurs fm

Country Status (4)

Country Link
EP (1) EP0217839A1 (fr)
AU (1) AU5589586A (fr)
DE (1) DE3510559A1 (fr)
WO (1) WO1986005637A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2220536A (en) * 1988-06-23 1990-01-10 Toshiba Kk Afc systems
EP0362949A3 (fr) * 1988-10-07 1990-10-31 Philips Patentverwaltung GmbH Montage de circuit pour la démodulation de signaux modulés en fréquence
US5062427A (en) * 1988-05-06 1991-11-05 Kabushiki Kaisha Toshiba Ultrasonic doppler apparatus
GB2244877A (en) * 1988-05-28 1991-12-11 Motorola Israel Ltd Control of oscillators
US6781474B2 (en) * 2002-02-18 2004-08-24 Freescale Semiconductor, Inc. Apparatus and method for tuning a filter

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3164777A (en) * 1959-02-18 1965-01-05 Patelhold Patentverwertung Means for the production of a voltage which depends upon the difference between two frequencies
DE2115683A1 (de) * 1971-03-31 1972-10-19 Siemens Ag Oszillatorschaltungsanordnung
FR2192412A1 (fr) * 1972-07-08 1974-02-08 Loewe Opta Gmbh
DE2624787A1 (de) * 1975-06-02 1976-12-16 Onkyo Kk Vorrichtung zum frequenzvergleich
FR2497039A1 (fr) * 1980-12-20 1982-06-25 Blaupunkt Werke Gmbh Appareil recepteur de radiodiffusion
JPS5992617A (ja) * 1982-11-19 1984-05-28 Hitachi Ltd 電子同調受信機
DE3317158A1 (de) * 1983-05-11 1984-11-15 Robert Bosch Gmbh, 7000 Stuttgart Hochfrequenzempfangsschaltung

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3164777A (en) * 1959-02-18 1965-01-05 Patelhold Patentverwertung Means for the production of a voltage which depends upon the difference between two frequencies
DE2115683A1 (de) * 1971-03-31 1972-10-19 Siemens Ag Oszillatorschaltungsanordnung
FR2192412A1 (fr) * 1972-07-08 1974-02-08 Loewe Opta Gmbh
DE2624787A1 (de) * 1975-06-02 1976-12-16 Onkyo Kk Vorrichtung zum frequenzvergleich
FR2497039A1 (fr) * 1980-12-20 1982-06-25 Blaupunkt Werke Gmbh Appareil recepteur de radiodiffusion
JPS5992617A (ja) * 1982-11-19 1984-05-28 Hitachi Ltd 電子同調受信機
DE3317158A1 (de) * 1983-05-11 1984-11-15 Robert Bosch Gmbh, 7000 Stuttgart Hochfrequenzempfangsschaltung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENTS ABSTRACTS OF JAPAN, Volume 8, No. 206 (E-267) (1643) 20 September 1984 & JP, A, 59092617 (Hitachi Seisakusho K.K.) 28 May 1984, see column 7, line 13 - column 10, line 8; figure 2 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5062427A (en) * 1988-05-06 1991-11-05 Kabushiki Kaisha Toshiba Ultrasonic doppler apparatus
GB2244877A (en) * 1988-05-28 1991-12-11 Motorola Israel Ltd Control of oscillators
GB2244877B (en) * 1988-05-28 1992-07-22 Motorola Israel Ltd Automatically self-calibrating oscillators in heterodyned radio receivers
GB2220536A (en) * 1988-06-23 1990-01-10 Toshiba Kk Afc systems
GB2220536B (en) * 1988-06-23 1992-06-03 Toshiba Kk Automatic frequency control apparatus for fm receivers
EP0362949A3 (fr) * 1988-10-07 1990-10-31 Philips Patentverwaltung GmbH Montage de circuit pour la démodulation de signaux modulés en fréquence
US6781474B2 (en) * 2002-02-18 2004-08-24 Freescale Semiconductor, Inc. Apparatus and method for tuning a filter

Also Published As

Publication number Publication date
EP0217839A1 (fr) 1987-04-15
DE3510559A1 (de) 1986-09-25
AU5589586A (en) 1986-10-13

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