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US20050218513A1 - Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus - Google Patents

Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus Download PDF

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Publication number
US20050218513A1
US20050218513A1 US11/091,918 US9191805A US2005218513A1 US 20050218513 A1 US20050218513 A1 US 20050218513A1 US 9191805 A US9191805 A US 9191805A US 2005218513 A1 US2005218513 A1 US 2005218513A1
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Prior art keywords
wire
patterns
semiconductor element
connecting terminals
solder resist
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US11/091,918
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English (en)
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Toshiharu Seko
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Sharp Corp
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Individual
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Assigned to SHARP KABUSHIKI KAISHA reassignment SHARP KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEKO, TOSHIHARU
Publication of US20050218513A1 publication Critical patent/US20050218513A1/en
Priority to US12/068,498 priority Critical patent/US7750457B2/en
Abandoned legal-status Critical Current

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    • H10W95/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10W46/00—
    • H10W74/012—
    • H10W74/15—
    • H10W99/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H10W46/101—
    • H10W46/601—
    • H10W46/603—
    • H10W70/688—
    • H10W72/01308—
    • H10W72/0711—
    • H10W72/07178—
    • H10W72/072—
    • H10W72/07236—
    • H10W72/073—
    • H10W72/07311—
    • H10W72/241—
    • H10W72/352—
    • H10W72/354—
    • H10W72/387—
    • H10W72/856—
    • H10W72/931—
    • H10W74/00—
    • H10W90/724—
    • H10W90/734—

Definitions

  • the present invention relates to (i) a semiconductor apparatus having a flexible wire substrate on which a semiconductor element is bonded and mounted in accordance with the COF (Chip On Film) method; (ii) a manufacturing method thereof, (iii) a semiconductor module apparatus using the semiconductor apparatus, and (iv) a wire substrate used for the semiconductor apparatus.
  • COF Chip On Film
  • TCP TCP type semiconductor apparatus
  • COF COF type semiconductor apparatus
  • TCP TCP type semiconductor apparatus
  • COF COF type semiconductor apparatus
  • the TCP is obtained by installing (mounting), by using the TCP (Tape Carrier Package) method, a semiconductor element on an insulating tape that is a base material of the flexible wire substrate.
  • the COF is obtained by installing (mounting), by using the COF (Chip On Film) method, a semiconductor element on such an insulating tape.
  • the TCP has an aperture portion (through hole) that is termed a “device hole” and that is provided beforehand in the aforementioned semiconductor element installation portion of the insulating tape, and the semiconductor element is bonded with front ends of wire patterns protruding, in a cantilever manner, in the aperture portion.
  • the COF does not have such an aperture portion (device hole) for mounting a semiconductor element, and the semiconductor element is bonded and mounted on a surface of the insulating tape.
  • the insulating tape used in the COF is a freely foldable thin film insulating tape.
  • the insulating tape (the flexible wire substrate) has an external conductive connector portion that is connected to external electronic devices such as a liquid crystal panel and a print substrate. Note that, for securing insulation, a solder resist is applied to a pattern exposed portion excluding (i) the connection region where the wire patterns are connected with the semiconductor element, and (ii) the external conductive connector portion.
  • the external conductive connector portion, and the connection portion connecting to the semiconductor element are each required to have fine pitches, and the tape carrier (insulating tape), the wire pattern, and the like are each required to be thinner. Further, for reduction of the pitch of the inner leads (the connection portion to the semiconductor element) of the wire patterns, each inner lead is required to be narrower and thinner.
  • Patent document 1 Japanese Examined Patent Publication Tokukouhei 2-7180 published on Feb. 15, 1990; hereinafter, referred to as “Patent document 1”
  • Patent document 2 Japanese Laid-Open Patent Publication Tokukaisho 63-151033/1988
  • Each of the connecting-sealing methods such as the NCP etc., is a method for connecting protruding electrodes (connecting terminals) of a semiconductor element to respective wire patterns (connecting terminals) of a flexible wire substrate, and for sealing the protruding electrode and the wire pattern with a photo-curable or thermo-curable resin, each of which serves as an insulating resin and is provided beforehand between the semiconductor element and the flexible wire substrate by applying the insulating resin to a surface of an insulating tape.
  • Patent document 1 shows an example using the MBB as follows. That is, a photo-curable or thermo-curable resin is applied to those wire patterns of the wire substrate which correspond to the protruding electrodes of the semiconductor element, respectively.
  • the protruding electrodes and the wire patterns are aligned with each other, and the insulating resin between the protruding electrodes and the wire patterns is pushed out by applied pressure, so that electric conduction between the protruding electrode and the wire pattern is attained only by way of the pressure.
  • the insulating resin thus pushed out extends to a periphery of the semiconductor element, and thereafter is cured by light or heat so as to fix the semiconductor element to the wire substrate and electrically connect the semiconductor element to the wire substrate.
  • Patent document 2 shows another example using the MBB as follows. That is, a thermo-curable resin is applied to those wire patterns of the wire substrate which correspond to the respective protruding electrodes of the semiconductor elements.
  • the semiconductor element is combined, by applying pressure to the semiconductor element with the use of a pulse heating tool, with the wire substrate such that the protruding electrodes are aligned with the wire patterns.
  • the thermo-curable resin on the wire patterns is pushed out by the applied pressure. Thereafter, under application of pressure, an electric current is applied to the pulse heating tool so that the thermo-curable resin is heated and cured. This fixes the semiconductor element on the wire substrate, and electrically connects the protruding electrodes with the wire patterns.
  • Patent documents 1 nor 2 particularly discloses a method for applying the insulating resin, and a method for aligning the protruding electrode and the wire patterns.
  • the semiconductor element is bonded by way of applying pressure after (i) the application of the insulating resin to the wire patterns of the insulating tape and (ii) the alignment of the protruding electrodes with the wire patterns. Therefore, for the alignment of the protruding electrodes and the wire patterns, an alignment mark pattern (hereinafter, referred to as “alignment mark”) is required to be provided so as to prevent a positioning (alignment) error thereof and exposure of the wire patterns.
  • the alignment mark is required to be provided outside the application region of the insulating resin, in other words, outside of the aperture portion of the solder resist, the alignment mark being used for alignment upon connecting the protruding electrodes and the wire patterns.
  • an alignment mark partially covered with an insulating resin cannot be detected when the alignment mark is partially covered with an insulating resin, so that the alignment mark is provided, outside the aperture portion of the solder resist, away from the solder resist as distant as possible.
  • the following explains a method for manufacturing a COF by using the connecting-sealing method such as the NCP etc., in other words, a method for installing a semiconductor element on a wire substrate, with reference to FIG. 13 , FIG. 14 , FIG. 15 , and FIG. 16 ( a ) through FIG. 16 ( e ).
  • FIG. 13 is a plan view schematically illustrating a structure of a semiconductor apparatus in which alignment marks are provided outside an aperture portion of a solder resist.
  • FIG. 14 is a plan view schematically illustrating a semiconductor element installation region in the semiconductor apparatus shown in FIG. 13 .
  • FIG. 14 indicates the semiconductor element by a chain double-dashed line, and indicates, by a broken line surrounding the chain double-dashed line, an installation site region (cover region) where the insulating resin is installed.
  • the region surrounded by the chain double-dashed line in FIG. 14 indicates an overlap region overlapping with the semiconductor element.
  • the region surrounded by the broken line surrounding the region surrounded by the chain double-dashed line indicates the installation site region of the insulating resin, in other words, the installation region where the semiconductor element is installed by means of the insulating resin.
  • FIG. 15 ( a ) through FIG. 15 ( e ) and FIG. 16 ( a ) through FIG. 16 ( e ) are cross sectional views each illustrating a major part of the semiconductor apparatus taken along a line B-B′ in FIG. 14 .
  • FIG. 15 ( a ) through FIG. 15 ( e ) illustrate steps of installing the semiconductor element on a wire substrate in Patent document 1
  • FIG. 16 ( a ) through FIG. 16 ( e ) illustrate steps of installing the semiconductor element on a wire substrate in Patent document 2.
  • each of alignment marks 1 is provided, for alignment upon connecting protruding electrodes 13 of the semiconductor element 12 with connecting terminals 2 a of wire patterns 2 , outside an aperture portion 4 a of the solder resist 3 .
  • the aperture portion 4 a is so formed as to surround the connection-overlap portion of the semiconductor element 12 in a tape carrier 10 (insulating tape) used in a wire substrate 201 .
  • FIG. 13 , FIG. 14 , and FIG. 15 ( a ) through FIG. 15 ( e ) has aperture portions 4 b , which are parts of an aperture portion 4 ′ of the solder resist 3 and which are provided in respective installation portions of the alignment marks 1 .
  • a photo-curable or thermo-curable insulating resin 11 is so applied as to cover each connecting terminal 2 a .
  • alignment of protruding electrodes 13 with the connecting terminals 2 a is carried out after carrying out (i) detection of each alignment mark 1 as indicated by arrows 14 in FIG. 15 ( c ), and (ii) detection of each of alignment marks 5 (see FIG. 14 ), provided on an active face of the semiconductor element 12 , as indicated by arrows 15 .
  • pressure is applied as indicated by arrows 17 in FIG. 15 ( d ).
  • each of alignment marks 1 is provided, for alignment upon connecting a protruding electrode 13 of the semiconductor element 12 with connecting terminals 2 a of wire patterns 2 , outside an aperture portion 4 a of the solder resist 3 .
  • the aperture portion 4 a is so formed as to surround the connection-overlap portion of the semiconductor element 12 on a tape carrier 10 (insulating tape) used for a wire substrate 201 .
  • the semiconductor apparatus has aperture portions 4 b , which are parts of an aperture portion 4 ′ of the solder resist 3 and which are provided in respective installation portions of the alignment marks 1 .
  • thermo-curable insulating resin 11 is so applied as to cover each connecting terminal 2 a .
  • detection of each alignment mark 1 is carried out as indicated by arrows 14 in FIG. 16 ( c ), and detection of the alignment mark 5 (see FIG. 14 ) provided on the active face of the semiconductor element is carried out as indicated by arrows 15 .
  • each wire pattern 2 is required to be provided away from such an alignment mark 1 provided outside the aperture portion 4 a of the solder resist 3 , i.e., outside the application region of the insulating resin 11 in Patent documents 1 and 2. This causes an increase in an outer size of a semiconductor apparatus obtained by employing the COF method.
  • each alignment mark 1 is possibly covered partially with the insulating resin 11 .
  • Such an alignment mark 1 partially covered with the insulating resin 11 deteriorates detection accuracy of the alignment mark 1 to such a degree that the alignment mark 1 cannot be accurately detected. This deteriorates the connection position accuracy of the protruding electrodes 13 of the semiconductor element 12 and the connecting terminals 2 a of the wire patterns 2 .
  • An object of the present invention is to provide (i) a COF type semiconductor apparatus that has good connection position accuracy of connecting terminals of a semiconductor element and connecting terminals of a wire pattern in a wire substrate, and that has a small outer shape; (ii) a method for manufacturing the semiconductor apparatus; (iii) a semiconductor module apparatus; and (iv) a wire substrate suitably used for the semiconductor apparatus.
  • Another object of the present invention is to provide (i) a COF type semiconductor apparatus that has good connection position accuracy of connecting terminals of a semiconductor element and connecting terminals of a wire pattern on a wire substrate, and that has a small outer shape, and that can prevent exposure of the wire pattern in the solder resist; (ii) a method for manufacturing the semiconductor apparatus; (iii) a semiconductor module apparatus; and (iv) a wire substrate suitably used for the semiconductor apparatus.
  • a semiconductor apparatus includes: (i) a wire substrate including an insulating substrate on which a plurality of wire patterns are provided; and (ii) a semiconductor element installed on the wire substrate with an insulating resin interposed therebetween, a plurality of connecting terminals provided in the semiconductor element being electrically connected to connecting terminals of the wire patterns, respectively, wherein: the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.
  • the mark pattern has the entire upper face which is covered with the insulating resin, and is provided in the insulating substrate of the semiconductor apparatus for the sake of alignment of the connecting terminals of the semiconductor element with the connecting terminals of the wire patterns. This allows prevention of hindrance of detection of the mark pattern, and good connection position accuracy of the connecting terminals of the semiconductor element and the connecting terminals of the wire pattern. Further, with the structure, the mark patterns are not required to be formed, e.g., outside the solder resist aperture portion that exposes the connecting terminals of the wire patterns, away from the solder resist as distant as possible for fear of the hindrance of the detection of the mark pattern.
  • the mark patterns can be provided within or in the vicinity of the semiconductor element installation region, overlapping with the insulating resin, in the insulating substrate. This reduces outer size of the semiconductor apparatus, and improves freedom in wiring because the wire patterns are not required to be provided away from the mark pattern.
  • a semiconductor module apparatus includes the semiconductor apparatus according to the present invention.
  • the semiconductor module including the semiconductor apparatus according to the present invention, it is possible to provide a semiconductor module apparatus using a COF semiconductor apparatus that allows good connection position accuracy between the connecting terminals of the semiconductor element and the connecting terminals of the wire pattern, and that has a small outer size, and that can prevent exposure of the wire patterns in the solder resist.
  • the semiconductor apparatus according to the present invention is suitably used for a driving apparatus for various kinds of semiconductor module apparatus, such as a mobile phone, a mobile information terminal, a thin display, and a laptop computer.
  • a method, according to the present invention, for manufacturing the semiconductor apparatus according to the present invention includes the steps of: (i) providing the insulating resin on the insulating substrate such that the insulating resin covers an entire surface of each of the mark patterns; and (ii) detecting the mark patterns via the insulating resin provided on the mark patterns, and aligning the connecting terminals of the semiconductor element with the connecting terminals of the wire patterns.
  • the insulating resin is so provided as to cover the entire upper face of each mark pattern, and detection of the mark patterns is carried out via the insulating resin thus provided.
  • the mark pattern is not required to be formed, e.g., outside the solder resist aperture portion that exposes the connecting terminals of the wire patterns, away from the solder resist as distant as possible for fear of the hindrance of the detection of the mark pattern. Therefore, with the method, the mark pattern can be provided within or in the vicinity of the semiconductor element installation region, overlapping with the insulating resin, in the insulating substrate. This reduces outer size of the semiconductor apparatus, and improves freedom in wiring because the wire patterns are not required to be provided away from the mark pattern.
  • a wire substrate for use in the semiconductor apparatus according to the present invention includes: the mark patterns, for use in alignment of (i) the connecting terminals of wire patterns with (ii) the connecting terminals of the semiconductor element to be installed in the insulating substrate, the mark patterns being provided within a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being formed in a solder resist covering the wire patterns provided in the insulating substrate.
  • another wire substrate for use in the semiconductor apparatus, according to the present invention, including a solder resist aperture portion having a shape, when viewed from above, defined by (i) line segments, each of which intersects with the wire patterns provided in a long length direction of the semiconductor element installed in the insulating substrate, and each of which extends along an installation site region of the wire patterns, (ii) line segments, each of which intersects with the wire patterns extending in a short length direction of the semiconductor element, and each of which extends along an installation site region of the wire patterns, and (iii) linkage attaining line segments, each of which connect adjacent line segments of the line segments such that the linkage attaining line segment extends in an inner side with respect to each intersection point of respective extended lines of the line segments; and the mark pattern is formed outside the solder resist aperture portion and opposes each of the linkage attaining line segments, and the wire substrate includes: the mark patterns for alignment of (i) the connecting terminals of the wire patterns and (ii) the connecting
  • the wire substrate For alignment of the connecting terminals of the semiconductor element installed on the insulating substrate and the connecting terminals of the wire patterns, the wire substrate has the mark patterns within the solder resist aperture portion, exposing the connecting terminals of the wire patterns, of the solder resist covering the wire patterns provided in the insulating substrate. Therefore, according to the present invention, it is possible to easily obtain a wire substrate that has the mark patterns in the semiconductor element installation region overlapping with the insulating resin, which mark patterns each have the upper face entirely covered with the insulating resin. The mark patterns are used when installing the semiconductor element in the insulating substrate.
  • the solder resist aperture portion has a shape defined by (i) the line segments, each of which intersects with the wire patterns provided in a long length direction of the semiconductor element, and each of which extends along a provided region of the wire patterns, (ii) the line segments, each of which intersects with the wire patterns extending in a short length direction of the semiconductor element, and each of which extends along a provided region of the wire patterns, and (iii) the linkage attaining line segments, each of which connect adjacent line segments of the line segments such that the linkage attaining line segment extends in an inner side with respect to each intersection point of respective extension lines of the line segments, and the mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns are formed outside the solder resist aperture portion and oppose the respective linkage attaining line segments.
  • the present invention it is possible to easily obtain a wire substrate that has the mark patterns in the semiconductor element installation region overlapping with the insulating resin, which mark patterns each have the upper face entirely covered with the insulating resin and are used when installing the semiconductor element on the insulating substrate.
  • FIG. 1 is a plan view schematically illustrating a structure of a semiconductor apparatus according to an embodiment of the present invention.
  • FIG. 2 is a plan view schematically illustrating a structure of a liquid crystal module in which the semiconductor apparatus shown in FIG. 1 is installed.
  • FIG. 3 is a plan view schematically illustrating a structure within a semiconductor element installation region in the semiconductor apparatus according to the embodiment of the present invention.
  • FIG. 4 is a cross sectional view schematically illustrating a major part of the structure of the semiconductor apparatus according to the embodiment of the present invention.
  • FIG. 5 ( a ) through FIG. 5 ( d ) are major part cross sectional views illustrating steps of manufacturing the semiconductor apparatus shown in FIG. 4 , respectively.
  • FIG. 6 is a cross sectional view schematically illustrating a major part of a structure of another semiconductor apparatus according to the embodiment.
  • FIG. 7 is a cross sectional view schematically illustrating a major part of a structure of still another semiconductor apparatus according to the embodiment.
  • FIG. 8 is a cross sectional view schematically illustrating a major part of a structure of yet another semiconductor apparatus according to the embodiment.
  • FIG. 9 is a cross sectional view schematically illustrating a major part of a structure of still another semiconductor apparatus according to the embodiment.
  • FIG. 10 is a cross sectional view schematically illustrating a major part of a structure of yet another semiconductor apparatus according to the embodiment.
  • FIG. 11 is a cross sectional view schematically illustrating a major part of a structure of still another semiconductor apparatus according to the embodiment.
  • FIG. 12 is a cross sectional view schematically illustrating a major part of a structure of a semiconductor apparatus according to another embodiment.
  • FIG. 13 is a plan view schematically illustrating a structure of a semiconductor apparatus in which an alignment mark is provided outside an aperture portion of a solder resist.
  • FIG. 14 is a plan view schematically illustrating a semiconductor element installation region in the semiconductor apparatus according to the embodiment of the present invention.
  • FIG. 15 ( a ) through FIG. 15 ( e ) illustrate steps of installing the semiconductor element on the wire substrate, assuming that an alignment mark is used in Patent document 1.
  • FIG. 16 ( a ) through FIG. 16 ( e ) respectively illustrate steps of installing the semiconductor element on the wire substrate, assuming that an alignment mark is used in Patent document 2.
  • FIG. 17 is a plan view schematically illustrating a semiconductor element installation region in a comparative semiconductor apparatus.
  • FIG. 18 ( a ) through FIG. 18 ( d ) are major part cross sectional views illustrating steps of manufacturing the semiconductor apparatus shown in FIG. 17 .
  • liquid crystal module liquid crystal display apparatus
  • present invention is not limited to this.
  • FIG. 1 is a plan view schematically illustrating a structure of a semiconductor apparatus according to the present embodiment.
  • FIG. 2 is a plan view schematically illustrating a structure of a liquid crystal module in which the semiconductor apparatus shown in FIG. 1 is installed.
  • FIG. 3 is a plan view schematically illustrating a semiconductor installation region in the semiconductor apparatus according to the present embodiment.
  • FIG. 4 is a cross sectional view schematically illustrating a major portion of the structure of the semiconductor apparatus according to the present embodiment.
  • the semiconductor element is indicated by a chain double-dashed line
  • an installation site region (formation region) of an insulating resin is indicated by a broken line surrounding the chain double-dashed line. Namely, in FIG.
  • the region surrounded by the chain double-dashed line is an overlap region overlapping with the semiconductor element itself.
  • the region surrounded by the broken line surrounding the chain double-dashed line is a region on which the insulating resin is provided, i.e., is an installation region in which the semiconductor is installed by using the insulating resin.
  • a region sandwiched between the chain double-dashed line and the broken line corresponds to a fillet portion (fillet formation portion), which will be described later.
  • the present invention assumes that the semiconductor installation region is made up of the semiconductor overlap region and the fillet formation region that is formed, by the insulating resin, on the periphery of the semiconductor overlap region.
  • FIG. 4 is a cross sectional view of the semiconductor apparatus taken along a line A-A′ of FIG. 3 .
  • a liquid crystal module 100 according to the present embodiment has such a structure that a semiconductor apparatus 20 according to the present embodiment is installed (provided) at an end of a shorter length direction of a liquid crystal panel 31 .
  • the semiconductor apparatus 20 according to the present embodiment includes a wire substrate 16 and a semiconductor element 12 as shown in FIG. 1 and FIG. 2 .
  • the semiconductor apparatus 20 includes an output terminal 7 and an input terminal 8 , each of which serves as an external conductive connector section.
  • the output terminal 7 is provided on one end of the wire substrate 16 , and is electrically connected to an external electronic device, i.e., to the liquid crystal panel 31 in the present embodiment.
  • the input terminal 8 is provided on the other side of the wire substrate 16 , and supplies a signal to the semiconductor apparatus 20 . As shown in FIG. 2 , the semiconductor apparatus 20 is electrically connected to the liquid crystal panel 31 via the output terminal 7 .
  • the semiconductor apparatus 20 is a COF type semiconductor apparatus (COF), and is connected (bonded) to the liquid crystal panel 31 via, e.g., an ACF (anisotropic conductive film; not shown) or the like.
  • COF COF type semiconductor apparatus
  • ACF anisotropic conductive film
  • An output signal of the semiconductor apparatus 20 is sent from the output terminal 7 to each signal line of the liquid crystal panel 31 via an onboard wire (connecting wire; not shown) provided on a glass substrate 32 which is a component of the liquid crystal panel 31 .
  • the semiconductor apparatus 20 is connected to a print substrate 41 (wire substrate) via the input terminal 8 . Through this input terminal 8 , a signal is exchanged and an electric power is distributed.
  • the semiconductor element 12 controls driving of the electronic device in which the semiconductor apparatus is provided.
  • the semiconductor element 12 serves as a liquid crystal driver (liquid crystal driving circuit) used for controlling driving of the liquid crystal panel 31 .
  • the semiconductor element 12 is made of, e.g., a silicon wafer (silicon signal crystal substrate).
  • a plurality of protruding electrodes 13 (connecting terminals; bumps) made of a metal material (conductive material) are provided, with a bonding pad (not shown) therebetween.
  • a suitable material thereof is, for example, gold (Au).
  • the wire substrate 16 has such a structure that each of wire patterns 2 (wires) is provided on a tape carrier 10 (insulating tape; insulating substrate), which is a film substrate (base).
  • a tape carrier 10 insulating tape; insulating substrate
  • the semiconductor sensor 12 is installed (mounted), with its active face downward (face down), in the wire substrate 16 such that the protruding electrodes 13 provided on the semiconductor element 12 are connected to the wire patterns 2 .
  • the tape carrier 10 is a freely foldable and very flexible insulating film.
  • the tape carrier 10 is a flexible insulating film that mainly consists of an insulating material containing plastic such as a polyimide resin and a polyester resin.
  • the present embodiment uses a thin polyimide base insulating tape as the tape carrier 10 ; however, the present invention is not limited to this.
  • the tape carrier 10 has such a thickness that allows the tape carrier 10 to be freely foldable, and the thickness is not particularly limited, but generally falls within a range from 15 ⁇ m to 40 ⁇ m. More specifically, the thickness of the tape carrier 10 is, e.g., 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 38 ⁇ m, or 40 ⁇ m.
  • the wire patterns 2 are formed by, e.g., wet-etching a copper foil that is adhered (fixed) to the tape carrier 10 and that has a thickness of about 5 ⁇ m through 20 ⁇ m. More specifically, the wire patterns 2 (copper foil patterns) provided on a surface of the tape carrier 10 has a thickness of, e.g., 5 ⁇ m, 8 ⁇ m, 9 ⁇ m, 12 ⁇ m, or 18 ⁇ m. Moreover, the surfaces of the wire patterns 2 (copper foil patterns) are coated with tin, gold, or the like (not shown).
  • solder resist 3 (protecting film) made of an insulating resin film (insulating material) such as epoxy resin is applied to a pattern exposed portion, which is a region other than (i) the connection region (semiconductor element installation region) where the tape carrier 10 and the semiconductor element 12 are connected to each other, and (ii) the external conductive connector section (the output terminal 7 and the input terminal 8 ) connected to the liquid crystal panel 31 , the print substrate 41 (see FIG. 2 ), and the like.
  • the solder resist thus applied protects oxidation of the wire patterns 2 , and secures insulation thereof.
  • the solder resist 3 has an aperture portion 4 (solder resist aperture portion) having a rectangular shape as shown in FIG. 3 .
  • the aperture portion 4 corresponds to the connection region of the wire patterns 2 with the semiconductor element 12 , i.e., to the installation region (connection-overlap region) of the semiconductor element 12 on the wire substrate 16 , more specifically, to the overlap region with the semiconductor element 12 on the wire substrate 16 and the peripheral region of the overlap region.
  • alignment mark patterns (hereinafter, referred to as “alignment marks”) 1 are provided at four ends (i.e., corners) inside the aperture portion 4 of the solder resist 3 , respectively. Each of the alignment marks 1 is used for alignment upon connecting the protruding electrode 13 of the semiconductor element 12 to the wire patterns 2 .
  • the alignment mark 1 has a substantially cross shape (“+” shape; hereinafter, referred to as simply “cross shape”) having line segments parallel to edges (sides) of the aperture portion 4 , respectively.
  • the alignment marks 1 and the wire patterns 2 be made of the same material. This allows simultaneous formations of the alignment marks 1 and the wire patterns 2 .
  • the alignment marks 1 and the wire patterns 2 are made of the same material (copper foil), and have the same height. Moreover, each of the alignment marks 1 is provided in each corner in the aperture portion, distantly away from the wire pattern 2 so as not to make contact with each protruding electrode 13 of the semiconductor element 12 .
  • the alignment is carried out in the following manner. That is, the semiconductor element 12 is positioned above the alignment mark 1 such that a junction of the cross shape of the alignment mark 1 corresponds to the corresponding corner of the semiconductor element 12 .
  • the semiconductor element 12 is installed within a region surrounded by the junctions of the alignment marks 1 , which are respectively provided in the four corners (ends) of the aperture portion 4 formed in the wire substrate 16 .
  • the installation is carried out such that the protruding electrodes 13 of the semiconductor element 12 are connected to the respective connecting terminals 2 a of the wire patterns 2 , by using an insulating resin 11 for sealing the lower face of the semiconductor element 12 .
  • a specific example of the insulating resin 11 is an NCP.
  • the insulating resin 11 is so provided (formed) as to cover each alignment mark 1 and extend outside the aperture portion 4 of the solder resist 3 .
  • the connection of the wire substrate 16 and the semiconductor element 12 is carried out under application of heat and pressure, so that the insulating resin 11 between the wire substrate 16 and the semiconductor element 12 becomes flowable, is pushed out of the space between the wire substrate 16 and the semiconductor element 12 , extends outwardly with respect to the semiconductor element 12 , and is cured.
  • a fillet portion (fin-shaped portion) 11 a extending outwardly with respect to the semiconductor element 12 is formed on the periphery of the semiconductor element 12 .
  • a publicly known insulating resin for connecting and sealing the semiconductor element 12 can be used as the insulating resin 11 , and a material (composition) of the resin is not particularly limited.
  • the insulating resin 11 include: translucent (preferably, transparent) thermo-curable resins or photo-curable resins such as a UV-curing resin.
  • Specific examples of the insulating resin 11 include: an epoxy resin, a silicone resin, a phenoxy resin, an acrylic resin, a polyethersulfone resin (PES resin), and so on.
  • FIG. 5 ( a ) through FIG. 5 ( d ) are cross sectional views each illustrating a major part of the semiconductor apparatus 12 according to the present embodiment, and illustrating steps of manufacturing the semiconductor apparatus 12 .
  • the alignment marks 1 are provided inside the aperture portion 4 of the solder resist 3 , the aperture portion 4 being formed in (i) the connection-overlap region of the semiconductor element 12 on the tape carrier 10 of the wire substrate 16 , and (ii) the peripheral region of the connection-overlap region (installation region).
  • the purpose of providing the alignment marks 1 is for the alignment upon connecting the protruding electrodes 13 of the semiconductor element 12 and the connecting terminals 2 a of the wire patterns 2 .
  • the alignment marks 1 and the wire patterns 2 can be made of the same material, and be formed simultaneously by the same formation steps.
  • the alignment marks 1 and the wire patterns 2 can be formed by, for example, etching the copper foil provided on the tape carrier 10 .
  • the alignment marks 1 and the wire patterns 2 can be formed by using a publicly known conventional wire pattern forming method.
  • a roughing treatment is carried out with respect to a surface of a copper foil, and a polyimide precursor solution is applied to the copper foil thus roughed up, and then imidization of the polyimide precursor solution is carried out.
  • a copper-polyimide layered substrate in other words, manufacture of a copper-clad base film by layering a copper foil, for use in the wire pattern formation, on a base film (tape carrier 10 ) made of polyimide.
  • a photo sensitive film which is made of an etching resistance material is adhered to the copper foil, and exposure and development are carried out with respect to a pattern formation region (of the wire patterns 2 and the alignment marks 1 ) so that the photo sensitive film having etching resistance is left only in the pattern formation region, and then an etching liquid is sprayed to the surface of the copper foil in order to etch and remove the copper foil provided in a region other than the pattern formation region.
  • the photosensitive film on the layered substrate is removed by a chemical such as an organic solvent so that the pattern is exposed, with the result that the tape carrier 10 having the wire patterns 2 and the alignment marks 1 is formed on one surface.
  • the solder resist 3 is applied to the pattern formation region excluding a region surrounded by the alignment marks 1 in the tape carrier 10 . With this, the alignment marks 1 are exposed in the region. A portion, which is not covered with the solder resist- 3 , of the wire pattern 2 will be used as the connecting terminal 2 a .
  • at least a surface of each connecting terminal 2 a is coated with tin or gold. This allows acquirement of the wire substrate 16 that has the alignment marks 1 inside the aperture portion 4 of the solder resist 3 and that is according to the present embodiment.
  • the alignment marks 1 each having a cross shape when viewed from above are provided at the corners inside the aperture portion 4 , distantly away from the wire patterns 2 , respectively.
  • thermo-curable insulating resin 11 is so applied as to cover the connecting terminals 2 a .
  • the insulating resin 11 is applied to inside and outside of the aperture portion 4 , and is applied to the entire surface of each alignment mark 1 such that the alignment mark 1 is wholly covered.
  • a target location for application of the insulating resin 11 is determined by detecting the alignment marks 1 .
  • the detection of the alignment marks 1 is carried out by, e.g., using a detecting mechanism (camera) of a commercially available flip chip bonder.
  • the alignment of the connecting terminals 2 a and the protruding electrodes 13 of the semiconductor element 12 is carried out.
  • the detection of the alignment marks 1 is carried out via the insulating resin 11 applied to the surface of the alignment mark 1 .
  • the detections of the alignment marks 1 and 5 can be carried out by detecting (checking) the respective positions of the alignment marks 1 and 5 with the use of the detecting mechanism (camera) of the commercially available flip chip bonder as described above.
  • the insulating resin 11 be translucent so as to allow for accurate detection of the insulating resin 11 , because the detection is carried out via the insulating resin 11 applied to the surface of the alignment mark 1 .
  • the insulating resin 11 is thinly layered (applied) on the alignment mark 1 , so that the insulating resin 11 is not necessarily transparent. Therefore, the insulating 11 may be made of such a material that allows the detecting mechanism to detect the alignment mark 1 , and may have such a film thickness that allows the detecting mechanism to detect the alignment mark 1 .
  • the alignment of the connecting terminals 2 a and the protruding electrodes 13 is carried out by positioning each corner of the semiconductor element 12 on the corresponding junction of the cross shape of the alignment marks 1 provided in each corner of the inside of aperture portion 4 .
  • a heating tool such as a pulse heating tool so that: (i) the semiconductor element 12 is bonded to and mounted on the wire substrate 16 by way of the thermo-curing of the insulating resin 11 , and (ii) the protruding electrodes 13 of the semiconductor element 12 and the connecting terminals 2 a are relevantly bonded together so that the protruding electrodes 13 are electrically connected to the wires of the wire patterns 2 , respectively.
  • the bonding of the protruding electrodes 13 and the connecting terminals 2 a under application of pressure on the semiconductor element 12 causes the insulating resin 11 to be pushed out from the region below the semiconductor element 12 to surroundings of the semiconductor element 12 .
  • the insulating resin 11 thus pushed out and the insulating resin 11 applied to the surroundings of the semiconductor element 12 forms the fillet portion 11 a (resin fillet) along sides of the semiconductor element 12 .
  • thermo-curable resin is used as the insulating resin 11 , and the insulating resin 11 is cured by heating.
  • a photo-curable resin may be used as the insulating resin 11 , and the insulating resin 11 may be cured by light irradiation thereon. Note that, curing conditions of the insulating resin 11 are not particularly limited.
  • Examples of the method for applying the insulating resin 11 may include: a spraying by using a dispenser, an instilling by using a nozzle, a layering of sheet-shaped thermo-plasticizing resins or photo-curable resin, and the like.
  • the method for applying the insulating resin 11 is not particularly limited, either.
  • the connecting-sealing methods such as the MBB, the NCP, and the ACP allow relatively easy control of the application region of the insulating resin 11 .
  • the alignment mark 1 is provided inside the aperture portion 4 of the solder resist 3 , and is wholly covered with the insulating resin 11 in the present embodiment as described above.
  • the wholly covered surface of the alignment mark 1 allows accurate detection of the alignment mark 1 , as is the case where the entire surface of the alignment mark 1 is exposed.
  • FIG. 17 and FIG. 18 ( a ) through FIG. 18 ( d ) each illustrate the case where the insulating resin 11 partially covers each of the alignment marks 1 , provided outside an aperture portion 4 a of a solder resist 3 as shown in FIG. 13 , FIG. 14 , FIG. 15 , and FIG. 16 ( a ) through FIG. 16 ( c ).
  • the aperture portion 4 a is formed within a connection-overlap region and its peripheral region (installation region) on a tape carrier 10 used in a wire substrate 201 .
  • the partial covering of the alignment mark 1 is an example of a problem occurring with ease when an application region of the insulating resin 11 is wide for prevention of exposure of the wire patterns 2 in the aperture portion 4 a .
  • FIG. 17 and FIG. 18 ( a ) through FIG. 18 ( d ) illustrate the case where the alignment mark 1 is not fully within the application region of the insulating resin 11 .
  • FIG. 17 is a plan view schematically illustrating a semiconductor element installation region of the comparison semiconductor apparatus.
  • FIG. 18 ( a ) through FIG. 18 ( d ) are cross sectional views illustrating a major part of the semiconductor apparatus, and illustrating steps of manufacturing the semiconductor apparatus shown in FIG. 17 , respectively. Note that, also in FIG. 17 , for ease of explanation, the semiconductor element is indicated by a chain double-dashed line, and an installation site region (formation region) of the insulating resin is indicated by a broken line surrounding the chain double-dashed line.
  • FIG. 18 ( a ) through FIG. 18 ( d ) corresponds to a cross sectional view taken along a line C-C′ of the semiconductor apparatus shown in FIG. 17 .
  • the alignment marks 1 are respectively provided within aperture portions 4 b formed outside the aperture portion 4 a of the solder resist 3 , the aperture portion 4 a being provided within the connection-overlap region and its peripheral region (installation region).
  • the thermo-curable insulating resin 11 is applied to inside and a periphery of the aperture portion 4 a as shown in FIG. 18 ( b ).
  • the insulating resin 11 partially covers the alignment mark 1 .
  • the present inventors found that the irregularity in detection portion (such an alignment mark 1 ) hinders normal detection of the alignment mark 1 , when the detection is carried out as indicated by arrows 14 in FIG. 18 ( c ).
  • the insulating resin 11 when the insulating resin 11 is applied beyond the aperture portion 4 a of the solder resist 3 for sake of preventing the exposure of the wire patterns 2 in the aperture portion 4 a , the insulating resin 11 partially covers the alignment mark 1 . This deteriorates the detection accuracy of the alignment mark 1 , and no accurate detection possibly can be carried out.
  • Such a tendency is noticeable when the alignment mark 1 is provided outside the aperture portion 4 a , and when the application region of the insulating resin 11 is large to some extent or when the alignment mark 1 is provided close to the aperture portion 4 a.
  • the application region of the insulating resin 11 is required to be smaller as shown in FIG. 14 , or the alignment mark 1 is required to be provided greatly away from the application region of the insulating resin 11 .
  • these arise problems such as (i) exposure of the wire patterns 2 within the aperture portion 4 a , and (ii) an increase in an outer size of the semiconductor apparatus to be manufactured.
  • the alignment mark 1 is free from the irregularity in the detection portion (alignment mark 1 ) when the entire surface of the alignment mark 1 is covered with the insulating resin 11 as described above, so that detection can be normally carried out.
  • the present embodiment ensures prevention of the exposure of the wire patterns 2 in the aperture portion 4 by applying the insulating resin 11 to the aperture portion 4 of the solder resist 3 and beyond the aperture portion 4 .
  • the insulating resin 11 is pushed out to the surroundings of the semiconductor element 12 and is cured there in order to reinforce and firmly bond the semiconductor element 12 and the tape carrier 10 in their connection region (semiconductor element installation region). As the result, the fillet portion 11 a is formed in the surroundings of the semiconductor element 12 .
  • the formation of the fillet portion 11 a in the surroundings of the semiconductor element 12 is done by using the insulating resin 11 applied to the tape carrier 10 .
  • the insulating resin 11 is less likely to spread beyond the application region of the insulating resin 11 . Rather, the region covered with the insulating resin 11 tends to be reduced.
  • the insulating resin 11 used for the formation of the fillet portion 11 a leaves a thin resin, as remaining of the applied insulating resin 11 , in the application region of the insulating resin 11 . For this reason, it is preferable that the insulating resin 11 be applied to inside and outside of the aperture portion 4 of the solder resist 3 , in order to surely prevent the exposure of the wire patterns 2 within the aperture portion 4 .
  • the alignment mark 1 is provided in the aperture portion 4 of the solder resist 3 , and the insulating resin 11 for connecting and sealing the semiconductor element 12 is so applied as to cover wholly the alignment mark 1 , and the insulating resin 11 thus wholly covering the surface of the alignment mark 1 allows the detection of the alignment mark 1 without any hindrance.
  • This allows good connection position accuracy between the protruding electrodes 13 and the connecting terminals 2 a of the wire pattern 2 .
  • the wire patterns 2 are not required to be provided away from the alignment marks 1 , so that freedom in wiring can be improved and the outer size of the semiconductor apparatus 20 can be reduced.
  • the alignment marks 1 for alignment of the protruding electrode 13 of the semiconductor element 12 and the wire pattern 2 of the tape carrier 10 upon connecting them, are provided within the aperture portion 4 that exposes (bares) the installation region of the semiconductor element 12 and that is formed in the solder resist 3 and that is covered wholly with the insulating resin 11 , which is applied to both inside and periphery of the aperture portion 4 , and via which detection of the alignment mark 1 is carried out.
  • the application region of the insulating resin 11 in a final product semiconductor apparatus (product) can be judged based on the application remains of the insulating resin 11 or a surface analysis.
  • the present embodiment mainly explains a structure in which the alignment mark 1 having a cross shape (when viewed from above) is provided, away from the wire patterns 2 , in each corner (end) of the rectangular shape (when viewed from above) of the aperture portion 4 of the solder resist 3 , the aperture portion 4 being formed within the connection overlap region and its peripheral region (installation region) in the tape carrier 10 used in the wire substrate 16 .
  • the shape and the layout (number) of the alignment mark 1 are not limited to this, and can be varied as long as good connection position accuracy is obtained.
  • FIG. 6 through FIG. 11 illustrate modified examples of the semiconductor apparatus according to the present embodiment, and illustrates structures in each of which the shape and the layout (number) of the alignment marks 1 are different from those in the semiconductor apparatus shown in FIG. 3 .
  • a semiconductor element is indicated by a chain double-dashed line
  • an installation region (formation region) of the insulating resin is indicated by a broken line surrounding the chain double-dashed line.
  • FIG. 6 and FIG. 7 illustrates an example in which the aforementioned alignment marks 1 shown in FIG. 3 are provided in two of the four corners inside the rectangular shape of the aperture portion 4 .
  • the present inventors found that two or more alignment marks 1 , whose surface is wholly covered with the insulating resin 11 as described in the present embodiment, allow acquirement of an acceptable connection position accuracy slightly less than the alignment (positioning) accuracy in the semiconductor apparatus 20 shown in FIG. 3 , during the alignment (automatic correction) carried out by detecting the alignment marks 1 . Further, such a change (see FIG. 6 and FIG. 7 ) in layout (number) of the alignment marks 1 allows further reduction of the size of the tape carrier 10 .
  • FIG. 8 and FIG. 9 illustrate examples where alignment marks 1 are smaller than those in FIG. 3 .
  • each alignment mark 1 in a semiconductor apparatus shown in each of FIG. 8 and FIG. 9 has such a shape that corresponds to a part of the shape of the alignment mark 1 shown in FIG. 3 , and is provided within the aperture portion 4 having a rectangular shape.
  • the alignment mark 1 of the semiconductor apparatus shown in FIG. 8 has a substantially T shape, and is provided in each corner (end) of the rectangular shape of the aperture portion 4 such that one side (longitudinal side) of the T shape abuts onto the corresponding corner of the semiconductor element when viewed from above.
  • the alignment mark 1 of the semiconductor apparatus shown in FIG. 9 has an L-shape, and is provided in each corner (end) of the rectangular shape of the aperture portion 4 such that the corners of the semiconductor element 12 are surrounded by the L-shaped alignment marks 1 .
  • Such an alignment mark 1 shown in each of FIG. 8 and FIG. 9 is suitable for a case where a space is narrow between, e.g., an edge of the semiconductor element 12 and an edge of the aperture portion 4 .
  • the alignment mark 1 can have various kinds of shape such as a donut-like (ring) or circular shape as shown in FIG. 10 .
  • the alignment mark 1 may be formed by extending the wire pattern 2 , in a direction of the corner of the semiconductor element 12 , to a location where the alignment mark 1 does not make contact with the protruding electrode 13 .
  • the effect of the present invention can be obtained even when the shape and the layout of the alignment marks 1 are changed, e.g., as shown in FIG. 6 through FIG. 11 .
  • the present embodiment exemplifies and explains the case where the alignment marks 1 and the wire patterns 2 are made of the same material, and are simultaneously manufactured by the same steps; however, the present invention is not limited to this.
  • the alignment marks 1 and the wire patterns 2 may be made of different materials, and may be manufactured by different steps.
  • the alignment marks 1 are made of a conductive material as the wire patterns 2 are, and are so provided as not to make contact with the semiconductor element 12 .
  • the alignment marks 1 may be made of any material that can be detected via the insulating resin 11 .
  • the alignment mark 1 may make contact with the semiconductor element 12 .
  • the present embodiment explains the liquid crystal module as an example of the semiconductor module apparatus according to the present invention; however, the present invention is not limited to this and is applicable to various modules (module semiconductor apparatuses) such as a mobile phone, a mobile information terminal, a thin display, and a laptop computer.
  • the semiconductor apparatus according to the present invention e.g., the semiconductor apparatus 20 can be suitably used for a driving apparatus of the above semiconductor modules.
  • the present embodiment exemplifies and explains the semiconductor apparatus 20 in which a single semiconductor element 12 is provided on the tape carrier 10 ; however, the present invention is not limited to this.
  • a plurality of the semiconductor elements 12 may be provided on a single tape carrier 10 , e.g., along the output terminal 7 by using the COF method.
  • the number of the semiconductor element 12 provided in a semiconductor apparatus is not limited.
  • Embodiment 1 The following description will explain another embodiment of the present invention with reference to FIG. 12 . Note that, for ease of explanation, components having the equivalent functions as those in Embodiment 1 will be given the same reference symbols, and explanation thereof will be omitted. The present embodiment mainly discusses differences from Embodiment 1.
  • Embodiment 1 above explains the case where the alignment marks 1 are provided within the rectangular shape of the aperture portion 4 of the solder resist 3 , the aperture portion 4 being so formed as to surround the connection-overlap region on the tape carrier 10 (wire substrate 16 ).
  • the present embodiment exemplifies and explains a case where the alignment marks 1 are provided outside an aperture portion 4 a (solder resist aperture portion) of a solder resist 3 , the aperture portion 4 a being so provided as to surround a connection-overlap region of the semiconductor element 12 in a tape carrier 10 (a wire substrate 16 ).
  • each of the alignment marks 1 has a cross shape (“+” shape) having line segments parallel to respective edges (sides) of the semiconductor element 12 installed on the wire substrate 16 .
  • the alignment mark 1 is provided in the vicinity of each corner of the overlap region of the semiconductor element 12 , more specifically, is so provided as to surround each corner of the semiconductor element 12 installed on the wire substrate 16 .
  • four aperture portions 4 b are so provided as to surround the connection-overlap region of the semiconductor element 12 .
  • the aperture portion 4 a exposes (bares) the connection-overlap region, and has an (substantially) octagon shape so as not to overlap with the aperture portions 4 b.
  • the semiconductor apparatus has an aperture portion 4 ′ as an aperture portion of the solder resist 3 .
  • the aperture portion 4 ′ is made up of the aperture portion 4 a and the aperture portions 4 b .
  • the aperture portion 4 a surrounds and exposes (bare) the connection-overlap region of the semiconductor element 12 on the tape carrier 10 , and has an (substantially) octagon shape whose two sides are longer than the other sides when viewed from above.
  • Each of the aperture portions 4 b corresponds to a formation region of the alignment mark 1 provided along each oblique side (when viewed from above) of the aperture portion 4 a.
  • the aperture portion 4 a has such a shape obtained by removing the four corners (ends) of the (substantially) rectangular aperture portion 4 of the solder resist 3 in Embodiment 1 (such a structure that the solder resist is filled in four corners of a rectangular solder resist aperture portion which is larger in size than the semiconductor element 12 ).
  • the aperture portion 4 a is defined (constituted) by two types of edges (sides): (1) edges (sides) that are orthogonal to the respective wire patterns 2 formed within the installation region of the semiconductor element 12 in the tape carrier 10 ; and (2) edges (sides) that connect the edges (1) with each other and that are formed by sealing, with the solder resist 3 , regions having no wire patterns 2 in the installation region of the semiconductor element 12 .
  • the aperture portion 4 a is defined by eight edges (sides) adjacent to the semiconductor element 12 installed (mounted) on the wire substrate 16 .
  • the eight line segments are made up of: (i) two line segments 51 and 52 (long length sides) that extend along long length sides of the semiconductor element 12 , and that oppose each other, and that has the same length; (ii) two line segments 53 and 54 (short length sides) that extend along short length sides of the semiconductor element 12 , and that oppose each other, and that has the same length; and (iii) four line segments 55 , 56 , 57 , and 58 (short length sides; linkage attaining line segments) that connect the line segments 51 and 52 (long length sides) with the line segments 53 and 54 (short length sides) together, and that respectively oppose the corners of the semiconductor elements 12 .
  • the semiconductor apparatus is a semiconductor apparatus in which the alignment mark 1 is provided outside the aperture portion 4 a of the solder resist 3 when the aperture portion 4 a is small, more specifically, in which the alignment mark 1 is provided outside the aperture portion 4 a whose aperture size at the corners are smaller than that of the aperture portion 4 having the rectangular shape, the aperture portion 4 a exposing the installation region of the semiconductor element 12 .
  • this reduces the application region of the insulating resin 11 as compared with the case where the alignment mark 1 is covered with the insulating resin 11 . Therefore, in the present embodiment, the insulating resin 11 can be applied to an entire upper face of the alignment mark 1 without an increase in size of the application region of the insulating resin 11 as compared with Embodiment 1.
  • the alignment mark 1 is provided within the normal application region of the insulating resin 11 , and the insulating resin 11 is also applied to the entire upper face of the alignment mark 1 upon the application of the insulating resin 11 . Via the insulating resin 11 thus applied, detection of the alignment mark 1 is carried out.
  • the present embodiment allows reduction of an outer size of the semiconductor apparatus, and allows good connection position accuracy between the protruding electrodes 13 and the wire patterns 2 , and allows prevention of exposure of the wire patterns 2 within the aperture portion 4 of the solder resist 3 .
  • the present embodiment assumes that the alignment marks 1 are provided outside the aperture portion 4 a such that each alignment mark 1 opposes each of the oblique sides (line segments 55 through 58 ) forming corners of the (substantially) octagon-shaped aperture portion 4 a .
  • the octagon shape is defined by (i) the two sides (the line segments 51 and 52 ), each of which intersects with the wire patterns 2 and extends along the long length sides of the semiconductor element 12 when viewed from above (i.e., extends along the installation site region of the wire patterns 2 in a direction of the long length sides of the semiconductor element 12 ); and (ii) the other sides (the line segments 53 through 58 ) shorter than the above two sides.
  • the alignment mark 1 may be provided outside the corners of the aperture portion 4 a having an elliptic shape or a polygon shape defined by (i) the above two sides, i.e., the line segments 51 and 52 (edges), and (ii) other sides (edges) shorter than the line segments 51 and 52 .
  • the alignment marks 1 may be provided within the formation region of the fillet portion 11 a made of the insulting resin 11 and formed outside the aperture portion 4 a in the installation region of the semiconductor element 12 .
  • the alignment mark 1 is so provided as to oppose each of the line segments 55 through 58 (edges; linkage attaining line segments) of the aperture portion 4 a .
  • the line segments 55 through 58 connect the line segments 51 through 54 (edges) with each other by connecting adjacent line segments of the line segments 51 through 54 in such a manner that the line segments 55 through 58 respectively extend in inner sides with respect to intersection points P (P 1 , P 2 , P 3 , and P 4 ) at which respective extension lines of the adjacent line segments intersect with each other.
  • the line segments 51 and 52 each extend along the installation site of the wire patterns 2 in the long length direction of the semiconductor element 2 , and each intersect (e.g., orthogonally) with the wire patterns 2 .
  • the line segments 53 and 54 (borders) each extend along the provided region of the wire patterns 2 in the short length direction of the semiconductor element 2 , and each intersect (e.g., orthogonally) with the wire patterns 2 .
  • the aperture portion 4 a has the following shape (1) or more preferably (2): (1) a shape (e.g., the elliptic shape or the polygon shape) that is defined by the line segments 51 through 58 (specifically, such a shape that is defined by the line segments 51 through 54 , and the line segments 55 through 58 (borders) which connect the line segments 51 through 54 together and whose total length are shorter than a total of length from (i) each end of the line segments 51 through 54 to (ii) each nearest intersection point of the extension lines of the line segments 51 through 54 ); or (2) a shape (e.g., the octagon) that is defined by the line segments 51 through 54 and the line segments 55 through 58 connecting the line segments 51 through 54 with each other in the shortest distance.
  • a shape e.g., the elliptic shape or the polygon shape
  • Embodiments 1 and 2 exemplify and explain the cases where the alignment marks 1 are formed within the installation region of the semiconductor element 12 ; however, the present invention is not limited to this, and the alignment marks 1 may be formed in the vicinity of the installation region. Because the entire upper face of each alignment mark 1 is covered with the insulating resin 11 , the present invention allows good connection position accuracy between the protruding electrode 13 of the semiconductor element 12 and the connecting terminal 2 a of the wire pattern 2 , and allows prevention of any hindrance in detecting the alignment mark 1 .
  • the alignment marks 1 are not required to be formed, e.g., outside the aperture portion 4 or 4 a of the solder resist 3 , away from the solder resist 3 and the installation site region of the insulating resin 11 as distant as possible for fear of the hindrance of the detection of the alignment marks 1 . Therefore, according to the present invention, while keeping the detection accuracy, the alignment mark 1 can be provided within or in the vicinity of the semiconductor element installation region on the tape carrier 10 (that is, the alignment mark 1 can be formed close to the semiconductor element installation region as much as possible). This reduces outer size of the semiconductor apparatus, and improves freedom in wiring because the wire pattern is not required to be provided away from the alignment mark 1 .
  • the insulating substrate has the mark patterns for aligning the connecting terminal of the semiconductor element with the connecting terminal of the wire pattern.
  • the entire upper face of each of the mark patterns is covered with the insulating resin, so that the detection of the mark patterns is free from any hindrance.
  • the mark patterns are not required to be formed, e.g., outside the solder resist aperture portion, exposing the wire pattern, of the solder resist covering the wire pattern, and be formed away from the solder resist and the provided region of the insulating resin as distant as possible for fear of the hindrance of the detection of the mark pattern.
  • the mark patterns within or in the vicinity of the semiconductor element installation region in the insulating substrate. Because the wire patterns are not required to be provided away from the mark patterns, outer size of the semiconductor apparatus is reduced, and freedom in wiring is improved. Therefore, according to the present invention, it is possible to provide a COF type semiconductor apparatus (i.e., a semiconductor apparatus having no device hole in the semiconductor element installation region) and a semiconductor module apparatus, each of which has a small outer size and good connection position accuracy between the respective connecting terminals of the semiconductor element and the wire pattern in the wire substrate.
  • a COF type semiconductor apparatus i.e., a semiconductor apparatus having no device hole in the semiconductor element installation region
  • a semiconductor module apparatus each of which has a small outer size and good connection position accuracy between the respective connecting terminals of the semiconductor element and the wire pattern in the wire substrate.
  • Such a semiconductor apparatus can be suitably used as a driving apparatus of various kinds of semiconductor module apparatuses such as a mobile phone, a mobile information terminal, a thin display, and a laptop computer.
  • the mark patterns be provided within or in the vicinity of the semiconductor element installation region overlapping with the insulating resin in the insulating substrate. It is more preferable that the mark patterns be provided within the semiconductor element installation region overlapping with the insulating resin in the insulating substrate. A reason for this is for reducing the size of the semiconductor apparatus and for improving connection position accuracy between the respective connecting terminals of the semiconductor element and the wire pattern.
  • the semiconductor element installation region overlapping with the insulating resin indicates the aforementioned semiconductor element overlap region and the fillet formation region formed on the periphery of the semiconductor element overlap region by the insulating resin.
  • the mark patterns are provided within, e.g., the solder resist aperture portion of the solder resist covering the wire pattern, or are provided in the fillet formation region made of the insulating resin and formed outside the solder resist aperture portion which exposes the connecting terminal of the wire pattern.
  • the mark patterns are provided in the fillet formation region made of the insulating resin and formed outside the solder resist aperture portion, which exposes the wire pattern, of the solder resist covering the wire pattern, it is possible to reduce the outer size of the semiconductor apparatus, to keep good connection position accuracy between the respective connecting terminals of the semiconductor element and the wire pattern, and to prevent the exposure of the wire pattern in the solder resist aperture portion.
  • the insulating resin wholly covering the solder resist aperture portion prevents the exposure of the wire patterns in the solder resist aperture portion.
  • the structure above makes it possible to reduce the outer size of the semiconductor apparatus, to keep good connection position accuracy between the respective connecting terminals of the semiconductor element and the wire pattern, and to prevent the exposure of the wire patterns in the solder resist aperture portion.
  • the solder resist aperture portion have a shape defined by (i) line segments, each of which intersects with the wire patterns provided in the long length direction of the semiconductor element, and each of which extends along the installation site region of the wire patterns, (ii) line segments, each of which intersects with the wire patterns extending in the short length direction of the semiconductor element, and each of which extends along the installation site region of the wire patterns, and (iii) linkage attaining line segments, each of which connect ones of the line segments such that the linkage attaining line segment extends in an inner side with respect to each intersection point of respective extension lines of the line segments, and the mark patterns are formed outside the solder resist aperture portion and oppose the respective linkage attaining line segments.
  • the solder resist aperture portion when viewed from above, have a substantially octagon shape, two sides of the solder resist aperture portion intersecting with the wire patterns provided in the long length direction of the semiconductor element, the two sides extending along the installation site region of the wire patterns, and the two sides being longer than other sides, and the mark pattern be so provided as to oppose respective oblique sides of the solder resist aperture portion, the oblique sides opposing corners of the semiconductor element.
  • the formation of the solder resist aperture portion or the mark patterns as above makes it possible to form the mark patterns in the semiconductor element installation region overlapping with the insulating resin in the insulating substrate, and to provide a semiconductor apparatus having a small region covered with the insulating resin and a smaller outer size.
  • a method for manufacturing the semiconductor apparatus includes the steps of: (i) providing the insulating resin on the insulating substrate such that the insulating resin covers an entire surface of each of the mark patterns; and (ii) detecting the mark patterns via the insulating resin provided on the mark patterns, and aligning the connecting terminals of the semiconductor element with the connecting terminals of the wire patterns. This allows prevention of hindrance in detection of the mark patterns, and allows alignment, with good connection position accuracy, of the connecting terminals of the semiconductor element and the connecting terminal of the wire pattern.
  • the mark patterns are not required to be formed, e.g., outside the solder resist aperture portion that exposes the connecting terminals of the wire patterns, away from the solder resist as distant as possible for fear of the hindrance of the detection of the mark patterns. Therefore, with the method, the mark patterns can be provided within or in the vicinity of the semiconductor element installation region, overlapping with the insulating resin, on the insulating substrate. This reduces outer size of the semiconductor apparatus, and improves freedom in wiring because the wire patterns are not required to be provided away from the mark patterns. As such, according to the method, it is possible to provide a COF type semiconductor apparatus having a small outer size and having good connection position accuracy between the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns of the wire substrate.
  • a wire substrate according to the present invention includes: the mark patterns, for use in alignment of (i) the connecting terminals of wire patterns and (ii) the connecting terminals of the semiconductor element to be installed in the insulating substrate, the mark patterns being provided within a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being formed in a solder resist covering the wire patterns provided in the insulating substrate. Therefore, it is possible to easily obtain a wire substrate that has the mark patterns in the semiconductor element installation region overlapping with the insulating resin, which mark patterns each have the upper face entirely covered with the insulating resin and are used when installing the semiconductor element in the insulating substrate.
  • the solder resist aperture portion has a shape, when viewed from above, defined by (i) line segments, each of which intersects with the wire patterns provided in a long length direction of the semiconductor element installed in the insulating substrate, and each of which extends along an installation site region of the wire patterns, (ii) line segments, each of which intersects with the wire patterns extending in a short length direction of the semiconductor element, and each of which extends along an installation site region of the wire patterns, and (iii) linkage attaining line segments, each of which connect adjacent ones of the line segments such that the linkage attaining line segment extends in an inner side with respect to each intersection point of respective extended lines of the line segments; and the mark pattern is formed outside the solder resist aperture portion and opposes each of the linkage attaining line segments.
  • the wire substrate includes: the mark patterns for alignment of (i) the connecting terminals of the wire patterns and (ii) the connecting terminals of the semiconductor element to be installed on the insulating substrate, the mark patterns opposing the linkage attaining line segments.
  • a method for manufacturing the semiconductor apparatus includes the steps of: (i) providing the insulating resin on the insulating substrate such that the insulating resin covers an entire surface of each of the mark patterns; and (ii) detecting the mark patterns via the insulating resin provided on the mark patterns, and aligning the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns. This makes it possible to prevent hindrance of detection of the mark pattern, and to carry out alignment, with good connection position accuracy, of the connecting terminals of the semiconductor element and the connecting terminal of the wire pattern.
  • the mark patterns are not required to be formed, e.g., outside the solder resist aperture portion that exposes the connecting terminals of the wire patterns, and be formed away from the solder resist as distant as possible for fear of the hindrance of the detection of the mark pattern. Therefore, with the method, the mark patterns can be provided within or in the vicinity of the semiconductor element installation region, overlapping with the insulating resin, on the insulating substrate. This reduces outer size of the semiconductor apparatus, and improves freedom in wiring because the wire patterns are not required to be provided away from the mark patterns. As such, according to the method, it is possible to provide a COF type semiconductor apparatus having a small outer size and having good connection position accuracy between the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns of the wire substrate.
  • a wire substrate according to the present invention includes: the mark patterns for use in alignment of (i) the connecting terminals of wire patterns and (ii) the connecting terminals of the semiconductor element to be installed in the insulating substrate, the mark patterns being provided within a solder resist aperture portion that exposes the connecting terminals of the wire patterns, the solder resist aperture portion being formed in a solder resist covering the wire patterns provided in the insulating substrate. Therefore, it is possible to easily obtain a wire substrate that has the mark patterns in the semiconductor element installation region overlapping with the insulating resin, which mark patterns each have the upper face entirely covered with the insulating resin and are used when installing the semiconductor element in the insulating substrate.
  • the solder resist aperture portion having a shape, when viewed from above, defined by (i) line segments, each of which intersects with the wire patterns provided in a long length direction of the semiconductor element installed in the insulating substrate, and each of which extends along an installation site region of the wire patterns, (ii) line segments, each of which intersects with the wire patterns extending in a short length direction of the semiconductor element, and each of which extends along an installation site region of the wire patterns, and (iii) linkage attaining line segments, each of which connect adjacent line segments of the line segments such that the linkage attaining line segment extends in an inner side with respect to each intersection point of respective extended lines of the line segments; and the mark patterns are formed outside the solder resist aperture portion and oppose the respective linkage attaining line segments.
  • the wire substrate includes: the mark patterns for alignment of (i) the connecting terminals of the wire patterns and (ii) the connecting terminals of the semiconductor element to be installed in the insulating substrate, the mark patterns opposing the respective linkage attaining line segments.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
US11/091,918 2004-03-30 2005-03-29 Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus Abandoned US20050218513A1 (en)

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JP2004099768A JP4024773B2 (ja) 2004-03-30 2004-03-30 配線基板、半導体装置およびその製造方法並びに半導体モジュール装置

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CN1677660A (zh) 2005-10-05
US7750457B2 (en) 2010-07-06
US20080251946A1 (en) 2008-10-16
TWI292682B (en) 2008-01-11
JP2005286186A (ja) 2005-10-13
JP4024773B2 (ja) 2007-12-19
KR100708364B1 (ko) 2007-04-17
KR20060044927A (ko) 2006-05-16
CN100552929C (zh) 2009-10-21

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