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US20020123180A1 - Transistor and memory cell with ultra-short gate feature and method of fabricating the same - Google Patents

Transistor and memory cell with ultra-short gate feature and method of fabricating the same Download PDF

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Publication number
US20020123180A1
US20020123180A1 US09/797,863 US79786301A US2002123180A1 US 20020123180 A1 US20020123180 A1 US 20020123180A1 US 79786301 A US79786301 A US 79786301A US 2002123180 A1 US2002123180 A1 US 2002123180A1
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Prior art keywords
ddd
source
ldd
drain regions
spacers
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US09/797,863
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English (en)
Inventor
Peter Rabkin
Hsingya Wang
Kai-Cheng Chou
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SK Hynix Inc
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Individual
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Priority to US09/797,863 priority Critical patent/US20020123180A1/en
Application filed by Individual filed Critical Individual
Priority to US09/808,097 priority patent/US6746906B2/en
Assigned to HYNIX SEMICONDUCTOR, INC. reassignment HYNIX SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WANG, HSINGYA ARTHUR, CHOU, KAI-CHENG, RABKIN, PETER
Priority to JP2002054033A priority patent/JP2002313971A/ja
Priority to KR1020020010841A priority patent/KR100851664B1/ko
Priority to CNB02118352XA priority patent/CN1275302C/zh
Publication of US20020123180A1 publication Critical patent/US20020123180A1/en
Priority to US10/861,116 priority patent/US6849489B2/en
Priority to US11/022,005 priority patent/US7202134B2/en
Priority to US11/676,777 priority patent/US8946003B2/en
Priority to US12/052,374 priority patent/US8288219B2/en
Priority to JP2009219704A priority patent/JP2009302575A/ja
Priority to JP2009219701A priority patent/JP2010004069A/ja
Priority to JP2009219702A priority patent/JP2010004070A/ja
Priority to JP2009219703A priority patent/JP5130269B2/ja
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10P10/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • Transistor punch through is defined as the drain voltage at which the drain depletion region extends all the way to that of the source region so that the source and drain regions become electrically shorted together.
  • the transistor thus draws an undesirably high amount of current, resulting in prohibitively high leakage current or even the destruction of the transistor.
  • the channel doping concentration may be increased; however, this in turn leads to a lower junction breakdown voltage.
  • a simplified conventional process sequence for a stack gate flash memory cell includes: forming a tunnel oxide over a substrate; forming a floating gate (poly 1) over the tunnel oxide; forming an interpoly ONO dielectric composite layer; and forming a control gate (poly 2 and tungsten silicide) over the ONO dielectric.
  • the control gate is often formed simultaneously with the gates of peripheral (CMOS) transistors, followed by cell self-aligned etch (SAE) of poly 1 using poly 2 as a mask.
  • SAE cell self-aligned etch
  • DDD implanting steps are performed for periphery high voltage (HV) NMOS and PMOS transistors, followed by oxidation and anneal cycles.
  • the cell S/D implant (in case of symmetrical S/D cells) is performed followed by forming oxide spacers along the side-walls of both the cell polysilicon stack the periphery transistor gates.
  • the properties and physical characteristics of the source and drain regions are dependent on the thickness of the screen oxide (i.e., oxide previously deposited covering the substrate surface areas where the source and drain regions are formed) through which the S/D implant is performed, the implant dose and energy, and the thermal activation.
  • the room for optimizing the source and drain regions is limited.
  • the S/D implant dose has to be sufficiently high to ensure low source and drain resistance, and the implant energy needs to be optimized based on the screen oxide thickness and the junction vertical depth requirements.
  • the above parameters along with the thermal budget of S/D activation/anneal determine the extent of the overlap between the poly stack and the S/D regions, and thus the minimum effective channel length.
  • the effective channel length (which equals the drawn gate length minus the overlaps between the gate and the S/D regions) may be sufficient for proper functioning of the cell (i.e., without punch-through and with high enough junction breakdown voltage BVdss), provided the channel doping is properly optimized.
  • the effective channel length becomes too short, or practically disappears. The cell will exhibit punch-through at very low drain voltage, preventing the cell from proper functioning.
  • an off-set spacer is introduced in the process steps for manufacturing memory cells and transistors and the resulting structures which enables dramatic scaling of the channel length such that high performance transistors and memory cell structures with extremely small gate feature and overall size that exhibit robust program/erase efficiency and read speed, and enable low operating voltages, can be manufactured.
  • a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.
  • said gate electrode forming act includes forming a gate electrode for each of first and second transistors, and said off-set spacers forming act includes forming off-set spacers along side-walls of the gate electrodes of the first and second transistors, said source and drain regions forming act further comprising performing a DDD implant to from DDD source and DDD drain regions for the first transistor.
  • the method further includes: performing a LDD implant to form LDD source and LDD drain regions for the second transistor; after both said DDD and LDD implants, forming main spacers adjacent the off-set spacers of the first and second transistors; and after forming said main spacers, performing a source/drain (S/D) implant to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions, the highly doped regions being of the same conductivity type as and having a doping concentration greater than the DDD and LDD regions.
  • S/D source/drain
  • the extent of an overlap between the gate electrode of the first transistor and each of the DDD source and DDD drain regions, and the extent of an overlap between the gate electrode of the second transistor and each of the LDD source and LDD drain regions is inversely dependent on a thickness of the off-set spacers, and wherein a distance between an outer edge of each of the DDD source and DDD drain regions and an outer edge of the highly doped region within each of the DDD source and DDD drain regions is directly dependent on a thickness of the main spacers, and a distance between an outer edge of each of the LDD source and LDD drain regions and an outer edge of the highly doped region within each of the LDD source and LDD drain regions is directly dependent on a thickness of the main spacers.
  • a method of forming a non-volatile memory cell includes: forming a first polysilicon layer over but insulated from a semiconductor body region; forming a second polysilicon layer over but insulated from the first polysilicon layer; forming an off-set spacer along at least one side-wall of the first and second polysilicon layers; and after forming said off-set spacer, forming at least one of source and drain regions in the body region so that the extent of an overlap between the first polysilicon layer and said one of source and drain regions is dependent on a thickness of the off-set spacer.
  • the first and second polysilicon layers form a polysilicon stack, off-set spacers being formed along side-walls of the polysilicon stack, and source and drain regions being formed after forming the off-set spacers so that the extent of an overlap between the polysilicon stack and each of the source and drain regions is inversely dependent on a thickness of the off-set spacers.
  • a method of forming a non-volatile memory cell and transistors includes: forming a first polysilicon layer over but insulated from a semiconductor body region, and a second polysilicon layer over but insulated from the first polysilicon layer, the first and second polysilicon layers forming a polysilicon stack of the memory cell; forming a gate electrode for each of first and second transistors over but insulated from a semiconductor region; forming off-set spacers along side-walls of the polysilicon stack and the gate electrode of the first and second transistors; and after forming said off-set spacers, forming source and drain regions for each of the memory cell and the first and second transistors so that the extent of an overlap between the polysilicon stack and the cell source and drain regions and the extent of an overlap between each of the gate electrodes of the first and second transistors and their corresponding source and drain regions are dependent on a thickness of the off-set spacers.
  • the method further comprises: performing a DDD implant to form DDD source and DDD drain regions for the first transistor; and performing a LDD implant to form LDD source and LDD drain regions for the second transistor.
  • the method further includes: performing a cell source/drain (S/D) implant to form the cell source and drain regions; and after said cell S/D implant and said LDD implant and said DDD implant, performing a transistor S/D implant to form highly doped regions within all the DDD and LDD regions.
  • S/D cell source/drain
  • the method further includes: after said cell S/D implant and said LDD implant and said DDD implant but before said transistor S/D implant, forming main spacers adjacent the off-set spacers of at least the first and second transistors, wherein the highly doped regions within all the DDD and LDD regions are of the same conductivity type as and have a doping concentration greater than the DDD and LDD regions.
  • a structure in another embodiment, includes a first transistor which includes: a first gate electrode over but insulated from a semiconductor body region; off-set spacers along side-walls of the first gate electrode; and a source region and a drain region in the body region so that the extent of an overlap between the first gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.
  • the structure further includes a second transistor which includes: a second gate electrode over but insulated from a semiconductor body region; off-set spacers along side-walls of the second gate electrode; source and drain regions; main spacers adjacent the off-set spacers of the first and second transistors; and wherein each of the source and drain regions of the first transistor comprises a highly doped region within a DDD region, and each of the source and drain regions of the second transistor comprises a highly doped region within a LDD region, the highly doped regions being of the same conductivity type as and having a doping concentration greater than the DDD and LDD regions.
  • a second transistor which includes: a second gate electrode over but insulated from a semiconductor body region; off-set spacers along side-walls of the second gate electrode; source and drain regions; main spacers adjacent the off-set spacers of the first and second transistors; and wherein each of the source and drain regions of the first transistor comprises a highly doped region within a DDD region, and each of the source and
  • the extent of an overlap between the first gate electrode and each of the DDD source and DDD drain regions, and the extent of an overlap between the second gate electrode and each of the LDD source and LDD drain regions is inversely dependent on a thickness of the off-set spacers.
  • a distance between an outer edge of each of the DDD source and DDD drain regions and an outer edge of the highly doped region within each of the DDD source and DDD drain regions is directly dependent on a thickness of the main spacers, and a distance between an outer edge of each of the LDD source and LDD drain regions and an outer edge of the highly doped region within each of the LDD source and LDD drain regions is directly dependent on a thickness of the main spacers.
  • a non-volatile memory cell includes: a first polysilicon layer over but insulated from a semiconductor body region; a second polysilicon layer over but insulated from the first polysilicon layer; an off-set spacer along at least one side-wall of the first and second polysilicon layers; and source and drain regions in the body region, wherein the extent of an overlap between the first polysilicon layer and at least one of said source and drain regions is dependent on a thickness of the off-set spacer.
  • the first and second polysilicon layers form a polysilion stack
  • the memory cell further comprising off-set spacers along side-walls of the polysilicon stack so that the extent of an overlap between the polysilicon stack and each of the source and drain regions is inversely dependent on a thickness of the off-set spacers.
  • FIGS. 1 a - 1 g show cross section views of a MOS transistor at different processing steps in accordance with an exemplary embodiment of the present invention
  • FIGS. 2 a - 2 d show cross section views of a channel erase non-volatile memory cell at different processing steps in accordance with an exemplary embodiment of the present invention
  • FIGS. 3 a - 3 d show cross section views of a memory cell, a low voltage periphery LDD transistor, and a high voltage periphery DDD transistor at different processing steps in accordance with an exemplary embodiment of the present invention
  • FIGS. 4 a and 4 b show cross section views of a source-side erase non-volatile memory cell at different processing steps in accordance with another exemplary embodiment of the present invention
  • FIGS. 5 a and 5 b show cross section views of a source-side erase non-volatile memory cell at different processing steps in accordance with yet another exemplary embodiment of the present invention
  • FIG. 6 shows a cross section view of a non-volatile memory cell at a processing step in accordance with another exemplary embodiment of the present invention.
  • FIG. 7 shows a cross section view of a split-gate non-volatile memory cell at a processing step in accordance with another exemplary embodiment of the present invention.
  • MOS transistors and non-volatile memory cells with ultra-short gate length e.g., 0.12 ⁇ m and shorter, with improved punch-through and junction breakdown characteristics, and methods of fabricating the same are obtained.
  • a new element, called the off-set spacer is introduced in the fabrication process and the resulting structures.
  • the off-set spacer serves as an additional means for process and device optimization, and controlling the effective channel length.
  • the off-set spacer can be used in MOS transistor to reduce the extent of overlap between the gate and the source/drain (S/D) regions, so that the effective channel length is sufficiently increased even for extremely small geometry of the gate.
  • the off-set spacer allows deeper S/D junctions to be formed for the same channel length, and thereby reduces source/drain resistance while controlling precisely gate overlap.
  • the off-set spacer can be similarly used in memory cells to reduce the extent of overlap between the floating gate or the select gate and the S/D regions, and to form deeper junctions.
  • MOS transistors and non-volatile memory cells with extremely small gate feature size which exhibit high program/erase efficiency and read speed, and enable use of low operating voltages, while eliminating the punch-through problem associated with ultra-short channel length devices, is obtained.
  • Other features and advantages of the present invention will become apparent from the following description.
  • FIG. 1 a shows a polysilicon gate 130 formed over but insulated from a body region 100 according to conventional processing steps.
  • an off-set oxide spacer layer 110 is deposited over the structure using conventional chemical vapor deposition (CVD) techniques, as shown in FIG. 1 b.
  • Oxide layer 110 is then etched using conventional reactive ion etching (REI) techniques, to form off-set oxide spacers 10 a and 10 b along the side-walls of gate 130 , as shown in FIG. 1 c.
  • CVD chemical vapor deposition
  • REI reactive ion etching
  • implant 150 is a conventional source/drain (S/D) implant.
  • S/D implant 150 is carried out before forming oxide spacers.
  • the drain/source to gate overlap is reduced, thus increasing the effective channel length for the same drawn gate feature.
  • the thickness of the off-set spacer can be optimized based on device requirements and the desired lateral drain/source to gate overlap.
  • N-type impurities for implant 150 By using N-type impurities for implant 150 , a NMOS transistor is formed, and by using P-type impurities for implant 150 , a PMOS transistor is formed. Conventional masking steps are carried out to protect the PMOS regions during N-type implant, and vice versa.
  • implant 150 is a double doped drain (DDD) implant to form DDD source and drain junctions for high voltage transistors.
  • DDD double doped drain
  • a main spacer oxide layer is deposited and etched to form main spacers 115 a , 115 b .
  • a S/D implant 160 is then carried out to form regions 120 b and 140 b as shown in FIG. 1 f .
  • N ⁇ impurities is used as implant 150
  • N + impurities is used as implant 160 , to form a high voltage NMOS transistor.
  • high voltage PMOS transistors are formed by using P ⁇ impurities as implant 150 and P + impurities as implant 160 .
  • implant 150 is a lightly doped drain (LDD) implant to form LDD source 120 c and LDD drain 140 c regions as shown in FIG. 1 g.
  • LDD lightly doped drain
  • off-set spacers are formed, and then DDD junctions for high voltage (HV) transistors are formed followed by forming LDD junctions for low voltage (LV) transistors.
  • Main oxide spacers are then formed followed by S/D implant. Forming the main oxide spacers is optional and may or may not be employed for LV and/or HV MOS transistors depending on device requirements. However, the off-set spacer and main spacer can be advantageously combined.
  • the off-set spacer can be used to obtain a longer effective channel length for the same drawn gate length in order to improve source/drain punch-through, while the main spacer can be used to improve the junction breakdown by providing a wider separation between the outer edges of each of the LDD and DDD regions and the outer edges of their respective inner regions formed by the S/D implant.
  • the main oxide spacers can be used to ensure that the outer edge of each of the junction regions 120 b and 140 b are farther from the edges of the corresponding junction regions 120 a and 140 a , thus improving the junction breakdown.
  • the extent of an overlap between the gate 130 and each of the DDD source 120 a and DDD drain 140 a regions is dependent on the thickness of the off-set spacers 110 a , 110 b
  • the extent of an overlap between the gate 130 and each of the LDD source 120 c and LDD drain 140 c regions is dependent on the combined thickness of the off-set 110 and main 115 spacers or to the thickness of only the off-set spacers if main spacers are not formed for the LDD transistor.
  • a distance between an outer edge of each of the DDD source 120 a and DDD drain 140 a regions and an outer edge of their corresponding inner regions 120 b , 140 b is directly dependent (i.e., not inversely) on the thickness of the main spacers.
  • off-set spacers are formed before DDD and LDD implant steps, and main spacers are formed after the DDD and LDD implant steps but before the subsequent S/D implant.
  • FIGS. 1 f and 1 g in the resulting DDD and LDD transistor structures, the extent of an overlap between the gate 130 and each of the DDD source 120 a and DDD drain 140 a regions, and the extent of an overlap between the gate 130 and each of the LDD source 120 c and LDD drain 140 c regions is inversely dependent on the thickness of the off-set spacers 110 a , 110 b .
  • a distance between an outer edge of each of the DDD source 120 a and DDD drain 140 a regions and an outer edge of their corresponding inner regions 120 b , 140 b is directly dependent on the thickness of the main spacers 115 a , 115 b
  • a distance between an outer edge of each of the LDD source 120 c and LDD drain 140 c regions and an outer edge of their corresponding inner regions 120 b , 140 b is directly dependent on the thickness of the main spacers.
  • off-set spacers are formed between the DDD implant and the subsequent LDD implant, and main spacers are formed between the LDD implant and the subsequent S/D implant.
  • the extent of an overlap between the gate 130 and each of the LDD source 120 c and LDD drain 140 c regions is inversely dependent on a thickness of the off-set spacers 110 a , 110 b , and a distance between an outer edge of each of the DDD source 120 a and DDD drain 140 a regions and an outer edge of their corresponding inner regions 120 b , 140 b is directly dependent on the combined thickness of the off-set 110 and main 115 spacers or to the thickness of only the off-set spacer if main spacers are not formed for the DDD transistor. Also, a distance between an outer edge of each of the LDD source 120 c and LDD drain 140 c regions and an outer
  • each of the source 120 and drain 140 regions has an overlap with gate 130 , the extent of which is dependent on the thickness of the off-set spacers 110 a , 110 b . If a thinner off-set oxide layer 110 (FIG. 1 b ) is deposited, a larger overlap is obtained, while a thicker off-set oxide layer will result in a smaller overlap.
  • the range of the thickness of the off-set oxide layer may be 100-500 ⁇ depending on device channel length and its overall optimization.
  • the off-set spacer thickness may be reduced to 20-50 ⁇ as technology scaling moves to next generation processes.
  • a flash technology that utilizes the advanced channel erase method with symmetrical source and drain regions is used.
  • the channel erase approach does not require the relatively deep DDD source junction, thus allowing for better scaling of the cell.
  • the source and drain regions can be symmetrical and formed by just one S/D implant.
  • the invention is not limited to memory cell structures using channel erase, and can be advantageously applied to other non-volatile memory cells including cell structures using source-side erase.
  • FIGS. 2 a - 2 d show cross section views of a non-volatile memory cell at different processing steps in accordance with an exemplary embodiment of the present invention.
  • FIG. 2 a shows a polysilicon stack formed according to conventional techniques.
  • a tunnel oxide layer 290 overlays a silicon substrate 200 ; floating gate 235 overlays tunnel oxide 290 ; a composite ONO dielectric layer 245 overlays floating gate 235 ; and control gate 265 overlays the ONO dielectric 245 .
  • An off-set oxide deposition and etch are carried out to form off-set oxide spacers 210 a , 210 b along the polysilicon stack side-walls as shown in FIG. 2 b .
  • conventional CVD techniques are used to deposit the off-set oxide layer over the structure, and then conventional reactive ion etching (REI) techniques are used to etch the off-set oxide layer.
  • the thickness of the off-set oxide layer is selected based on the drawn gate length and the desired channel length, and process specifics.
  • the thickness of the off-set spacers may be in the range of, for example, 20-500 ⁇ .
  • the drawn gate length is 0.1 ⁇ m
  • the off-set spacer thickness is around 250 ⁇ . Modern processes can provide spacer thickness as thin as 20-30 ⁇ with 8-10% film thickness variations.
  • a S/D implant 260 is performed next to form source 220 and drain 240 regions in accordance with conventional techniques.
  • N + impurities may be used to from a N-type cell
  • P + impurities may be used to form a P-type cell.
  • a main oxide spacer layer is deposited and etched to from main oxide spacers 215 a , 215 b adjacent the off-set spacers 210 a , 210 b , as shown in FIG. 2 d .
  • the implanted S/D regions 220 , 240 are then subjected to a thermal activation cycle.
  • Main oxide spacers 215 a , 215 b are not necessary, and are included in the cell to eliminate a masking layer which would otherwise be needed to protect the array region during the formation of main oxide spacers in low voltage (LV) LDD and high voltage (HV) DDD peripheral transistors. This is discussed in more detail below where integration of a flash cell process with a CMOS process is described.
  • the presence of the off-set spacers 210 a , 210 b reduces the overlap between the floating gate and the source/drain junctions by approximately the off-set spacer width, thus resulting in a longer effective channel length for the small gate feature of 0.1 ⁇ m.
  • an effective channel length of about 0.06 ⁇ m is obtained.
  • Simulation results indicate that with proper optimization of the channel doping profile (e.g., boron Vt implant in the range of 4.5 ⁇ 10 13 to 5.5 ⁇ 10 13 /cm 2 , S/D implant in the range of 3 ⁇ 10 15 to 4 ⁇ 10 15 at 20-25 keV, a tunnel oxide in the range of 80-90 ⁇ , and ONO thickness in the range of 110-140 ⁇ ) the cell does not exhibit punch-through, with a BV dss of 4.4-4.5V. This level of BV dss allows drain programming voltage of 3.5-4.0V, which ensures high programming efficiency.
  • the channel doping profile e.g., boron Vt implant in the range of 4.5 ⁇ 10 13 to 5.5 ⁇ 10 13 /cm 2 , S/D implant in the range of 3 ⁇ 10 15 to 4 ⁇ 10 15 at 20-25 keV, a tunnel oxide in the range of 80-90 ⁇ , and ONO thickness in the range of 110-140 ⁇
  • This level of BV dss allows drain programming voltage
  • the off-set spacer regulates the source/drain to gate overlap and consequently the channel length
  • the S/D implant and thermal activation conditions can now be optimized independently. This provides an added flexibility in obtaining the required junction vertical depth and the desired source/drain resistance.
  • the spacer off-set oxide etch step is delayed or completely excluded, so that the subsequent S/D implant is carried out through the deposited off-set oxide layer.
  • the S/D implant energy and dose need to be properly adjusted based on the combined thickness of the off-set spacer and the screening (residual) oxide present from prior processing steps.
  • the off-set spacer may also be advantageously used in manufacturing other types of non-volatile memory cells.
  • the off-set spacers can be used to improve the band-to-band tunneling and the junction breakdown problems commonly encountered at the source side.
  • the band-to-band tunneling can adversely impact the cell endurance and charge retention.
  • the source region is typically a DDD junction while the drain region has ordinary characteristics. Because the source region is a DDD junction, the junction tends to be deep with relatively large side diffusion. The large side diffusion of the source junction results in a relatively large overlap between the source and the floating gate. Thus, the drawn gate length must be made large enough to account for such an overlap, which leads to a bigger cell size.
  • off-set spacers 410 a , 410 b are formed along the side-walls of the stacked gate.
  • a source DDD implant 450 is carried out to form a source DDD region 420 a .
  • a conventional S/D implant 460 is then carried out, followed by thermal activation to form the source diffusion region 420 b and drain diffusion region 440 .
  • each of source region 420 and drain region 440 with the floating gate is reduced by the thickness of the respective off-set spacers 410 a , 410 b , thus allowing the drawn cell gate length and the overall cell size to be reduced.
  • FIG. 4 In another embodiment (not shown) of the FIG. 4 source-side erase cell approach, after the DDD implant 450 (FIG. 4 a ), main spacers are formed adjacent the off-set spacers 410 a , 410 b , followed by S/D implant 460 as shown in FIG. 4 b .
  • This embodiment has the added advantage that the main spacer can be used to adjust the distance between the outer edge of the DDD region 420 a and the outer edge of the inner region 420 b to improve source junction breakdown.
  • the S/D implant 460 may be split into two implanting steps whereby a first S/D implant optimized specifically to form the drain region 440 is carried out, and a second S/D implant optimized specifically to form the inner region 420 b . Although this requires additional masking and processing steps, but it allows the source junction to be fully independently optimized for erase as well as other operations.
  • off-set spacers 510 a , 510 b are formed after source DDD implant 550 , but before the S/D implant 560 .
  • This sequence results in a wider separation between the outer edges of the two source regions 520 a and 520 b .
  • the wider separation results in a lower doping gradient, and thus an improved source junction breakdown and less band-to-band tunneling during cell erase operation.
  • the source DDD region 520 a is formed in the absence of an off-set spacer, the overlap between the source and the polysilicon stack is larger than the FIG. 4 embodiment, thus requiring a longer drawn channel length.
  • the S/D implant may be split into a fist S/D implant for the drain region 540 and a separate second S/D implant for the inner region 520 b . This provides more flexibility in forming the two source regions 520 a , 520 b , and allows the source and drain regions to be separately optimized.
  • the off-set spacer can also be advantageously used in split gate cell structures to reduce the drawn cell gate length, as shown in FIG. 7. Even though there is a height difference along the two side-walls of the split gate cell structure, the same off-set spacer deposition and etch steps will result in formation of off-set spacers 710 a and 710 b having similar thickness. As such, the extent of the overlap between the source 720 and the control gate 730 will be similar to that between the drain 740 and floating gate 780 . Alternatively, by using a mask, as in the FIG. 5 embodiment, only one off-set spacer (either on the drain side or the source side) may by formed, as needed.
  • FIGS. 3 a - 3 d are used to illustrate how the off-set spacer is advantageously used in a process integrating non-volatile memory cell technology and CMOS process.
  • Each of FIGS. 3 a - 3 d shows cross section views of an array cell (the far left structure), a periphery DDD high voltage (HV) transistor (the middle structure) and a periphery LDD low voltage (LV) transistor (the far right structure).
  • HV high voltage
  • LV low voltage
  • FIG. 3 a shows a polysilicon stack in the array cell, and polysilicon gates in the periphery HV DDD and LV LDD transistors, all formed in accordance with conventional processing techniques.
  • Off-set spacers 310 are formed along the side-walls of the polysilicon stack in the array cell and the side-walls of the polysilicon gates of the periphery DDD and LDD transistors.
  • a DDD implant 350 is performed to form DDD junctions 320 a , 340 a for the HV DDD periphery transistor.
  • a LDD implant 355 is performed to form LDD regions 325 a , 327 a for the LV LDD periphery transistor.
  • a source/drain (S/D) implant 317 is carried out for the array cell to form the cell source 328 and drain 329 regions.
  • main oxide spacers 315 are formed adjacent the off-set spacers 310 for each of the array cell and the periphery DDD and LDD transistors.
  • the main spacers in the cell are not necessary, and may be eliminated at the expense of a masking step if desired.
  • a S/D implant 360 is then performed for the periphery DDD and LDD transistors to from highly doped regions 320 b , 340 b within the respective DDD regions 320 a , 340 a , and to from highly doped regions 325 b , 327 b within the respective LDD regions 325 a , 327 a .
  • a conventional Boron Phosphorous Silicon Glass (BPSG) thermal cycle may then be carried out to activate all dopings.
  • BPSG Boron Phosphorous Silicon Glass
  • a masking layer may be used to protect areas that are not to receive a given implant.
  • a masking layer (not shown) may be used to protect the memory cell area and periphery DDD transistor area from receiving the LDD implant 355 .
  • NMOS (and/or PMOS) LDD and DDD transistors and a N-type (and/or P-type) memory cell are formed by using N-type (and/or P-type) impurities in the DDD, LDD and S/D implants.
  • N-type impurities in the DDD, LDD and S/D implants As an example, in FIG.
  • NMOS LDD transistors are formed by implanting N ⁇ impurities in the NMOS LDD transistor areas while a masking layer protects the cell area, the NMOS DDD transistor areas, the PMOS DDD transistor areas, and the PMOS LDD transistor areas.
  • PMOS LDD transistors can be formed by implanting P ⁇ impurities in the PMOS LDD transistor areas while a masking layer covers the memory cell area, the NMOS DDD transistor area, the PMOS DDD transistor areas, and the NMOS LDD transistor area.
  • the S/D implant for the array cell and the periphery low and high voltage transistors is performed simultaneously. This reduces the number of masking steps by one, and eliminates the steps corresponding to the main spacer formation, but has the disadvantage of losing the flexibility of optimizing the S/D implant for the array and periphery areas independently. Also, eliminating the main spacers results in the LDD and DDD junctions being more closely spaced to their corresponding S/D junctions. This may result in lower junction breakdown voltage.
  • FIGS. 3 a - 3 d may be modified and/or their order changed depending on the process/device targets and goals.
  • the off-set spacer formation step precedes the main spacer formation step
  • the DDD and LDD implanting steps precede the S/D implant step
  • at least seven different process step permutations are possible, as described next.
  • off-set spacers are formed before the DDD implant, main spacers are formed for the cell and the periphery DDD and LDD transistors (or only for the DDD and LDD transistors) between the DDD implant and the subsequent LDD implant, and the S/D implant for the cell and the DDD and LDD transistors is performed (simultaneously or separately) after the LDD implant.
  • off-set spacers are formed before DDD and LDD implant steps, and main spacers are formed for the cell and the DDD and LDD transistors (or only for the LDD and DDD transistors) after the DDD and LDD implant steps but before the S/D implant for the cell and the periphery transistors.
  • the S/D implant may be performed simultaneously or separately for the cell and periphery transistors.
  • a third exemplary permutation corresponds to the process steps shown in FIGS. 3 a - 3 d.
  • off-set spacers are formed between the DDD implant and the subsequent LDD implant, and main spacers are formed for the cell and the DDD and LDD transistors (or only for the LDD transistor) between the LDD implant and the subsequent S/D implant for the cell and the periphery transistors.
  • the S/D implant may be performed simultaneously or separately for the cell and periphery transistors.
  • off-set spacers are formed between the DDD implant and the subsequent LDD and cell S/D implant, and main spacers are formed for the cell and the DDD and LDD transistors (or only for the LDD transistor) after LDD and cell S/D implant but before the periphery S/D implant.
  • off-set spacers are formed after the DDD and LDD implant steps but before the cell S/D implant, and main spacers are formed for the cell and the DDD and LDD transistors (or eliminated all together) after the cell S/D implant but before the periphery S/D implant.
  • off-set spacers are formed after the DDD and LDD implant steps but before the S/D implant for the cell and periphery transistors, and the S/D implant for the cell and periphery DDD and LDD transistors are performed simultaneously after the off-set spacer formation.
  • Process step permutations other than those describe above, can also be envisioned by one skilled in the art in light of the description provided herein.
  • the off-set spacers for the cell and the LDD and DD transistors are formed at the same time. If specific requirements for the transistors warrant it, the off-set spacers can be formed separately for each of the array cells, LDD transistors, and DDD transistors.
  • each additional off-set spacer requires a separate set of processing and potentially masking steps, e.g., spacer oxide deposition, a masking step to expose only the cell area or the DDD or LDD transistor areas, and a spacer etch, thus increasing the process cost.
  • CMOS portion of the integrated process described above includes DDD and LDD transistors
  • modifying this process to eliminate one or both of the LDD and DDD type transistors, or to include other types of MOS transistors, would be readily apparent to one skilled in the art in light of the description provided herein.
  • the cell portion of the integrated process described above corresponds to a symmetrical stack gate cell
  • modifying the process to implement other types of memory cells would be obvious to one skilled in the art in light of the description provided herein.
  • the steps corresponding to FIG. 3 a can be modified so that the DDD implant 350 is also provided for the cell to form the DDD source region of the cell.
  • a cell DDD implant, independent of the periphery DDD implant can be added to the process steps at the expense of additional masking and processing steps.
  • the other process permutations and variations described above can be similarly modified to enable implementation of a source-side erase cell or other types of cells.
  • the off-set-spacer may have been referred to as an oxide spacer, however, the invention is not limited as such.
  • the off-set spacer may instead be oxynitride (i.e., oxide containing certain amount of nitrogen), or a composite oxide-nitride, or a composite oxide-nitride-oxide.
  • an off-set oxide-nitride spacer is formed by first forming a high temperature oxide (HTO) layer having a thickness in the range of 20-100 ⁇ , followed by forming a nitride layer having a thickness in the range of 100-500 ⁇ over the HTO layer, in accordance with conventional techniques.
  • HTO high temperature oxide
  • both the oxide and nitride layers are etched to form oxide-nitride off-set spacers, or alternatively, only the nitride layer is etched to form nitride spacers adjacent the oxide layer along the side-walls of the memory cell and/or periphery transistors, such that the subsequent S/D implant is carried out through the oxide layer.
  • the S/D implant energy and dose need to be properly adjusted based on the combined thickness of the off-set oxide layer and any screening (residual) oxide layer(s) present from prior processing steps.
  • the advantage of an off-set oxide-nitride spacer is that the oxide layer ensures better charge retention characteristics while the nitride layer serves as a natural spacer and polysilicon gate stack protector from subsequent etch steps such as self-aligned contact (SAC) etch.
  • SAC self-aligned contact
  • the N ⁇ impurities used during the LDD and DDD implants may be phosphorous, and the N+ implant used during the S/D implant may be arsenic; and in forming PMOS transistors and P-type memory cells, the P ⁇ impurities used during the LDD and DDD implants may be boron, and the P+ impurities used during the S/D implant may be the heavier boron atom BF 2 .
  • the highly doped inner region of the LDD and DDD regions is shown not to overlap the gate electrode or the floating gate, however, the invention is not limited as such. Depending on the thickensses of the off-set and main spacers and the thermal cycle(s) following the implant step(s), the inner regions may or may not overlap the gate electrode or the floating gate.
  • the above-mentioned inverse relationship between the amount of overlap (e.g., between gate and S/D) and the off-set spacer thickness may or may not be linear depending on the process parameters and targets.
  • the above-mentioned distance between the outer edge of each of the LDD and DDD regions and the outer edge of their corresponding inner region may or may not be linearly dependent on the thickness of the off-set or main spacers.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US09/797,863 2001-03-01 2001-03-01 Transistor and memory cell with ultra-short gate feature and method of fabricating the same Abandoned US20020123180A1 (en)

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US09/797,863 US20020123180A1 (en) 2001-03-01 2001-03-01 Transistor and memory cell with ultra-short gate feature and method of fabricating the same
US09/808,097 US6746906B2 (en) 2001-03-01 2001-03-13 Transistor with ultra-short gate feature and method of fabricating the same
JP2002054033A JP2002313971A (ja) 2001-03-01 2002-02-28 非常に短いゲート形状を有するトランジスタとメモリセル、及びその製造方法
KR1020020010841A KR100851664B1 (ko) 2001-03-01 2002-02-28 매우 짧은 게이트 모양을 갖는 트랜지스터와 메모리 셀,및 그 제조 방법
CNB02118352XA CN1275302C (zh) 2001-03-01 2002-03-01 有超短栅特征的晶体管和存储器单元及其制造方法
US10/861,116 US6849489B2 (en) 2001-03-01 2004-06-03 Method for forming transistors with ultra-short gate feature
US11/022,005 US7202134B2 (en) 2001-03-01 2004-12-21 Method of forming transistors with ultra-short gate feature
US11/676,777 US8946003B2 (en) 2001-03-01 2007-02-20 Method of forming transistors with ultra-short gate feature
US12/052,374 US8288219B2 (en) 2001-03-01 2008-03-20 Method of forming a non-volatile memory cell using off-set spacers
JP2009219703A JP5130269B2 (ja) 2001-03-01 2009-09-24 非常に短いゲート形状を有するトランジスタとメモリセルの製造方法
JP2009219704A JP2009302575A (ja) 2001-03-01 2009-09-24 非常に短いゲート形状を有するトランジスタとメモリセルの製造方法
JP2009219701A JP2010004069A (ja) 2001-03-01 2009-09-24 非常に短いゲート形状を有するトランジスタとメモリセルの製造方法
JP2009219702A JP2010004070A (ja) 2001-03-01 2009-09-24 非常に短いゲート形状を有するトランジスタとメモリセルの製造方法

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US10/861,116 Expired - Lifetime US6849489B2 (en) 2001-03-01 2004-06-03 Method for forming transistors with ultra-short gate feature
US11/022,005 Expired - Lifetime US7202134B2 (en) 2001-03-01 2004-12-21 Method of forming transistors with ultra-short gate feature
US11/676,777 Expired - Fee Related US8946003B2 (en) 2001-03-01 2007-02-20 Method of forming transistors with ultra-short gate feature
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US11/022,005 Expired - Lifetime US7202134B2 (en) 2001-03-01 2004-12-21 Method of forming transistors with ultra-short gate feature
US11/676,777 Expired - Fee Related US8946003B2 (en) 2001-03-01 2007-02-20 Method of forming transistors with ultra-short gate feature
US12/052,374 Expired - Fee Related US8288219B2 (en) 2001-03-01 2008-03-20 Method of forming a non-volatile memory cell using off-set spacers

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