TWM576363U - Potential converter to reduce competition - Google Patents

Abstract

This creation proposes a potential converter that reduces competition, which is composed of an input circuit (1), a potential conversion circuit (2), a potential pull-up transistor (3), and a potential pull-up transistor (4). The input circuit (1) is used to provide a first signal (V (IN)) and an inverted signal of the first signal (V (IN)); the potential conversion circuit (2) is used to The contention phenomenon between the pull-up path and the pull-down path is suppressed during the potential conversion; the potential pull-up transistor (3) is used to pull up the potential of a first node (N1); and the potential pull-up The crystal (4) is coupled to a second input terminal (INB) for pulling up the potential of a second node (N2).

The potential converter that reduces the competition phenomenon proposed in this creation can not only accurately convert the first signal into a second signal, but also effectively reduce the competition between the pull-up path and the pull-down path, thereby reducing power consumption.

Description

Potential converter to reduce competition

This creation relates to a potential converter that reduces competition, especially using an input circuit (1), a potential conversion circuit (2), a potential pull-up transistor (3), and a potential pull-up transistor (4) It is an electronic circuit composed to obtain accurate voltage level conversion and effectively suppress competition between the pull-up path and the pull-down path, thereby reducing power loss.

Potentiometer is a type of integrated circuit used to communicate Circuit (IC for short) is an electronic circuit for signal transmission between circuits. In many applications, when the application system needs to transfer signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the potential converter is responsible for converting low-voltage working signals into high-voltage working signals.

Figure 1 shows a latch-type potential converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter ( INV) to form a potential converter circuit to reduce competition, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the input voltage (V (IN)) The potential is also between ground (GND) and the second high potential voltage (VDDL). Input voltage (V (IN)) and inverting input voltage output through inverter (INV) The voltage signals are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, because of the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potentiometer. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the process of the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) is approaching on (or off) and when the second NMOS transistor (MN2) is approaching off (or on), the output node There is a phenomenon of contention between the pull-up and pull-down of the potential at (OUT), so the output voltage signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the input voltage (V (IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that the first Two PMOS transistors (MP2) are turned on. Therefore, the output is a first high potential voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower input voltage (V (IN)) during the conversion may not be possible Make the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), and the second NMOS transistor (MN2) reach full conduction or completely cut off. There is a static current between the potential voltage (VDDH) and the ground (GND). This static current will increase the power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high potential voltage (VDDH). Since the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is The first high-potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high-potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type potential converter operate normally is limited.

Figure 2 shows one of the other prior art mirror-type potential converter circuits. The potential converter is connected and connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). To the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in a saturation region, and Its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) is changed, the potential converter The performance will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

In view of this, the main purpose of this creation is to propose a potential converter that reduces the phenomenon of competition, which can accurately and quickly convert the first signal to a second signal, and can effectively suppress the pull-up path and pull-down path. Competition between them, which in turn reduces power loss.

This creation proposes a potential converter that reduces competition, which is composed of an input circuit (1), a potential conversion circuit (2), a potential pull-up transistor (3), and a potential pull-up transistor (4). The input circuit (1) is used to provide a first signal (V (IN)) and an inverted signal of the first signal (V (IN)); the potential conversion circuit (2) is used to The contention phenomenon between the pull-up path and the pull-down path is suppressed during the potential conversion; the potential pull-up transistor (3) is used to pull up the potential of a first node (N1); and the potential pull-up The crystal (4) is coupled to a second input terminal (INB) for pulling up the potential of a second node (N2).

The simulation results confirm that the potential converter proposed in the present invention to reduce competition can not only accurately and quickly convert a first signal to a second signal, but also effectively suppress the difference between the pull-up path and the pull-down path. Competition can also effectively reduce power loss.

1‧‧‧input circuit

2‧‧‧potential conversion circuit

3‧‧‧ potential pull-up transistor

4‧‧‧ potential pull-up transistor

N1‧‧‧First Node

N2‧‧‧Second Node

N3‧‧‧ third node

N4‧‧‧ fourth node

MP1‧‧‧The first PMOS transistor

MP2‧‧‧Second PMOS transistor

MP3‧‧‧Third PMOS Transistor

MP4‧‧‧Fourth PMOS transistor

MN1‧‧‧The first NMOS transistor

MN2‧‧‧Second NMOS transistor

MN3‧‧‧The third NMOS transistor

MN4‧‧‧Fourth NMOS transistor

IN‧‧‧first input

V (IN) ‧‧‧First Signal

INB‧‧‧Second Input

OUT‧‧‧output

GND‧‧‧ Ground

V (OUT) ‧‧‧Second signal

VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧The second highest power supply voltage

I1‧‧‧first inverter

V (INB) ‧‧‧Inverted first signal

Figure 1 shows a circuit diagram of a potential converter in the first prior art; Figure 2 shows a circuit diagram of a potential converter in the second prior art; and Figure 3 shows a potential conversion that reduces competition in the preferred embodiment of the present invention Circuit diagram; Figure 4 shows the transient analysis sequence of the first signal and the second signal of the preferred embodiment of this creation Figure;

According to the above purpose, this creation proposes a potential converter with reduced competition. As shown in FIG. 3, it is composed of an input circuit (1), a potential conversion circuit (2), and a potential pull-up transistor ( 3) and a potential pull-up transistor (4), wherein the input circuit (1) is used to provide the first signal (V (IN)) and the inverse of the first signal (V (IN)) Phase signal; it is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter (I1), wherein the third NMOS transistor (MN3) The source is connected to the ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); the fourth NMOS transistor The source of (MN4) is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); the first An inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN)) and provide an inversion with the first signal (V (IN)). Signal; the potential conversion circuit (2) is used during potential conversion Competition between pull-up and pull-down paths; it consists of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), and a second NMOS transistor It is composed of a crystal (MN2), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its sink The source is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), and the gate is connected to the third node (N3), The drain is connected to the second node (N2); the source of the first NMOS transistor (MN1) is connected to the third node (N3), and the gate is connected to the second input terminal (INB). ), And its drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the first node (N2) Four nodes (N4), whose gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2); the potential-pumping transistor (3) is coupled to the The first input terminal (IN) is used to pull up the potential of the first node (N1); it is composed of a third PMOS transistor (MP3), and its source is connected to the first high power supply voltage ( VDDH), whose gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); and the potential pull-up transistor (4) is coupled to the second The input terminal (INB) is used to pull up the potential of the second node (N2); it is composed of a fourth PMOS transistor (MP4), and its source is connected to the first high power supply voltage (VDDH) , Its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the first high power supply voltage (VDDH) is used to provide the potential converter The first high power supply voltage required, the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the potential converter, and the level of the second high power supply voltage (VDDL) is less than The first high power supply Voltage level (VDDH), the first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT)) is between 0 volts and Corresponding waveform between 1.8 volts.

Please refer to Figure 3 again. The working mode of the potential converter is described below. The working principle of Figure 3 is as follows: Now consider the stability of the potential converter when the first signal (V (IN)) is a logic low level ("0"). State operation situation: the logic low level ("0") on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the second NMOS transistor (MN2), The gate of the third NMOS transistor (MN3) and the gate of the third PMOS transistor (MP3) cause the second NMOS transistor (MN2), the third NMOS transistor (MN3) to turn off, and the first The three PMOS transistors (MP3) are turned on, and the first inverter (I1) transmits a logic high level ("VDDL") to the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4). The gate and the gate of the fourth PMOS transistor (MP4) make the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) conductive, The fourth PMOS transistor (MP4) is turned off. At this time, because the fourth NMOS transistor (MN4) is turned on, the potential of the fourth node (N4) is pulled down to a logic low level ("0"). The logic low level ("0") of the fourth node (N4) makes the first PMOS transistor (MP1) conductive; furthermore, the first NMOS transistor (MN1) and the third PMOS transistor (MP3) are turned on. ) Are turned on, and the third NMOS transistor (MN3) is turned off. Therefore, the potential of the third node (N3) is pulled up to a logic high level ("VDDH"), and the third node (N3) The logic high level ("VDDH") is transmitted to the gate of the second PMOS transistor (MP2), so that the second PMOS transistor (MP2) is turned off; because the second PMOS transistor (MP2), the first Both the four PMOS transistors (MP4) and the second NMOS transistor (MN2) are turned off, and the fourth NMOS transistor (MN4) is turned on. Therefore, the potential of the fourth node (N4) is maintained at a logic low level ("0"); further, since the first NMOS transistor (MN1), the first PMOS transistor (MP1), and the third PMOS transistor (MP3) are all turned on, and the third NMOS transistor (MN3) is turned off And therefore, the third node (N3) The bit will be maintained at a logic high level ("VDDH"), and the potential of the fourth node (N4) is also maintained at a logic low level ("0"). Therefore, the potential of the output (OUT) will be maintained at a logic low Quasi ("0") steady state value.

Consider again the steady-state operation of the potential converter when the first signal (V (IN)) is at a logic high level ("VDDL"): the second high power voltage on the first input (IN) is simultaneously transmitted to the The input terminal of the first inverter (I1), the gate of the second NMOS transistor (MN2), the gate of the third NMOS transistor (MN3), and the gate of the third PMOS transistor (MP3) So that the second NMOS transistor (MN2), the third NMOS transistor (MN3) are turned on, the third PMOS transistor (MP3) is turned off, and the first inverter (I1) transmits a logic low level (" 0 ") to the gate of the first NMOS transistor (MN1), the fourth NMOS transistor (MN4), and the gate of the fourth PMOS transistor (MP4), so that the first NMOS transistor (MN1) The fourth NMOS transistor (MN4) Off, and the fourth PMOS transistor (MP4) is turned on. At this time, because the first NMOS transistor (MN1) is turned off, and the third NMOS transistor (MN3) is turned on, the third node (N3) The potential is pulled down to a logic low level ("0"), and the logic low level ("0") on the third node (N3) is transferred to the gate of the second PMOS transistor (MP2), so that the The second PMOS transistor (MP2) is turned on; since the second PMOS transistor (MP2), the fourth PMOS transistor (MP4), and the second NMOS transistor (MN2) are all turned on, the fourth node ( The potential of N4) will be pulled up to a logic high level ("VDDH"); and the logic high level ("VDDH") of the fourth node (N4) causes the first PMOS transistor (MP1) to be turned off. Since the first NMOS transistor (MN1), the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are all turned off, the potential of the third node (N3) will be maintained at a logic low level ("0"), and the potential of the fourth node (N4) will also be maintained at a logic high level ("VDDH"), so the potential of the output terminal (OUT) will be pulled up to a first high power supply voltage (VDDH) steady state value

To sum up, because the first PMOS transistor (MP1), the third NMOS transistor (MN3) or the second PMOS transistor (MP2), and the fourth NMOS transistor (MN4) can be completed in a short time. At the same time. In this creation, the first NMOS transistor (MN1) and the second NMOS transistor (MN2) cut off corresponding pull-up paths to reduce competition. When the third NMOS transistor (MN3) or the fourth NMOS transistor (MN4) is turned on (that is, the pull-down path is enabled), the first NMOS transistor (MN1) and the second NMOS transistor (MN2) A transistor will cut off the pull-up path to avoid competition between the pull-up path and the pull-down path. Therefore, the delay time can be greatly reduced, and short-circuit power loss can be eliminated.

The simulation results of Spice transient analysis of the potential converter proposed in this work are shown in Figure 4. From the simulation results, it can be confirmed that the The potential converter not only can quickly and accurately convert the first signal into a second signal, but also can effectively reduce the power loss.

Although this creation specifically discloses and describes the preferred embodiment selected, Those skilled in the art can understand that any form or detail may change without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (8)

A potential converter with reduced competition phenomenon is used to convert a first signal (V (IN)) into a second signal (V (OUT)). The potential converter includes a first node (N1) for converting The drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the drain of a first NMOS transistor (MN1) are connected together; a second node (N2), The drain of the second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the drain of a second NMOS transistor (MN2) are connected together; a third node ( N3) for connecting the gate of the second PMOS transistor (MP2), the source of the first NMOS transistor (MN1), and the drain of a third NMOS transistor (MN3); a first Four nodes (N4) for connecting the gate of the first PMOS transistor (MP1), the source of the second NMOS transistor (MN2), and the drain of a fourth NMOS transistor (MN4) together A first input terminal (IN) coupled to the gate of the third PMOS transistor (MP3) and the second NMOS transistor (MN2) to provide a first signal (V (IN)); A second input terminal (INB) is coupled to the fourth PMOS transistor (MP4) to The gate of the first NMOS transistor (MN1) is used to provide an inverted signal (V (INB)) of the first signal (V (IN)); an output terminal (OUT) is coupled to the fourth Node (N4) is used to output the second signal (V (OUT)); a first inverter (I1) is coupled to the first input terminal (IN) and used to receive the first signal (V (IN)), and provide a signal (V (INB)) which is opposite to the first signal (V (IN)); a first high power supply voltage (VDDH) is coupled to the first PMOS transistor (MP1), the sources of the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4) are used to provide the first height required by the potential converter Power supply voltage; a second high power supply voltage (VDDL) for providing a second high power supply voltage required by the potential converter, the potential of the second high power supply voltage (VDDL) being less than the first high power supply Potential of voltage (VDDH); an input circuit (1) is coupled to the first input terminal (IN) for providing a differential input signal; a potential conversion circuit (2) is coupled to the first high power source The supply voltage (VDDH) and the input circuit (1) are used to Suppress the competition phenomenon of the circuit during the conversion; a potential pull-up transistor (3) is coupled to the first input terminal (IN) to pull up the potential of the first node (N1); and a potential pull-up A crystal (4) is coupled to the second input terminal (INB) and is used to pull up the potential of the second node (N2). The potential converter with reduced competition phenomenon as described in item 1 of the patent application scope, wherein the input circuit (1) includes: a third NMOS transistor (MN3), the source of which is connected to the ground (GND), and the gate Is connected to the first input terminal (IN), and its drain is connected to the source of the first NMOS transistor (MN1); a fourth NMOS transistor (MN4), whose source is connected to the ground ( GND), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the second NMOS transistor (MN2); and a first inverter (I1), coupled Connected to the first input terminal (IN) to receive the first signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)). The potential converter with reduced competition phenomenon described in item 2 of the scope of patent application, wherein the potential conversion circuit (2) includes: a first PMOS transistor (MP1), the source of which is connected to the first high power supply Voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the The first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); a first NMOS transistor (MN1), which The source is connected to the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the first node (N1); and a second NMOS transistor ( MN2), its source is connected to the fourth node (N4), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). The potential converter with reduced competition phenomenon described in item 3 of the scope of patent application, wherein the potential pull-up transistor (3) is composed of a third PMOS transistor (MP3), and its source is connected to the third PMOS transistor (MP3). A high power supply voltage (VDDH) has a gate connected to the first input terminal (IN), and a drain connected to the first node (N1). The potential converter with reduced competition phenomenon as described in item 4 of the scope of patent application, wherein the potential pull-up transistor (4) is composed of a fourth PMOS transistor (MP4), and its source is connected to the first PMOS transistor (MP4). A high power supply voltage (VDDH) has a gate connected to the second input terminal (INB) and a drain connected to the second node (N2). The potential converter with reduced competition phenomenon described in item 1 of the scope of patent application, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). The potential converter with reduced competition phenomenon described in item 6 of the scope of the patent application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH). The potential converter with reduced competition phenomenon described in item 7 of the scope of the patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).