TWM628446U - Contention-free level converting circuit for data receiving circuit - Google Patents

Abstract

The present invention proposes a non-competitive potential conversion circuit for a data receiving circuit, which is composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein the input circuit ( 1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of output potential; the mode control switch (3) is used to control the non-competitive potential conversion circuit for the data receiving circuit different operating modes.

The non-competitive potential conversion circuit for the data receiving circuit proposed in this work can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and the miniaturization of the device. It can also effectively avoid the competition phenomenon at the output end, thereby reducing power loss.

Description

Competitive potential conversion circuit for data receiving circuit

The present invention proposes a non-competitive potential conversion circuit for a data receiving circuit, especially a circuit composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), in order to obtain accurate potential Converting electronic circuits.

A potential conversion circuit is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential conversion circuit is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

FIG. 1 shows a prior art latch-type potential conversion circuit, which uses a first PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistor (MP1), a A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter (INV) ) to form a potential conversion circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the potential of the first signal (V(IN)) is also at the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, in the same During the time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential conversion circuit is in a stable state, the latch type There is no static current generated in the potential conversion circuit. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP2). The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential conversion circuit, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), for the output terminal The pull-up and pull-down of the potential on (OUT) have a phenomenon of contention, so the speed of the second signal (V(OUT)) is slower when it transitions to a low potential. Furthermore, consider that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) And the second NMOS transistor (MN2) is fully turned on or completely off, which will cause a static current (static current) between the first high potential voltage (VDDH) and the ground (GND), which will increase the power loss.

Furthermore, the performance of the latch-type potential conversion circuit is affected by the first high potential voltage (VDDH), since the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) in which the latch-type potential conversion circuit can operate normally is limited.

FIG. 2 shows another prior art mirror-type potential conversion circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together and to The drain of the first PMOS transistor (MP1) makes the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in the saturation region, and its The gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential conversion circuit is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the potential conversion The performance of the circuit will not change much either. Therefore, the mirror-type potential conversion circuit can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a voltage is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1). a quiescent current path.

In view of this, the main purpose of this creation is to provide a non-competitive potential conversion circuit for a data receiving circuit, which can not only accurately and quickly convert a first signal into a second signal, but also has a simple and advantageous circuit structure. It has multiple functions such as miniaturization of the device.

The present invention proposes a non-competitive potential conversion circuit for a data receiving circuit, which is composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein the input circuit ( 1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; the mode control switch (3) is used to control the non-competition for the data receiving circuit Different operating modes of the potential conversion circuit.

It is confirmed by the simulation results that the non-competitive potential conversion circuit for the data receiving circuit proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has a simple circuit structure and is beneficial to the device. Multiple functions such as miniaturization can also effectively avoid the competition phenomenon at the output end, thereby reducing power loss.

1: Input circuit

2: Latch circuit

3: Mode control switch

EN: Enable control terminal

N1: the first node

N2: second node

N3: The third node

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MP6: sixth PMOS transistor

MP7: seventh PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

OUT: output terminal

I1: first inverter

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

V(OUT): Second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Fig. 1 is a circuit diagram of a potential conversion circuit in the first prior art; Fig. 2 is a circuit diagram of a potential conversion circuit in a second prior art; Fig. 3 is a circuit diagram of a data receiving circuit according to a preferred embodiment of the present invention The circuit diagram of the non-competitive potential conversion circuit; Figure 4 shows the transient analysis timing of the first signal and the second signal in the preferred embodiment of the present invention picture;

According to the above purpose, the present invention proposes a non-competitive potential conversion circuit for a data receiving circuit, as shown in FIG. 3, which consists of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein, the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; the mode control switch (3) is used to For controlling different operation modes of the non-competitive potential conversion circuit for the data receiving circuit; the input circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first NMOS transistor (MN2) An inverter (I1) is formed, wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), the gate is connected to the first input terminal (IN), and the drain is connected to the ground. connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the third node (N3); the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and provides a connection with the first Signal (V(IN)) inverted signal; the latch circuit (2) consists of a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a third PMOS transistor (MP3) , a fourth PMOS transistor (MP4) and a seventh PMOS transistor (MP7), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), Its gate is connected to the third node (N3), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node The node (N2) is connected; the source of the third PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain is connected is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to the first high power supply voltage (VDDH), and the gate of the fourth PMOS transistor (MP4) is connected to the second input terminal (INB) , and its drain is connected to the second node (N2); the source of the seventh PMOS transistor (MP7) is connected to the second node (N2), and its gate is connected to the second input ( INB), and its drain is connected to the third node (N3); the mode control switch (3) is composed of a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6) and a A control terminal (EN) is formed, wherein the source of the fifth PMOS transistor (MP5) is connected to the first high power supply voltage (VDDH), and the gate of the fifth PMOS transistor (MP6) is connected to the gate of the sixth PMOS transistor (MP6). The pole is connected to the enable control terminal (EN), and the drain pole is connected to the first node (N1); the source pole of the sixth PMOS transistor (MP6) is connected to the first high power supply Supply voltage (VDDH), its gate is connected to the gate of the fifth PMOS transistor (MP5) and connected to the enable control terminal (EN), and its drain is connected to the third node (N3) connected; the enable control terminal (EN) is coupled to the gates of the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) to provide an enable signal; the first high power supply The voltage (VDDH) is used to provide the first high potential voltage required by the non-competitive potential conversion circuit for the data receiving circuit; and the second high power supply voltage (VDDL) is used to provide the voltage for the data receiving circuit The second high potential voltage required by the non-competitive potential conversion circuit, the potential of the second high power supply voltage (VDDL) is smaller than the potential of the first high power supply voltage (VDDH), the first high power supply voltage ( VDDH) is 1.8 volts, and the second highest power supply The response voltage (VDDL) is 1.2 volts; the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is between 0 volts and 1.8 volts Corresponding waveform between volts.

Please refer to Fig. 3 again, and the working principle of Fig. 3 is explained according to the working mode of the non-competitive potential conversion circuit used in the data receiving circuit:

(I) Active mode

In the active mode, that is, when the enable control terminal (EN) is in a high potential state, both the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are in an OFF state.

Now consider the steady state operation of the potential conversion circuit when the first signal (V(IN)) is at a low potential (0 volts): the low potential on the first input terminal (IN) is simultaneously transmitted to the first inverter ( I1) input terminal, the first NMOS transistor (MN1) and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) is turned off, the third PMOS transistor (MP3) turn on, and the first inverter (I1) transmits a second high potential voltage (1.2 volts) to the second NMOS transistor (MN2), the fourth PMOS transistor (MP4) and the seventh PMOS transistor ( MP7) gate, so that the second NMOS transistor (MN2) is turned on, the fourth PMOS transistor (MP4) and the seventh PMOS transistor (MP7) are both turned off. At this time, due to the second NMOS transistor (MN2) is turned on, the fourth PMOS transistor (MP4) and the seventh PMOS transistor (MP7) are both turned off, so that the potential of the third node (N3) will be pulled down to a low potential (0 volts) value, the low potential of the third node (N3) makes the first PMOS transistor (MP1) turn on. At this time, since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned on, and The first NMOS transistor (MN1) is turned off, so that the potential of the first node (N1) is pulled to a high potential, and the high potential of the first node (N1) causes the second PMOS transistor (MP2) to be turned off , at this time, since the second NMOS transistor (MN2) is turned on, the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the The seven PMOS transistors (MP7) are all turned off, so the potential of the third node (N3) is maintained at a steady state value of a low potential (0 volts). In other words, when the first signal (V(IN)) is at a low potential (0 volts), it is converted into a second signal with a low potential (0 volts) through the potential conversion circuit, and is output from the output terminal (OUT).

Then consider the steady state operation of the potential conversion circuit when the first signal (V(IN)) is the second high potential voltage (1.2 volts): the low potential on the first input terminal (IN) is simultaneously transmitted to the first inverter The input terminal of the phase device (I1), the gate of the first NMOS transistor (MN1) and the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) is turned on and the third PMOS transistor (MP3) is turned off, and the first inverter (I1) transmits a low potential (0 volts) to the second NMOS transistor (MN2), the fourth PMOS transistor (MP4) and the seventh PMOS transistor (MP7) gate, so that the second NMOS transistor (MN2) is turned off, the fourth PMOS transistor (MP4) and the seventh PMOS transistor (MP7) are both turned on. (MP4) and the seventh PMOS transistor (MP7) are both turned on, and the second NMOS transistor (MN2) is turned off, so that the potential of the first node (N1) is pulled down to a low potential (0 volts) The low potential of the first node (N1) makes the second PMOS transistor (MP2) turn on. At this time, due to the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the The seven PMOS transistors (MP7) are all turned on, and the second NMOS transistor (MN2) is turned off. Therefore, the potential of the first node (N1) will be maintained at a low potential (0 volts), and the third node (N3) ) will be maintained at a steady state value of a first high potential voltage (1.8 volts). In other words, when the first signal (V(IN)) is the second high potential voltage (1.2 volts), it is converted into a second signal with the first high potential voltage (1.8 volts) through the potential conversion circuit, and the output terminal ( OUT) output.

To sum up, when the first signal (V(IN)) is at a low level (0 volts), the second signal (V(OUT)) is also at a low level (0 volts); and the first signal (V(IN) ) is the second high potential voltage (1.2 V Special), the second signal (V(OUT)) is the first high potential voltage (1.8V). In this way, the purpose of voltage level conversion is achieved.

(II) Standby mode (Standby mode)

Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low potential state, both the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are in a conducting (ON) state , at this time, since the first node (N1) and the third node (N3) are both at potentials close to the first high potential voltage (VDDH), the first PMOS transistor (MP1) and the second PMOS transistor are The crystals (MP2) are all off, so the latch circuit (2) is disabled. Its working principle is not repeated here.

As shown in Figure 4, the simulation results of Spice transient analysis of the non-competitive potential conversion circuit proposed in this creation for the data receiving circuit can be confirmed by the simulation results. The competitive potential conversion circuit can not only convert the first signal into a second signal quickly and accurately, but also can effectively reduce the power consumption.

Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included in the scope of the patent application of this creation.

1: Input circuit

2: Latch circuit

3: Mode control switch

EN: Enable control terminal

N1: the first node

N2: second node

N3: The third node

MP1: The first PMOS transistor

MP2: Second PMOS transistor

MP3: Third PMOS transistor

MP4: Fourth PMOS transistor

MP5: Fifth PMOS transistor

MP6: sixth PMOS transistor

MP7: seventh PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

OUT: output terminal

I1: first inverter

IN: the first input terminal

V(IN): The first signal

INB: the second input terminal

V(OUT): Second signal

GND: ground

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Claims (7)

A non-competitive potential conversion circuit for a data receiving circuit, for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1), For connecting the drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3), the drain of a fifth PMOS transistor (MP5) and a second PMOS transistor (MP2) ) gates are connected together; a second node (N2) is used for the drain of the second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and a seventh PMOS transistor The sources of the crystals (MP7) are connected together; a third node (N3) is used for the gate of the first PMOS transistor (MP1), the drain of a sixth PMOS transistor (MP6) and the The drains of seven PMOS transistors (MP7) are connected together; a first input terminal (IN) is coupled to the gate of the third PMOS transistor (MP3) and the gate of a first NMOS transistor (MN1) pole and an input terminal of a first inverter (I1) for providing the first signal (V(IN)); a second input terminal (INB), coupled to the fourth PMOS transistor (MP4) , the gate of the seventh PMOS transistor (MP7), the gate of a second NMOS transistor (MN2) and the output terminal of the first inverter (I1) for providing the first signal (V(IN)) inversion signal; an enable control terminal (EN) for providing an enable signal; an output terminal (OUT), coupled to the third node (N3) for outputting the second signal(V(OUT)); a first high power supply voltage (VDDH) for providing the first high potential voltage required by the non-competitive potential conversion circuit for the data receiving circuit; a second high power supply voltage (VDDL) for providing the The second high potential voltage required by the non-competitive potential conversion circuit used for the data receiving circuit, the potential of the second high power supply voltage (VDDL) is smaller than the potential of the first high power supply voltage (VDDH); an input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal; a latch circuit (2), coupled to the first high power supply voltage (VDDH), for storing and The competition phenomenon of output potential is suppressed; and a mode control switch (3) is used to control different operation modes of the non-competitive potential conversion circuit for the data receiving circuit. The non-competitive potential conversion circuit for a data receiving circuit as described in claim 1, wherein the input circuit (1) comprises: the first NMOS transistor (MN1), the source of which is connected to the ground (GND) , its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); the second NMOS transistor (MN2), its source is connected to the ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the third node (N3); and the first inverter (I1) is coupled to the first input terminal (IN ) to receive the first signal (V(IN)) and provide a signal inverse to the first signal (V(IN)). The non-competitive potential conversion circuit for a data receiving circuit as described in item 2 of the patent application scope, wherein the latch circuit (2) comprises: The first PMOS transistor (MP1) has its source connected to the first high power supply voltage (VDDH), its gate connected to the third node (N3), and its drain connected to the first node ( N1) is connected; the second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to The second node (N2) is connected; the third PMOS transistor (MP3), its source is connected to the first high power supply voltage (VDDH), and its gate is connected to the first input terminal (IN), And its drain is connected to the first node (N1); the fourth PMOS transistor (MP4), its source is connected to the first high power supply voltage (VDDH), and its gate is connected to the second an input terminal (INB) whose drain is connected to the second node (N2); and the seventh PMOS transistor (MP7) whose source is connected to the second node (N2) and whose gate is connected to the second input terminal (INB), and its drain is connected to the third node (N3). The non-competitive potential conversion circuit for a data receiving circuit as described in claim 3, wherein the mode control switch (3) comprises: the fifth PMOS transistor (MP5), the source of which is connected to the first A high power supply voltage (VDDH), the gate of which is connected to the gate of the sixth PMOS transistor (MP6) and to the enable control terminal (EN), and the drain of which is connected to the first node (N1) ) is connected; the source of the sixth PMOS transistor (MP6) is connected to the first high power supply voltage (VDDH), its gate is connected to the gate of the fifth PMOS transistor (MP5) and to the enable control terminal (EN), and its drain is connected to the third node (N3) ; and the enable control terminal (EN), coupled to the gates of the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6), for providing an enable signal. The non-competitive potential conversion circuit for a data receiving circuit as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL) between. The non-competitive potential conversion circuit for a data receiving circuit as described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH) between. The non-competitive potential conversion circuit for a data receiving circuit as described in claim 1, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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