TWM598009U - Voltage level shifter having output control circuit - Google Patents

Abstract

This creation proposes a potential converter with an output control circuit, which is composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), wherein the input circuit (1) ) Is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; and the output control circuit (3) is used to control the output terminal (OUT ) Voltage level.

The potential converter with output control circuit proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and it is also effective The ground suppresses the competition between the pull-up path and the pull-down path, thereby reducing power loss.

Description

Potential converter with output control circuit

This creation proposes a potential converter with an output control circuit, especially one composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), in order to obtain accurate voltage level conversion At the same time, it can effectively reduce the power loss of the electronic circuit.

A potential converter is an electronic circuit used to communicate signals between different integrated circuits (IC). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage working signal into a high-voltage working signal.

Figure 1 shows another prior art mirror-type potential converter circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in the The saturation region and its gate voltage make the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high power supply voltage (VDDH) changes, the potential The performance of the converter will not be too Big change. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

Figure 2 shows a latch-type potential converter circuit of the prior art, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor (MN1) , A second NMOS transistor (MN2) and an inverter (INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second high power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between the ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potential converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so as to pull up the gate potential of the second PMOS transistor (MP2) and turn off the second PMOS transistor (MP2); furthermore, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the second PMOS The gate potential of the transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

However, in the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) is close to turning on (or off) and the second NMOS transistor (MN2) is close to turning off (or on), the output terminal There is a contention phenomenon between the pull-up and pull-down of the potential on the (OUT), so the second signal (V(OUT)) is slower when it changes to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion period may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current (static) between the first high power supply voltage (VDDH) and ground (GND). current), this quiescent current will increase power loss.

Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch type level converter operate normally is limited. When the second PMOS transistor (MP2) tends to be on (or off) and in When the second NMOS transistor (MN2) is close to turning off (or on), there is a contention phenomenon for the rise and fall of the potential on the output terminal (OUT), so the second signal (V (OUT)) The speed is slow when changing to a low potential.

In view of this, the main purpose of this creation is to propose a potential converter with an output control circuit, which can not only accurately and quickly convert the first signal into a second signal, but also can effectively reduce the pull-up path and the pull-down path Compete with each other, thereby reducing power loss.

This creation proposes a potential converter with an output control circuit, which is composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), wherein the input circuit (1) is Used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; and the output control circuit (3) is used to control the voltage level of the output terminal of the potential converter.

The simulation results confirm that the potential converter with output control circuit proposed by this creation not only can accurately and quickly convert the first signal to a second signal, but also has a simple circuit structure and is beneficial to the miniaturization of the device. Multiple functions can effectively reduce power loss at the same time.

1: Input circuit

2: Latching circuit

3: Output control circuit

GND: ground

I1: First inverter

N1: the first node

N2: second node

N3: third node

N4: Fourth node

N5: fifth node

MP1: The first PMOS transistor

MP2: second PMOS transistor

MP3: third PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: The third NMOS transistor

MN4: Fourth NMOS transistor

MN5: The fifth NMOS transistor

MN6: The sixth NMOS transistor

OUT: output terminal

IN: the first input

V(OUT): second signal

INB: second input

V(IN): first signal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Figure 1 shows the circuit diagram of the potential converter in the first prior art; Figure 2 shows the circuit diagram of the potential converter in the second prior art; Figure 3 shows the electrical potential of the output control circuit in the preferred embodiment of this creation The circuit diagram of the converter; Figure 4 is a timing diagram showing the transient analysis of the first signal and the second signal of the preferred embodiment of this creation;

According to the above purpose, this author proposes a potential converter with an output control circuit, as shown in Figure 3, which consists of an input circuit (1), a latch circuit (2) and an output control circuit (3) The input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; and the output control circuit (3) is used to Control the voltage level of the output terminal of the potential converter; the input circuit (1) is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter (I1) Composition, wherein the source of the third NMOS transistor (MN3) is connected to the ground (GND), the gate is connected to the first input (IN), and the drain is connected to the third node (N3) Phase connection; the source of the fourth NMOS transistor (MN4) is connected to ground (GND), its gate is connected to the second input (INB), and its drain is connected to the fourth node (N4) Connection; the first inverter (I1) is coupled to the first input (IN), used to receive the first signal (V(IN)), and provide a first signal (V(IN) )) Inverted signal; the latch circuit (2) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1) and a second NMOS The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), the gate is connected to the fourth node (N4), and the source of the first PMOS transistor (MP1) is connected to the fourth node (N4). The drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), and the gate is connected to the third node (N3) ), and its drain is connected to the second node (N2); the source of the first NMOS transistor (MN1) is connected Connected to the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the first node (N1); the second NMOS transistor (MN2) The source is connected to the fourth node (N4), its gate is connected to the first input (IN), and its drain is connected to the second node (N2); the output control circuit (3) is It is composed of a third PMOS transistor (MP3), a fifth NMOS transistor (MN5) and a sixth NMOS transistor (MN6), wherein the source of the third PMOS transistor (MP3) is connected to the The first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the drain of the fifth NMOS transistor (MN5); the fifth NMOS transistor The source of (MN5) is connected to the fifth node (N5), its gate is connected to the first input (IN), and its drain is connected to the drain of the third PMOS transistor (MP3) The source of the sixth NMOS transistor (MN6) is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the fifth node (N5); The first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the level converter with output control circuit; the second high power supply voltage (VDDL) is used to provide the output control The second high power supply voltage required by the level converter of the circuit; the level of the second high power supply voltage (VDDL) is less than the level of the first high power supply voltage (VDDH); the first signal is between A rectangular wave between 0 volts and 1.2 volts, the second signal has a corresponding waveform between 0 volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply The voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is between 0 volts and 1.8 volts Corresponding waveforms between.

Please refer to Figure 3 again, now consider that the first signal (V(IN)) is a logic low level (0 Volts), the steady-state operation of the potential converter with the output control circuit: the logic low level on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1) and the second NMOS The gates of the transistor (MN2), the third NMOS transistor (MN3), and the fifth NMOS transistor (MN5) make the second NMOS transistor (MN2), the third NMOS transistor (MN3) and The fifth NMOS transistor (MN5) is all turned off (OFF), and the first inverter (I1) transmits a logic high level (VDDL) to the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) and the gate of the sixth NMOS transistor (MN6) so that the first NMOS transistor (MN1), the fourth NMOS transistor (MN4) and the sixth NMOS transistor (MN6) are all turned on ( ON). At this time, since the second NMOS transistor (MN2) is turned off (OFF), and the fourth NMOS transistor (MN4) and the sixth NMOS transistor (MN6) are both turned on (ON), the fourth The potential of the node (N4) and the fifth node (N5) will be pulled down to a logic low level (0V), and the logic low level on the fourth node (N4) is transmitted to the first PMOS transistor ( The gate of MP1) turns on the first PMOS transistor (MP1). At this time, since both the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are turned on (ON), The third NMOS transistor (MN3) is turned off. Therefore, the potential of the third node (N3) is pulled up to a logic high level, and the logic high level of the third node (N3) makes the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are both turned off (OFF), at this time, because the third PMOS transistor (MP3) and the fifth NMOS transistor (MN5) are both turned off (OFF), and the The six NMOS transistors (MN6) are turned on (ON), so the potential of the output terminal (OUT) will maintain a steady-state value of a logic low level (0 volt). In a nutshell, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through the potential converter with an output control circuit. (OUT) output.

Then consider that when the first signal (V(IN)) is at a logic high level (VDDL), there is an output control The steady-state operation of the potential converter of the control circuit: the logic high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the second NMOS transistor ( MN2) and the gate of the third NMOS transistor (MN3), so that the second NMOS transistor (MN2) and the third NMOS transistor (MN3) are both turned on (ON), and the first inverter ( I1) Transmit the logic low level to the gates of the first NMOS transistor (MN1), the fourth NMOS transistor (MN4), and the sixth NMOS transistor (MN6), so that the first NMOS transistor (MN1) , The fourth NMOS transistor (MN4) and the sixth NMOS transistor (MN6) are both turned off (OFF). At this time, since the third NMOS transistor (MN3) is turned on (ON), the fourth NMOS transistor Both the crystal (MN4) and the sixth NMOS transistor (MN6) are turned off (OFF), the potential of the third node (N3) will be pulled down to a logic low level, and the logic low level on the third node (N3) Quasi-transmitted to the gates of the second PMOS transistor (MP2) and the third PMOS transistor (MP3), so that the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are both turned on (ON) ), at this time, because the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are both turned on (ON), and the fourth NMOS transistor (MN4) is turned off, the fourth node (N4) ) Will be pulled up to a logic high level. The logic high level of the fourth node (N4) makes the first PMOS transistor (MP1) turn off (OFF). At this time, because the first PMOS transistor (MP1) ) And the first NMOS transistor (MN1) are both turned off (OFF), and the third NMOS transistor (MN3) is turned on (ON), therefore, the potential of the third node (N3) will be maintained at a logic low level , And the potential of the fourth node (N4) will also be maintained at a logic high level. Furthermore, since the third PMOS transistor (MP3) and the fifth NMOS transistor (MN5) are both turned on (ON), The sixth NMOS transistor (MN6) is turned off (OFF), so the potential of the output terminal (OUT) will maintain a steady-state value at a logic high level. In a nutshell, when the first signal (V(IN)) is at a logic high level (VDDL), it is converted into a first high power supply by a potential converter with an output control circuit The second signal of the supply voltage (VDDH) is output from the output terminal (OUT).

To sum up, when the first signal (V(IN)) is at a logic low level (0 volt), the second signal (V(OUT)) is also at a logic low level (0 volt); and the first signal When (V(IN)) is the logic high level (VDDL), the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

The simulation result of Spice transient analysis of the potential converter with output control circuit proposed in this creation is shown in Figure 4. The simulation results can confirm that the potential converter with output control circuit proposed in this creation has Not only can the first signal be converted into a second signal quickly and accurately, but also the competition between the pull-up path and the pull-down path of the output terminal (OUT) can be effectively reduced, thereby reducing power loss.

Although this creation specifically discloses and describes the selected best embodiment, anyone familiar with the technology can understand that any possible changes in form or details do not depart from the spirit and scope of this creation. Therefore, all changes within the scope of related technologies are included in the scope of patent application for this creation.

1: Input circuit

2: Latching circuit

3: Output control circuit

GND: ground

I1: First inverter

N1: the first node

N2: second node

N3: third node

N4: Fourth node

N5: fifth node

MP1: The first PMOS transistor

MP2: second PMOS transistor

MP3: third PMOS transistor

MN1: The first NMOS transistor

MN2: Second NMOS transistor

MN3: The third NMOS transistor

MN4: Fourth NMOS transistor

MN5: The fifth NMOS transistor

MN6: The sixth NMOS transistor

OUT: output terminal

IN: the first input

V(OUT): second signal

INB: second input

V(IN): first signal

VDDH: The first high power supply voltage

VDDL: The second highest power supply voltage

Claims (7)

A potential converter with an output control circuit for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes: a first node (N1) for converting The drain of a first PMOS transistor (MP1) and the drain of a first NMOS transistor (MN1) are connected together; a second node (N2) is used to connect the drain of a second PMOS transistor (MP2) The drain and the drain of a second NMOS transistor (MN2) are connected together; a third node (N3) is used to connect the second PMOS transistor (MP2) and a third PMOS transistor (MP3) The gate, the source of the first NMOS transistor (MN1) and the drain of a third NMOS transistor (MN3) are connected together; a fourth node (N4) is used for the first PMOS transistor ( The gate of MP1), the source of the second NMOS transistor (MN2) and the drain of a fourth NMOS transistor (MN4) are connected together; a fifth node (N5) is used to connect a fifth NMOS The source of the transistor (MN5) and the drain of a sixth NMOS transistor (MN6) are connected together; a first input terminal (IN) is coupled to the second NMOS transistor (MN2), the third The gate of the NMOS transistor (MN3) and the fifth NMOS transistor (MN5) is used to provide the first signal (V(IN)); a second input terminal (INB) is coupled to the first NMOS The gates of the transistor (MN1), the fourth NMOS transistor (MN4), and the sixth NMOS transistor (MN6) are used to provide an inverted signal of the first signal (V(IN)); An output terminal (OUT), coupled to the fifth node (N5), for outputting the second signal (V(OUT)); a first high power supply voltage (VDDH), coupled to the first PMOS The source of the transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3) are used to provide the first high power supply voltage required by the level converter; a second high power supply The supply voltage (VDDL) is used to provide the second high power supply voltage required by the level converter, and the potential of the second high power supply voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH); An input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal; a latch circuit (2), coupled to the first high power supply voltage (VDDH) and the input The circuit (1) is used to save and suppress the competition phenomenon of the output potential; and an output control circuit (3) is used to control the voltage level of the output terminal (OUT) of the potential converter. The potential converter with an output control circuit as described in item 1 of the scope of patent application, wherein the input circuit (1) includes: a third NMOS transistor (MN3), the source of which is connected to the ground (GND), and the gate The electrode is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a fourth NMOS transistor (MN4), the source of which is connected to the ground (GND), and its gate Pole is connected to the second input terminal (INB), and its drain pole is connected to the fourth node (N4); and A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)), and providing a signal with the first signal (V(IN)) Inverted signal. The potential converter with an output control circuit according to the second item of the scope of patent application, wherein the latch circuit (2) includes: a first PMOS transistor (MP1) whose source is connected to the first high power supply Voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the The first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); a first NMOS transistor (MN1), which The source is connected to the third node (N3), the gate is connected to the second input (INB), and the drain is connected to the first node (N1); and a second NMOS transistor ( MN2), its source is connected to the fourth node (N4), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). The potential converter with an output control circuit as described in item 3 of the scope of patent application, wherein the output control circuit (3) includes: a third PMOS transistor (MP3) whose source is connected to the first high power supply Voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the drain of the fifth NMOS transistor (MN5); A fifth NMOS transistor (MN5), its source is connected to the fifth node (N5), its gate is connected to the first input (IN), and its drain is connected to the third PMOS transistor ( MP3) is connected to the drain; and a sixth NMOS transistor (MN6) whose source is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the The fifth node (N5) is connected. The potential converter with an output control circuit as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volt and the second high power supply voltage (VDDL). The potential converter with an output control circuit described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). In the level converter with output control circuit described in the scope of patent application, the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

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