TWI908145B - Physically unclonable function (puf) generator - Google Patents

Abstract

The present disclosure provides a physically unclonable function (PUF) generator including a conductive pattern, an insulation layer, a plurality of conductive lines and a via array. The conductive pattern is disposed on a substrate. The insulation layer is disposed on the substrate to cover the conductive pattern. The conductive lines are disposed on the insulation layer. The via array is disposed in the insulation layer and includes a first via group and a plurality of second via groups. The first via group is overlapped with the conductive pattern and includes a plurality of first vias electrically connected to the conductive pattern. The second via groups are overlapped with the conductive lines respectively, and each includes a plurality of second vias electrically connected to the respective conductive line. The second via, closest to the first via, in the at least one of second via group among the second via groups includes an extension portion bowing outwardly and electrically connecting to the first via.

Description

Physically unreplicable functional generator

This invention relates to a semiconductor device, and more particularly to a physically uncopyable functional generator.

With increasing reliance on computer systems and the internet in sectors such as personal communications, shopping, banking, and commerce, network security is receiving growing attention. A physically unclonable function (PUF) is a physical object implemented in a physical structure that can generate output. The output is easy to evaluate, but difficult or almost impossible to predict. In secure computing and communications, PUFs can be used as unique identifiers or keys.

Generally speaking, even given the exact manufacturing process for producing a PUF device, each PUF device produced is practically impossible to replicate. In this respect, a PUF device is a hardware analogue of a one-way function. PUFs are typically implemented in integrated circuits and are often used in applications with high security requirements.

This invention provides a Physically Unforgeable Function (PUF) generator, wherein the via array is designed to include a first via group that overlaps with and is electrically connected to a conductive pattern, and a multiple second via group that overlaps with and is electrically connected to a multiple second via each of a multiple conductors. This allows at least one second via group in the multiple second via groups to include an extended portion electrically connected to the first via due to process randomness. This enables the PUF generator to generate more diverse and unpredictable random codes based on process randomness, thereby improving the performance of the PUF generator.

One embodiment of the present invention provides a physically uncopyable functional generator, comprising a conductive pattern, an insulating layer, multiple wires, and an array of vias. The conductive pattern is disposed on a substrate. The insulating layer is disposed on the substrate to cover the conductive pattern. Multiple wires are disposed on the insulating layer. The array of vias is disposed in the insulating layer and includes a first group of vias and multiple second groups of vias. The first group of vias overlaps with the conductive pattern and includes multiple first vias electrically connected to the conductive pattern. The multiple groups of second vias overlap with multiple wires respectively and each includes multiple second vias electrically connected to the corresponding wire. The second via closest to the first via in at least one of a plurality of second via groups includes an extended portion electrically connected to the first via.

In some embodiments, the extended portion of the second through hole is in direct contact with the nearest first through hole.

In some embodiments, the extended portion of the second through hole is positioned at the upper or middle level of the second through hole.

In some embodiments, the outward expansion of the second through hole makes the outline of the second through hole resemble the shape of a bowling pin.

In some embodiments, at least one of the plurality of first through holes that is closest to the second through hole includes an extended portion that contacts an extended portion of the second through hole.

In some embodiments, at least one of the plurality of first through holes that is closest to the second through hole includes an extended portion that contacts the second through hole, the extended portion of the at least one first through hole being positioned at an upper horizontal position of the first through hole, and the extended portion of the second through hole being positioned at a middle horizontal position of the second through hole.

In some embodiments, multiple conductors do not overlap with the conductive pattern in a direction perpendicular to the surface of the substrate.

In some embodiments, the plurality of wires includes a plurality of first wires and a plurality of second wires. The plurality of first wires are disposed on an insulation layer on a first side of the conductive pattern. The plurality of second wires are disposed on an insulation layer on a second side of the conductive pattern. The first and second sides of the conductive pattern are opposite to each other in a first direction, and the plurality of first wires and the plurality of second wires are respectively arranged in a second direction intersecting the first direction.

In some embodiments, multiple first wires are spaced apart from each other in a second direction, and multiple second wires are spaced apart from each other in a second direction.

In some embodiments, the via array includes multiple third via groups that do not overlap with the conductive pattern and multiple conductors, and the multiple third via groups are arranged alternately with multiple second via groups in a second direction.

Based on the above, in the aforementioned Physically Unforgeable Function (PUF) generator, the first via group is designed to overlap with the conductive pattern and include multiple first vias electrically connected to the conductive pattern, while multiple second via groups are designed to overlap with multiple conductors and each includes multiple second vias electrically connected to the corresponding conductor. In this way, by utilizing the randomness of the manufacturing process, at least one of the second via groups can have a second via closest to the first via including an extended portion electrically connected to the first via. This allows the PUF generator to generate more different and unpredictable random codes based on the randomness of the process, thereby improving the performance of the PUF generator.

The invention is described more fully with reference to the figures of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the figures is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

It should be understood that when a component is referred to as being "on" or "connected" to another component, it may be directly on or connected to the other component, or there may be an intermediate component. If a component is referred to as being "directly on" or "directly connected" to another component, then there is no intermediate component. As used herein, "connection" can refer to a physical and/or electrical connection, while "electrical connection" or "coupling" can mean the presence of other components between two components. As used herein, "electrical connection" can include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

As used herein, “about,” “approximately,” or “substantially” includes the value mentioned and the average value within an acceptable range of deviation from a specific value that can be determined by someone of ordinary skill in the art, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, “about,” “approximately,” or “substantially” may be used to select a more acceptable range of deviations or standard deviations depending on the optical, etchable, or other properties, rather than applying a single standard deviation to all properties.

The terminology used herein is for illustrative purposes only and is not intended to limit this disclosure. In such cases, the singular form includes the majority form unless the context otherwise requires.

Physically unforgeable features (PUFs) are physical objects implemented in a physical structure that can produce outputs that are easily evaluated but virtually impossible to predict. Integrated circuit (IC) devices typically consist of electronic circuitry formed on a semiconductor substrate or chip made of a semiconductor material such as silicon. The components of an IC device are typically constructed on the substrate using lithography processes, such as subtractive processes like etching and/or additive processes like deposition, rather than being built one object at a time. The electronic devices formed on the substrate are interconnected by conductors or wires, which are also formed on the substrate using lithography processes. Although mass-produced, each integrated circuit device is unique due to physical randomness, even when using the same manufacturing process materials. This inherent variation can be extracted and used as a unique identifier for an integrated circuit device, much like DNA is for humans. According to the embodiments disclosed herein, this variation is used to form a unique integrated circuit device signature used as a PUF because it is unique, device-specific, non-forgeable (potentially impossible to imitate or replicate), reproducible, etc.

Memory-based PUFs transform variations in the device within a bi-stable element to produce a 1 or 0 value. An exemplary type of memory-based PUF is the static random access memory (SRAM) PUF. These PUFs generate a signature using small variations in the memory element. For example, an SRAM PUF obtains its signature from the element's startup state. This type of PUF is very similar to an array of SRAM elements. These elements are powered up and powered down by a virtual power supply. Because each element includes a pair of cross-coupled inverters with variable strength, when the element is powered on, it takes a random value based on the characteristics of the cross-coupled inverters. Next, the status of each element is read through the sensing amplifier and the normal SRAM array channels for input/output (I/O). The performance of the PUF can be improved by using a variety of threshold voltage (Vt) devices.

Figure 1 is a top view of a physically unreplicable functional generator according to one embodiment of the present invention. Figure 2 is a cross-sectional view taken along line A-A' in Figure 1. Figure 3A is an enlarged view of region R1 in Figure 2 according to one embodiment of the present invention. Figure 3B is an enlarged view of region R1 in Figure 2 according to another embodiment of the present invention. Figure 3C is an enlarged view of region R1 in Figure 2 according to yet another embodiment of the present invention. Figure 3D is an enlarged view of region R1 in Figure 2 according to yet another embodiment of the present invention.

Referring to Figures 1 and 2, the Physically Unforgeable Function (PUF) generator 10 includes a conductive pattern 110 disposed on a substrate 100, an insulating layer 120 disposed on the substrate 100 to cover the conductive pattern 110, multiple wires 130 disposed on the insulating layer 120, and an array of vias disposed in the insulating layer 120 (e.g., an array of vias including a first via group GR1 and multiple second via groups GR2).

The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate, as well as component layers and interconnect layers formed on the active surface of the semiconductor substrate or SOI substrate. That is, the substrate 100 may include a semiconductor substrate or SOI substrate, as well as film layers and/or structures formed in the front end of line (FEOL) and back end of line (BEOL) processes.

The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, group III-V semiconductor materials, or group II-VI semiconductor materials. Group III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS e. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. Semiconductor materials may be doped with a first conductivity type dopant or a second conductivity type dopant that complements the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type.

The component layer may include active components (e.g., transistors), passive components, or combinations thereof. The interconnect layer may include dielectric layers formed during front-end online (FEOL) and/or back-end online (BEOL) processes and/or conductor layers and/or vias embedded therein. The dielectric layer may include dielectric materials such as oxides (e.g., silicon oxide) or nitrides (e.g., silicon nitride). The conductor layers and vias may each include conductive materials such as metals or metal alloys. Metals and metal alloys may, for example, be Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

The conductive pattern 110 may be a conductive pattern formed by an interconnect manufacturing process. In some embodiments, the conductive pattern 110 may be a rectangular pattern whose width in the first direction D1 is smaller than its length in the second direction D2. In some embodiments, the first direction D1 intersects the second direction D2. In some embodiments, the first direction D1 is perpendicular to the second direction D2. In other embodiments, the conductive pattern 110 may be a line pattern extending in the second direction D2, the width of which in the first direction D1 may be greater than the width of each conductor 130 in the first direction D1. The conductive pattern 110 may include conductive materials such as metals or metal nitrides. For example, metals may include metal materials such as Cu, Al, Ti, Ta, W, Pt, Cr, and Mo. Metal nitrides may include metal nitrides such as WN, TiSiN, WSiN, TiN, TaN or combinations thereof.

The insulating layer 120 may be an insulating layer formed by an interconnect process. The insulating layer 120 may include suitable insulating materials. For example, the insulating layer 120 may include oxides such as silicon oxide (SiOx), nitrides such as silicon nitride (SiN), or combinations thereof. In some embodiments, the insulating layer 120 may also include materials with a dielectric constant less than that of silicon oxide (e.g., about 3.9), such as tetraethyl orthosilicate (TEOS).

The conductor 130 may be a conductor formed by an interconnect process. In some embodiments, the plurality of conductors 130 may include a plurality of first conductors 132 and a plurality of second conductors 134. The first conductors 132 and the second conductors 134 may be spaced apart from each other in a first direction D1. In some embodiments, the first conductors 132 and the second conductors 134 may not overlap with the conductive pattern 110 in a direction perpendicular to the surface of the substrate 100 (e.g., a third direction D3). In some embodiments, the first conductors 132 and the second conductors 134 may each extend in the first direction D1 and have a width in a second direction D2. In some embodiments, the widths of the first conductors 132 and the second conductors 134 in the second direction D2 are smaller than the dimensions of the conductive pattern 110 in the second direction D2 and/or in the first direction D1. The first conductor 132 and the second conductor 134 may each comprise a conductive material such as a metal or a metal nitride. For example, the metal may include metal materials such as Cu, Al, Ti, Ta, W, Pt, Cr, and Mo. The metal nitride may include metal nitrides such as WN, TiSiN, WSiN, TiN, TaN, or combinations thereof.

Multiple first wires 132 may be disposed on an insulating layer 120 on a first side of the conductive pattern 110. Multiple second wires 134 may be disposed on an insulating layer 120 on a second side of the conductive pattern 110. The first and second sides of the conductive pattern 110 may be opposite to each other in a first direction D1. The multiple first wires 132 and the multiple second wires 134 may be arranged respectively in a second direction D2 intersecting the first direction D1. In some embodiments, the multiple first wires 132 and the multiple second wires 134 are spaced apart from each other in the second direction D2.

The via array includes a first via group GR1 overlapping with the conductive pattern 110 and multiple second via groups GR2 overlapping with multiple conductors 130. The first via group GR1 includes multiple first vias 122 electrically connected to the conductive pattern 110. Each of the second via groups GR2 includes multiple second vias 124 electrically connected to the corresponding conductors 130. The first vias 122 and the second vias 124 may each include a conductive material such as a metal or a metal nitride. For example, the metal may include metal materials such as Cu, Al, Ti, Ta, W, Pt, Cr, Mo, etc. The metal nitride may include metal nitrides such as WN, TiSiN, WSiN, TiN, TaN, or combinations thereof.

In this embodiment, the PUF generator 10 can utilize the randomness of the manufacturing process to allow at least one of the second via groups GR2, whose second via 124b is closest to the first via 122b, to include an extended portion electrically connected to the first via 122b (as shown in Figures 3A to 3D). This allows the PUF generator 10 to generate more diverse and unpredictable random codes composed of 0s and 1s, thereby improving the performance of the PUF generator 10. For example, the conductive pattern 110 is connected to the source terminal to provide current, while the first wire 132 and the second wire 134 are connected to the drain terminal to receive signals. Referring to Figures 2 and 3A, when the extended portion of the second via 124b is in direct contact with and electrically connected to the nearest first via 122b, the current supplied by the source terminal flows through the conductive pattern 110, the first via 122b, the second via 124b with its extended portion, and the first conductor 132 to the drain terminal. In this short-circuit condition, a signal of 1 is generated. On the other hand, when the other second vias 124b maintain their original design shape and do not have extended portions due to random process variations, the current supplied by the source terminal only flows to the first via 122b and not through the extended portion of the second via 124b to the drain terminal. In this normal condition, a signal of 0 is generated. In this way, as shown in Figure 1, the PUF generator 10 can generate more different and unpredictable random codes composed of 0 and 1 at the junction of the conductive pattern 110 and the first wire 132 and/or the second wire 134 (from a top view), thereby improving the performance of the PUF generator 10.

In some embodiments, as shown in Figures 3A to 3D, the flared portion of the second through-hole 124b directly contacts the nearest first through-hole 122b. In some embodiments, the flared portion of the second through-hole 124b may be positioned at an upper horizontal level (as shown in Figure 3A) or a middle horizontal level (as shown in Figure 3C). In some embodiments, as shown in Figures 3A to 3D, the flared portion of the second through-hole 124b gives the outline of the second through-hole 124b a bowling pin shape. In some embodiments, at least one of the plurality of first through-holes 122b closest to the second through-hole 124b includes a flared portion that contacts the flared portion of the second through-hole 124b (as shown in Figures 3B or 3D). In some embodiments, as shown in FIG3D, at least one of the plurality of first through holes 122 adjacent to the second through hole 124 includes an extended portion that contacts the second through hole 124. The extended portion of the at least one first through hole 122b is positioned at the upper horizontal level of the first through hole 122b, and the extended portion of the second through hole 124b is positioned at the middle horizontal level of the second through hole 124b.

In some embodiments, the via array may include multiple third via groups GR3 that do not overlap with the conductive pattern 110 and the multiple conductors 130. The multiple third via groups GR3 and multiple second via groups GR2 are arranged alternately with each other in the second direction D2.

In some embodiments, during the fabrication process of forming the via array, the position of the expanded portions of the first via 122b and/or the second via 124b can be adjusted by changing the gas ratio (e.g., xenon (Xe) and argon (Ar) (Xe/Ar)). For example, because Xe has a larger atomic weight, increasing the proportion of Xe gas enhances the ion bombardment capability of the etching plasma, causing the expanded portion to appear at the lower horizontal level of the via. Conversely, increasing the proportion of Ar gas causes the expanded portion to appear at the upper horizontal level of the via. In some embodiments, the Xe/Ar ratio can be approximately 170 sccm/50 sccm to 50 sccm/170 sccm.

In some embodiments, during the process of forming the via array, _{the proportion} of short _circuits (i.e., _the conduction of the conductive pattern _{110 and} the conductor ₁₃₀ ) caused by the expansion of different areas can be adjusted by adjusting the gas ratio (WC/WE, e.g., 30 _{/ 70} % to 70/30%) of the etching gas ₍ e.g., O2/CF4/CH2F2/C4F6/C4F8/C5F8) at the wafer center and wafer edge.

In some embodiments, the density of the via array is between 0.093 and 0.216 (via area/total area). In some embodiments, the top critical dimension (CD) of the first via 122 and/or the second via 124 is approximately 78 to 80 nm. In some embodiments, the critical dimension (CD) of the expanded portion of the first via 122b and/or the second via 124b is approximately 80 to 84 nm. In some embodiments, the depth of the first via 122b and/or the second via 124b is approximately 1400 nm to 1600 nm.

In summary, in the Physically Unforgeable Function (PUF) generator of the above embodiments, the first via group is designed to overlap with the conductive pattern and include multiple first vias electrically connected to the conductive pattern, while the multiple second via groups are designed to overlap with multiple wires and each includes multiple second vias electrically connected to the corresponding wires. Thus, by utilizing the randomness of the manufacturing process, at least one of the multiple second via groups can have a second via closest to the first via including an extended portion electrically connected to the first via. This allows the PUF generator to generate more diverse and unpredictable random codes based on the randomness of the process, thereby improving the performance of the PUF generator.

10: Physically Unforgeable Function (PUF) Generator 100: Substrate 110: Conductive Pattern 120: Insulation Layer 122, 122a, 122b: First Through-Hole 124, 124a, 124b: Second Through-Hole 130: Conductor 132: First Conductor 134: Second Conductor D1: First Direction D2: Second Direction D3: Third Direction GR1: First Through-Hole Group GR2: Second Through-Hole Group GR3: Third Through-Hole Group

Figure 1 is a top view of a physically unreplicable functional generator according to one embodiment of the present invention. Figure 2 is a cross-sectional view taken along line A-A' in Figure 1. Figure 3A is an enlarged view of region R1 in Figure 2 according to one embodiment of the present invention. Figure 3B is an enlarged view of region R1 in Figure 2 according to another embodiment of the present invention. Figure 3C is an enlarged view of region R1 in Figure 2 according to yet another embodiment of the present invention. Figure 3D is an enlarged view of region R1 in Figure 2 according to yet another embodiment of the present invention.

10: Physically Unforgeable Function (PUF) Generator / PUF Generator

110: Conductivity Pattern

120: The Insulation Layer

122, 122a, 122b: First through hole

124, 124a, 124b: Second through hole

130: Wire

132: First Conductor

134: Second Conductor

D1: First Direction

D2: Second Direction

D3: Third direction

GR1: First through-hole group

GR2: Second through-hole group

GR3: Third through-hole group

Claims (10)

A physically unreplicable functional generator includes: a conductive pattern disposed on a substrate; an insulating layer disposed on the substrate to cover the conductive pattern; a plurality of wires disposed on the insulating layer; and an array of vias disposed in the insulating layer and including: a first group of vias overlapping the conductive pattern and including a plurality of first vias electrically connected to the conductive pattern; and a plurality of second groups of vias, each overlapping a plurality of the wires and each including a plurality of second vias electrically connected to the corresponding wire, wherein at least one of the second groups of vias has a second via closest to a first via including an expanded portion formed by adjusting the etching gas ratio, and the expanded portion is electrically connected to the first via. As described in claim 1, in a physically uncopyable function generator, wherein the extended portion of the second through-hole is in direct contact with the nearest first through-hole. The physically uncopyable functional generator as claimed in claim 1, wherein the flared portion of the second through-hole is positioned at the upper or middle level of the second through-hole. The physically unreplicable functional generator as claimed in claim 1, wherein the outward expansion of the second through-hole causes the outline of the second through-hole to be in the shape of a bowling bottle. The physically uncopyable function generator as described in claim 1, wherein at least one of the plurality of first through holes adjacent to the second through hole includes an expansion portion that contacts the expansion portion of the second through hole. As described in claim 1, in a physically uncopyable function generator, at least one of the plurality of first through holes adjacent to the second through hole includes an extended portion that contacts the second through hole, the extended portion of the at least one first through hole being positioned at an upper horizontal position of the first through hole, and the extended portion of the second through hole being positioned at a middle horizontal position of the second through hole. The physically uncopyable functional generator as described in claim 1, wherein a plurality of the said wires do not overlap with the conductive pattern in a direction perpendicular to the surface of the substrate. The physically uncopyable function generator as described in claim 7, wherein the plurality of said wires includes: a plurality of first wires disposed on the insulation layer on a first side of the conductive pattern; and a plurality of second wires disposed on the insulation layer on a second side of the conductive pattern, wherein the first side and the second side of the conductive pattern are opposite to each other in a first direction, and the plurality of first wires and the plurality of second wires are respectively arranged in a second direction intersecting the first direction. The physically uncopyable function generator as described in claim 8, wherein a plurality of first wires are spaced apart from each other in the second direction, and a plurality of second wires are spaced apart from each other in the second direction. The physically uncopyable functional generator as described in claim 8, wherein the via array includes multiple third via groups that do not overlap with the conductive pattern and the multiple vias, the multiple third via groups and the multiple second via groups being alternately arranged in the second direction.