TWI831561B - Semiconductor device and fabrication method thereof - Google Patents

Abstract

A semiconductor device includes a substrate having a first conductivity type. A well region having a second conductivity type is disposed in the substrate. A source region having the first conductivity type is disposed in the well region. A body region having the second conductivity type is disposed in the substrate and the well region, and abuts the source region. A recess is disposed in the substrate and abuts the body region. A gate electrode is disposed on the well region. A first metal layer is disposed on the source region and the body region, and fills up the recess. A drain electrode is disposed on the backside of the substrate. The substrate and the first metal layer filling up the recess construct a junction barrier Schottky diode.

Description

Semiconductor device and manufacturing method thereof

The present disclosure relates to the technical field of semiconductors, in particular to semiconductor devices integrating junction barrier Schottky diodes and metal oxide semiconductor field effect transistors and manufacturing methods thereof.

In recent years, silicon carbide (SiC) materials have gradually replaced silicon to develop silicon carbide components due to their excellent physical and electrical properties, such as wide energy gap, high thermal conductivity, high breakdown electric field, etc. Compared with semiconductor components using silicon, silicon carbide components have many excellent characteristics, such as fast switching speed, low leakage current, low on-resistance, low power loss, etc. Therefore, silicon carbide components have been widely used in high-power power electronic systems. used as power components such as power switches and converters.

Common silicon carbide components are vertical double diffused metal-oxide-semiconductor transistors (VDMOS) field effect transistors. In electronic circuit applications, silicon carbide VDMOS field effect transistors usually need to be combined with a Anti-parallel diodes are used together to increase operating speed and reduce switching losses. One of them is a parasitic PIN type diode (phase-shifted switching diode) formed directly using the silicon carbide component itself. However, this parasitic PIN During operation, the diode will gradually deteriorate due to the recombination of electron holes, which will not only destroy the lattice structure of silicon carbide, reduce the reliability of silicon carbide components, or cause component failure. The other is to convert silicon carbide components It is packaged together with an external Schottky diode in anti-parallel connection, but this method will increase the area of the semiconductor component or The volume is not conducive to the need for size miniaturization and increases the cost.

In view of this, the present disclosure proposes a semiconductor device and a manufacturing method thereof. The semiconductor device integrates a junction barrier Schottky diode (JBS diode) into a metal oxide semiconductor field effect transistor (Metal oxide semiconductor field effect transistor). -Oxide-Semiconductor Field-Effect Transistor (MOSFET) structure, so the area of the semiconductor device will not be increased. At the same time, one of the purposes of setting up the JBS diode in this disclosure can also reduce the cost of adding the JBS diode to the traditional MOSFET. Compared with the traditional JBS-MOSFET integrated component due to the loss of source contact area, the semiconductor device of the present disclosure can further improve the source contact resistance.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a well region, a source region, a base region, a recess, a gate electrode, a first metal layer and a drain electrode. The substrate has a first conductivity type, the well region has a second conductivity type and is disposed in the substrate, the source region has a first conductivity type and is disposed in the well region, and the base region has a second conductivity type and is disposed in the substrate and the well region , and adjacent to the source region, the recess is provided in the substrate and adjacent to the base region, the gate electrode is provided on the well region, the first metal layer is provided on the source region and the base region, and is filled in the recess, the drain electrode The first metal layer is disposed on the back side of the substrate, and the first metal layer filled in the recess forms a junction barrier Schottky diode with the substrate.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, including the following steps: providing a substrate with a first conductivity type; forming a well region with a second conductivity type in the substrate; forming a source with the first conductivity type The pole region is in the well region; a base region with a second conductivity type is formed in the substrate and the well region, and the base region is adjacent to the source region; a gate electrode is formed on the well region; a recess is formed in the base and adjacent to the base region ; Forming a first metal layer on the source region and the base region, and filling the recess; and forming a drain electrode on the back of the substrate, wherein the first metal layer filled in the recess forms a junction barrier with the substrate, a Xiaochi diode body.

In order to make the features of the present disclosure clear and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

100:Semiconductor device

101: Base

102:Heavily doped region

103:Lightly doped epitaxial layer

105:Well area

107: Source area

109:Matrix area

111: Gate dielectric layer

113: Gate electrode

114:Oxide layer

115: Dielectric layer

116:Open your mouth

117: Metal silicide layer

119: Second metal layer

119A:Part 1

119B:Part 2

119C:Part 3

119D:Part 4

120:dent

121: First metal layer

123: Drain electrode

130:Patterned photoresist

132:Open your mouth

W1, W2: Width

D1: Depth

T1:Thickness

S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions may be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present disclosure are explained in detail, and the working principles of the specific embodiments of the present disclosure are explained. In addition, features in the drawings may not be drawn to actual scale for the sake of clarity, and therefore the dimensions of some features in some drawings may be intentionally exaggerated or reduced.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

Figures 3, 4, 5, 6, 7, 8, 9 and 10 illustrate some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Schematic cross-section.

The present disclosure provides several different embodiments that can be used to implement different features of the disclosure. To simplify explanation, examples of specific components and arrangements are also described in this disclosure. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or above the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". "There are other features between the features", so that the first feature and the second feature are not in direct contact. Additionally, various embodiments in the present disclosure may use repeated reference symbols and/or textual notations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.

In addition, for the space-related descriptive words mentioned in this disclosure, such as: "under", "low", "lower", "above", "above", "upper", "top" ", "bottom" and similar words are used to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings for the convenience of description. In addition to the orientation shown in the drawings, these spatially relative terms are used to describe possible orientations of semiconductor devices during use and operation. As a semiconductor device is oriented differently (rotated 90 degrees or otherwise), the spatially relative statements used to describe its orientation should be interpreted in a similar manner.

Although this disclosure uses terms such as first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not themselves imply or represent the element. There is no previous serial number, nor does it represent the order of arrangement of one component with another component, or the order of the manufacturing method. Therefore, a first element, component, region, layer, or block discussed below may also be termed a second element, component, region, layer, or block without departing from the scope of the specific embodiments of the disclosure. Of.

The terms "about" or "substantially" used in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "approximately" or "substantially", the meaning of "approximately" or "substantially" may still be implied.

The terms "coupling", "coupling" and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connections.

Although the invention of the present disclosure is described below through specific embodiments, the inventive principles of the present disclosure can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and these omitted details fall within the scope of knowledge of those with ordinary skill in the art.

This disclosure relates to integrating a junction barrier Schottky diode (JBS diode) into the structure of a planar silicon carbide metal oxide semiconductor field effect transistor (planar SiC MOSFET), thereby not increasing the area of the semiconductor device. And one of the purposes of the semiconductor device of the present disclosure is to use JBS diodes to improve the SiC lattice damage problem caused by the conventional PNP bicarrier diodes. At the same time, the arrangement of the JBS diodes can also reduce the traditional The source contact area of the MOSFET is lost due to the addition of the JBS diode. Therefore, compared with the traditional JBS-MOSFET integrated component, the semiconductor device of the present disclosure can further improve the source contact resistance to improve short-circuit energy (short-circuit energy). energy, Esc) and un-clamped avalanche energy (Eas) to improve the durability of semiconductor devices.

1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a substrate 101 with a first conductivity type (eg, n-type). The composition of the substrate 101 may be silicon carbide (SiC). , and the substrate 101 may include a heavily doped region 102 and a lightly doped epitaxial layer 103 located on the heavily doped region 102. The heavily doped region 102 is, for example, an n-type heavily doped substrate (N ⁺ Sub), and the lightly doped epitaxial layer 103 is The crystal layer 103 is, for example, an n-type lightly doped epitaxial layer (N ^- Epi). The well region 105 with a second conductivity type (for example, p-type) is disposed in the lightly doped epitaxial layer 103 of the substrate 101, and the source region 107 with a first conductivity type (for example, n-type) is disposed in the well region 105, The source region 107 is, for example, an n-type heavily doped region. In addition, a body region 109 having a second conductivity type (for example, p-type) is disposed in the lightly doped epitaxial layer 103 and the well region 105 of the substrate 101, and is adjacent to the source region 107. The doped body region 109 The impurity concentration is higher than that of the well region 105 , and the bottom surface of the base region 109 is lower than the bottom surface of the source region 107 . The base region 109 is, for example, a deep p-type heavily doped region (deep P ⁺ region). In one embodiment, as shown in FIG. 1 , the bottom surface of the base region 109 may be flush with the bottom surface of the well region 105 . In other embodiments, the bottom surface of the base region 109 may be higher or lower than the bottom surface of the well region 105 . In addition, the gate electrode 113 is disposed on the well region 105 and part of the source region 107 , and the gate dielectric layer 111 is disposed between the gate electrode 113 and the well region 105 , and between the gate electrode 113 and the source region 107 In between, the dielectric layer 115 covers the top surface and side walls of the gate electrode 113 . In this embodiment, the heavily doped region 102 of the substrate 101 can be a drain region, and the drain electrode 123 is disposed on the back side of the substrate 101 and adjacent to the heavily doped region 102 to form a vertical double-diffused metal oxide semiconductor field effect. Transistor (VDMOSFET) structure.

According to some embodiments of the present disclosure, the semiconductor device 100 includes a recess 120 formed in the lightly doped epitaxial layer 103 of the substrate 101 , and the recess 120 is adjacent to the base region 109 . As shown in FIG. 1 , the recess 120 is located between the two base regions 109 and extends downward from the front surface of the substrate 101 (for example, along the Z-axis direction) into the lightly doped epitaxial layer 103 . In some embodiments, , the depth D1 of the recess 120 may be 25% to 75% of the thickness T1 of the base region 109 , and the depth D1 within this range may provide a sufficient source contact area. In addition, as shown in FIG. 1 , in one embodiment, the recess 120 can also extend laterally (for example, along the X-axis direction) into the two base regions 109 . In some embodiments, the width W1 of the recess 120 in the base region 109 is more than 0% to 75% of the width W2 of the base region 109. For example, the width W1 can be 25% to 75% of the width W2. The width in this range W1 can further provide more source contact area. The semiconductor device 100 further includes a first metal layer 121 disposed on the source region 107 and the base region 109 and filled in the recess 120 . According to some embodiments of the present disclosure, the first metal layer 121 filled in the recess 120 and the substrate 101 form a junction barrier Schottky (JBS) diode. The JBS diode is located in the area of the VDMOSFET and therefore does not It will occupy additional layout area, which is beneficial to miniaturization of the size of the semiconductor device 100 . In addition, the first metal layer 121 also covers the dielectric layer 115 , and the dielectric layer 115 is located between the gate electrode 113 and the first metal layer 121 .

In addition, the semiconductor device 100 further includes a silicide layer 117 disposed on the source region 107 and the base region 109, and a second metal layer 119 sequentially disposed on the dielectric layer 115 and the silicide layer 117. and on the side walls and bottom of the recess 120. The second metal layer 119 includes a first portion 119A and a second portion 119B located in the recess 120 , wherein the first portion 119A is adjacent to the base region 109 and the second portion 119B is adjacent to the lightly doped epitaxial layer of the substrate 101 103. In addition, the second metal layer 119 also includes a The third part 119C and the fourth part 119D, wherein the third part 119C is disposed on the dielectric layer 115 , and the fourth part 119D is disposed on the metal silicide layer 117 . According to some embodiments of the present disclosure, the metal silicide layer 117 is made of a metal material that can form an ohmic contact with the semiconductor material, so the metal silicide layer 117 forms an ohmic contact with the source region 107 and the base region 109 . The second metal layer 119 is made of a metal material that will form a Schottky contact with the semiconductor material. Since the base region 109 is a heavily doped region, the first portion 119A of the second metal layer 119 will form an ohmic contact with the base region 109 , and the second portion 119B of the second metal layer forms Schottky contact with the lightly doped epitaxial layer 103 of the substrate 101 .

Figure 2 is a schematic cross-sectional view of a semiconductor device 100 according to another embodiment of the present disclosure. In this embodiment, the sidewalls of the recess 120 of the semiconductor device 100 are adjacent to the sidewalls of the base region 109, and the recess 120 does not extend laterally. to the base region 109. As shown in Figure 2, in one embodiment, the side walls of the recess 120 are at least in contact with the side walls of the base region 109, and the recess 120 does not extend into the base region 109 (that is, the recess 120 is in the base region 109 The width in is 0% of the width of the base region 109). In addition, in this embodiment, the first portion 119A of the second metal layer 119 is only located on the sidewall of the recess 120 . In addition, as shown in FIG. 2 , in one embodiment, the bottom surface of the base region 109 of the semiconductor device 100 may be lower than the bottom surface of the well region 105 .

According to some embodiments of the present disclosure, by forming the recess 120 in the substrate 101, the contact area between the second metal layer 119 and the base region 109 can be increased without increasing the overall projected area of the semiconductor device 100, for example, at least Increase the area of the base region 109 exposed to the sidewall of the recess 120, or further increase the area of the base region 109 exposed to the bottom surface of the recess 120. By increasing the contact area between the second metal layer 119 and the base region 109, the junction resistance and voltage drop between the second metal layer 119 and the base region 109 can be reduced. In addition, the bottom surface of the base region 109 can be lowered than the bottom surface of the source region 107 to reduce the pressure drop between the base region 109 and the adjacent well region 105 . Furthermore, by increasing the contact area between the second metal layer 119 and the base region 109, or further setting the bottom surface of the base region 109 lower than the bottom surface of the source region 107, the source region 107, the well region 105 and the light doping can be avoided. The parasitic bipolar transistor (parasitic BJT) composed of the hybrid epitaxial layer 103 is turned on to prevent the SiC lattice of the lightly doped epitaxial layer 103 from being destroyed, thereby improving the reliability of the semiconductor device 100 Spend.

Figures 3, 4, 5, 6, 7, 8, 9 and 10 illustrate some stages of a manufacturing method of the semiconductor device 100 according to an embodiment of the present disclosure. schematic cross-section diagram. Referring to Figure 3, first, a first conductivity type substrate 101 is provided. The composition of the substrate 101 may be 4H-type single crystal silicon carbide (4H-SiC), and the substrate 101 may include a heavily doped region 102, such as n-type heavily doped A SiC substrate and a lightly doped epitaxial layer 103, such as an n-type lightly doped SiC epitaxial layer, are grown on the heavily doped region 102. In some embodiments, the doping concentration of the heavily doped region 102 is, for example, 1x10 ¹⁹ to 1x 10 ²⁰ atoms/cm ³ , and the doping concentration of the lightly doped epitaxial layer 103 is, for example, 1x10 ¹⁵ To 1x 10 ¹⁶ atoms/cm 3 (atoms/cm ³ ). Then, in step S101, a patterned photoresist (not shown) is formed on the lightly doped epitaxial layer 103, and the patterned photoresist is used as a mask to form a second conductivity type well region 105 using an ion implantation process. For example, the p-type well region is in the lightly doped epitaxial layer 103 . In some embodiments, the doping concentration of the well region 105 is, for example, 1×10 ¹⁷ to 1×10 ¹⁸ atoms/cm ³ .

Next, referring to FIG. 4 , in step S103 , another patterned photoresist (not shown) is formed on the lightly doped epitaxial layer 103 , and this patterned photoresist is used as a mask to form a second patterned photoresist using an ion implantation process. A source region 107 of a conductivity type, such as an n-type heavily doped region, is located in the well region 105 . In some embodiments, the doping concentration of the source region 107 is, for example, 1×10 ¹⁹ to 1×10 ²⁰ atoms/cm ³ . Then, in step S105, another patterned photoresist (not shown) is formed on the lightly doped epitaxial layer 103, and this other patterned photoresist is used as a mask to form a second conductive layer using an ion implantation process. A type body region 109 , such as a deep p-type heavily doped region, is located in the lightly doped epitaxial layer 103 and the well region 105 of the substrate 101 . Afterwards, a high-temperature thermal annealing process may be performed to activate the dopants in the base region 109 , the source region 107 and the well region 105 . The base region 109 is adjacent to the source region 107 , and the doping concentration of the base region 109 is higher than the doping concentration of the well region 105 . In some embodiments, the doping concentration of the base region 109 is, for example, 5×10 ¹⁸ to 1×10 ²⁰ atoms/cm ³ . In some embodiments, the bottom surface of the base region 109 is lower than the bottom surface of the source region 107 , and the bottom surface of the base region 109 can be flush with the bottom surface of the well region 105 , or the bottom surface of the base region 109 can be lower than or higher than the well region. 105 on the bottom.

Next, referring to FIG. 5 , in step S107 , a gate dielectric layer 111 is formed on the front surface of the substrate 101 to cover the surface of the well region 105 , the source region 107 , the base region 109 and the lightly doped epitaxial layer 103 . Then, a deposition and patterning process is used to form a gate electrode 113 on the gate dielectric layer 111 , and the gate electrode 113 is located directly above the well region 105 and part of the source region 107 . In some embodiments, the gate dielectric layer 111 is composed of, for example, silicon oxide, and the thickness of the gate dielectric layer 111 may be approximately 400 Å to 500 Å. The composition of the gate electrode 113 is, for example, polycrystalline silicon, and the thickness of the gate electrode 113 may be approximately 2000 Å to 3000 Å. Then, in step S109, a thermal oxidation process is used to introduce oxygen and react with the polysilicon of the gate electrode 113 to form an oxide layer 114, such as a silicon oxide layer. On the top surface and side walls of the gate electrode 113, the oxide layer 114 has This facilitates the bonding between the gate electrode 113 and the subsequently formed dielectric layer.

6, in step S111, a deposition process such as a chemical vapor deposition process is used to form a dielectric layer 115 on the substrate 101, covering the gate electrode 113, the gate dielectric layer 111, the source region 107, The base region 109 and the lightly doped epitaxial layer 103 located on the front side of the substrate 101. The composition of the dielectric layer 115 is, for example, silicon oxide or other low dielectric constant dielectric materials, and the oxide layer 114 facilitates the bonding between the gate electrode 113 and the dielectric layer 115 . Then, in step S113, a patterned photoresist (not shown) is formed on the dielectric layer 115 as an etching mask, and an etching process is used to remove part of the dielectric layer 115 and the gate dielectric layer 111 below it. The opening 116 is formed to expose portions of the source region 107 , the base region 109 and the lightly doped epitaxial layer 103 located between the base region 109 .

Next, referring to FIG. 7 , in step S115 , first, a metal material layer is conformally deposited on the surface of the dielectric layer 115 and on the surface of the area exposed by the opening 116 . The composition of the metal material layer can be A metallic material such as nickel (Ni) that forms ohmic contact with a semiconductor material such as SiC. Then, a rapid thermal processing (RTP) silicidation process is used to react the metal material layer with SiC to form metal silicide, such as nickel silicide (NiSi), and remove unreacted metal on the dielectric layer 115 material to form a metal silicide layer 117 on the source region 107 , the base region 109 and the lightly doped epitaxial layer 103 between the base region 109 . Then, in step S117, the patterned photoresist 130 is formed On the substrate 101, the patterned photoresist 130 covers the dielectric layer 115, the gate electrode 113, the source region 107 and a part of the base region 109. The opening 132 of the patterned photoresist 130 corresponds to the recess to be formed subsequently. a predetermined area, and a part of the metal silicide layer 117 is exposed.

Then, referring to FIG. 8, in step S119, the patterned photoresist 130 shown in FIG. 7 is used as an etching mask. In one embodiment, an etching process is used to remove the metal silicide layer 117 exposed by the opening 132. A part of the lightly doped epitaxial layer 103 and a part of the base region 109 of the substrate 101 below it to form the recess 120 and leave the metal silicide layer 117 in the source region 107 and the base region 109 on the surface. In this embodiment, the sidewalls of the recess 120 may extend laterally into the base region 109 . In another embodiment, the opening 132 does not expose the base region 109 , and an etching process is used to remove a portion of the metal silicide layer 117 exposed by the opening 132 and the lightly doped epitaxial layer 103 of the substrate 101 below it. A portion of the recess 120 is formed. In this embodiment, the sidewalls of the recess 120 may be aligned with the sidewalls of the base region 109 adjacent to the lightly doped epitaxial layer 103 . In some embodiments, the width of the recess 120 can be controlled by the opening 132 of the patterned photoresist 130 so that the recess 120 can extend laterally into the base region 109 or the side walls of the recess 120 can contact the side walls of the base region 109 .

Afterwards, referring to FIG. 9 , in step S121 , the second metal layer 119 is deposited on the surface of the dielectric layer 115 and the metal silicide layer 117 , and on the sidewalls and bottom of the recess 120 . , the composition of the second metal layer 119 is a metal material, such as titanium (Ti), that can form Schottky contact with the semiconductor material (such as SiC).

Then, referring to FIG. 10 , in step S123 , the first metal layer 121 is formed on the second metal layer 119 , and the first metal layer 121 covers the dielectric layer 115 , the metal silicide layer 117 , the source region 107 and the base region 109 , and the first metal layer 121 is filled in the depression 120 . The composition of the first metal layer 121 is, for example, aluminum-copper alloy (AlCu) or other conductive metal materials. According to some embodiments of the present disclosure, the first metal layer 121 filled in the recess 120 and the substrate 101 form a junction barrier Schottky diode. Afterwards, referring to FIG. 1 , the drain electrode 123 is formed on the back surface of the substrate 101 to complete the semiconductor device 100 .

Semiconductor devices according to some embodiments of the present disclosure utilize recesses formed in a substrate, and the recesses are located between two base regions and adjacent to the base regions to form a junction barrier Schiff base (JBS) diode. This JBS The diode is integrated into the structure of the metal oxide semiconductor field effect transistor (MOSFET), so it does not increase the layout area of the semiconductor device. In addition, the second metal layer located in the recess and contacting the base region can form an ohmic contact with the heavily doped base region, and effectively increase the contact area between the first metal layer and the base region, thereby reducing the source contact resistance. Therefore, the short-circuit energy (Esc) and unclamped avalanche energy (Eas) tolerance of the semiconductor device will be improved due to the reduction of the source contact resistance, so as to improve the durability of the semiconductor device, which is beneficial to the application of high-power components .

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

100:Semiconductor device

101: Base

102:Heavily doped region

103:Lightly doped epitaxial layer

105:Well area

107: Source region

109:Matrix area

111: Gate dielectric layer

113: Gate electrode

115: Dielectric layer

117: Metal silicide layer

119: Second metal layer

119A:Part 1

119B:Part 2

119C:Part 3

119D:Part 4

120:dent

121: First metal layer

123: Drain electrode

W1, W2: Width

D1: Depth

T1:Thickness

Claims (10)

A semiconductor device, including: a substrate with a first conductivity type; a well region with a second conductivity type disposed in the substrate; a source region with the first conductivity type disposed in the well region within; a base region having the second conductivity type, disposed in the base and the well region, and adjacent to the source region; a recess, disposed in the base, and adjacent to the base region; a gate electrode, is disposed on the well region; a first metal layer is disposed on the source region and the base region, and is filled in the recess; and a drain electrode is disposed on the back side of the substrate, and is filled in the recess The first metal layer and the substrate form a junction barrier Schottky diode. The semiconductor device of claim 1, further comprising: a metal silicide layer disposed on the source region and the base region; and a second metal layer sequentially disposed on the metal silicide layer and the sidewalls and bottom of the recess, wherein the second metal layer located in the recess includes: a first portion adjacent to the base region; and a second portion adjacent to the substrate, wherein the metal silicide layer An ohmic contact is formed with the source region and the base region, the first portion of the second metal layer located in the recess forms an ohmic contact with the base region, and the third portion of the second metal layer located in the recess forms an ohmic contact with the base region. The two parts form Schottky contact with the substrate. The semiconductor device according to claim 2, further comprising a dielectric layer disposed between the gate electrode and the first metal layer, wherein the second metal layer is synchronously disposed on the dielectric layer. The semiconductor device of claim 1, wherein the depth of the recess is 25% to 75% of the thickness of the base region. The semiconductor device according to claim 1, wherein the sidewalls of the recess are adjacent to the sidewalls of the base region, or the recess extends laterally into the base region, and the width of the recess in the base region is equal to the width of the base region. 0% to 75%. The semiconductor device of claim 1, wherein the substrate is composed of silicon carbide, and the substrate includes a heavily doped region and a lightly doped epitaxial layer located on the heavily doped region, and the drain electrode is adjacent to the heavily doped region. doped region. The semiconductor device of claim 1, wherein the doping concentration of the base region is higher than the doping concentration of the well region, the bottom surface of the base region is lower than the bottom surface of the source region, and the bottom surface of the base region is in contact with the well region. The bottom surface of the well area is flush with or lower than the bottom surface of the well area. A method of manufacturing a semiconductor device, including: providing a substrate with a first conductivity type; forming a well region with a second conductivity type in the substrate; forming a source region with the first conductivity type in the substrate In the well region; forming a base region with the second conductivity type in the substrate and the well region, and the base region is adjacent to the source region; Forming a gate electrode on the well region; forming a recess in the substrate and adjacent to the base region; forming a first metal layer on the source region and the base region and filling the recess; and forming a The drain electrode is on the back side of the substrate, and the first metal layer filled in the recess and the substrate form a junction barrier Schottky diode. The manufacturing method of a semiconductor device as claimed in claim 8, further comprising: before forming the recess, forming a metal silicide layer on the substrate, the base region and the source region; forming a patterned photoresist having An opening corresponds to a predetermined area of the recess; etching removes a portion of the metal silicide layer and a portion of the substrate exposed by the opening to form the recess; and before forming the first metal layer, A second metal layer is formed on the metal silicide layer and on the side walls and bottom surface of the recess. The method of manufacturing a semiconductor device according to claim 9, wherein the opening of the patterned photoresist also corresponds to a part of the base region, and the part of the base region is removed by etching to form the recess.

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