TWI863441B - High voltage semiconductor device - Google Patents

Abstract

A high-voltage semiconductor device includes a substrate having a first conductivity type and an epitaxial layer having the first conductivity type stacked on the substrate. An isolation region is disposed in the epitaxial layer. A first well region having the first conductivity type is disposed in the epitaxial layer, and a source contact region having a second conductivity type is disposed in the first well region. A drain contact region having the second conductivity type is disposed in the epitaxial layer. A gate electrode is disposed on the epitaxial layer, where a portion of the gate electrode is extended laterally onto the isolation region. In addition, a deep trench isolation structure is disposed directly below the isolation region, located between the gate electrode and the drain contact region, and in the vertical projection direction, the deep trench isolation structure partially overlaps with the gate electrode.

Description

High voltage semiconductor device

The present disclosure relates to semiconductor technology, and more particularly to high voltage semiconductor devices including lateral diffused metal oxide semiconductor elements.

Metal-oxide semiconductor field effect transistor (MOSFET) is the most commonly used component in integrated circuits. It can be widely used as a high-power component or a high-voltage component in various power applications and power lines. High-voltage components are, for example, laterally-diffused metal-oxide semiconductor (LDMOS) field effect transistors (FETs). In order to achieve the effect of withstanding high voltage, the length of the drift region in the LDMOS can be expanded, however, this will cause the size of the component to increase. In addition, the two main characteristics pursued by high-voltage components are low on-state resistance (Ron) and high breakdown voltage, but the conventional lateral diffusion metal oxide semiconductor components cannot fully meet the aforementioned requirements.

In view of this, the present disclosure proposes a high-voltage semiconductor device including a laterally diffused metal oxide semiconductor (LDMOS) element, which has a deep trench isolation structure directly below the isolation region between the gate and the drain to reduce the surface electric field, and can reduce the impact ionization and electric field intensity occurring at the corner of the isolation region near the gate while maintaining the same element cell size, thereby increasing the breakdown voltage. At the same time, the high-voltage semiconductor device disclosed in the present disclosure can also reduce the element cell size while maintaining the same breakdown voltage, thereby reducing the on-resistance (Ron).

According to an embodiment of the present disclosure, a high voltage semiconductor device is provided, including a substrate, an epitaxial layer, an isolation region, a first well region, a source contact region, a drain contact region, a gate electrode, and a deep trench isolation structure. The substrate has a first conductivity type, the epitaxial layer has the first conductivity type and is stacked on the substrate, the isolation region is arranged in the epitaxial layer, the first well region has the first conductivity type and is arranged in the epitaxial layer, the source contact region has a second conductivity type and is arranged in the first well region, the drain contact region has the second conductivity type and is arranged in the epitaxial layer, the gate electrode is arranged on the epitaxial layer, and a portion of the gate electrode extends laterally to the isolation region, and the deep trench isolation structure is arranged directly below the isolation region, between the gate electrode and the drain contact region, and in the vertical projection direction, the deep trench isolation structure partially overlaps with the gate electrode.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the accompanying drawings.

100: High voltage semiconductor device

101-1: Base

101-2: Epitaxial layer

102: buried layer

103: Second well area

104: Shallow groove

105-1, 105-2: Isolation area

105S1: First side

105S2: Second side

106: Deep groove

107: Dielectric materials

109: Conductive part

109-1, 109-2, 109-3: Longitudinally separated parts

110: Deep trench isolation structure

111: First doped top layer

112: Second doped top layer

113: Fourth Well Area

115: Gate electrode

115P: Part of the gate electrode

117: First Well Area

119: Fifth Well Area

120: The third well area

121: Drain contact area

123: Source contact area

125: substrate contact area

127:Heavy mixing area

d1: first distance

d2: second distance

d3: third distance

d4: fourth distance

S101, S103, S105, S107, S109, S111, S113: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device according to an embodiment of the present disclosure.

Figure 2 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device according to another embodiment of the present disclosure.

FIG. 3 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device according to another embodiment of the present disclosure.

FIG. 4 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device according to another embodiment of the present disclosure.

FIG. 5 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device according to yet another embodiment of the present disclosure.

Figures 6, 7, 8 and 9 are cross-sectional schematic diagrams of some stages of a method for manufacturing a high voltage semiconductor device according to an embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. With the different orientations of the semiconductor device (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the invention principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a high voltage semiconductor device including a lateral diffused N-type metal oxide semiconductor (LD-NMOS) element, wherein a deep trench isolation (DTI) structure is disposed directly below an isolation region between a gate electrode and a drain contact region to reduce a surface electric field. The deep trench isolation structure is disposed directly below a portion of the isolation region near the gate electrode and between an edge of an active region and a doped top layer, the doped top layer being disposed directly below the isolation region. The high-voltage semiconductor device of the embodiment of the present disclosure can reduce the impact ionization and electric field strength occurring at the corner of the isolation region near the gate electrode while maintaining the same cell size, thereby increasing the breakdown voltage. In addition, the deep trench isolation structure includes a conductive portion, which can be electrically coupled to the ground terminal or the source electrode to further reduce the electric field, which is beneficial to increasing the breakdown voltage. In addition, the high-voltage semiconductor device of the embodiment of the present disclosure can also reduce the component cell size and reduce the on-resistance while maintaining the same breakdown voltage.

FIG. 1 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device 100 according to an embodiment of the present disclosure. The high-voltage semiconductor device 100 includes a substrate 101-1 and an epitaxial layer 101-2 stacked on the substrate 101-1. In one embodiment, the epitaxial layer 101-2 has a first conductivity type, such as a P-type epitaxial layer, and the substrate 101-1 may have a first conductivity type, such as a P-type substrate. The substrate 101-1 and the epitaxial layer 101-2 may each be composed of silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN) or other suitable semiconductor materials. Isolation regions 105-1 and 105-2 are disposed in epitaxial layer 101-2, gate electrode 115 is disposed on epitaxial layer 101-2, and a portion 115P of gate electrode 115 extends laterally onto isolation region 105-1. In some embodiments, isolation regions 105-1 and 105-2 may be shallow trench isolation (STI) structures or field oxide (FOX). The drain contact region 121 has a second conductivity type, such as an n-type heavily doped region (N ⁺ ), which is disposed in the epitaxial layer 101-2 and between the isolation regions 105-1 and 105-2. The drain contact region 121 can be electrically coupled to the drain electrode (not shown) via a drain contact in the interlayer dielectric layer. The first well region 117 has a first conductivity type, such as a p-type well region (PW), which is disposed in the epitaxial layer 101-2. The isolation region 105-1 and the first well region 117 are respectively located on both sides of the gate electrode 115. The source contact region 123 has a second conductivity type, such as an N-type heavily doped region (N ⁺ ), which is disposed in the first well region 117. The source contact region 123 can be electrically coupled to a source electrode (not shown) via a source contact in the interlayer dielectric layer. In addition, a bulk contact region 125 is also disposed in the first well region 117. The bulk contact region 125 has a first conductivity type, such as a P-type heavily doped region (P ⁺ ), which is adjacent to the source contact region 123. The bulk contact region 125 can be electrically coupled to a bulk electrode (not shown) via a conductive plug in the interlayer dielectric layer.

According to some embodiments of the present disclosure, the high voltage semiconductor device 100 includes a deep trench isolation (DTI) structure 110, which is disposed directly below the isolation region 105-1, between the gate electrode 115 and the drain contact region 121, and in the vertical projection direction (e.g., the Z-axis direction), the deep trench isolation structure 110 partially overlaps with the gate electrode 115. As shown in FIG. 1, the deep trench isolation structure 110 can directly contact a portion of the isolation region 105-1, and a portion 115P of the gate electrode 115 extends laterally to the portion of the isolation region 105-1. The deep trench isolation structure 110 includes a deep trench 106 disposed in the epitaxial layer 101-2, a conductive portion 109 disposed in the deep trench 106, and a dielectric material 107 filled in the deep trench 106 and surrounding the conductive portion 109. In some embodiments, the conductive portion 109 is composed of, for example, polysilicon, metal, or other conductive materials, and the dielectric material 107 is composed of, for example, silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or other suitable dielectric materials. In addition, in some embodiments, the conductive portion 109 can be electrically coupled to a ground terminal or a source electrode to reduce the electric field around the deep trench isolation structure 110. In other embodiments, the conductive portion 109 can be electrically coupled to the gate electrode, thereby achieving the effect of reducing the on-resistance during forward voltage operation. In addition, when the conductive portion 109 is composed of polysilicon, the conductive portion 109 can be a floating potential.

Still referring to FIG. 1 , the high voltage semiconductor device 100 further includes a first doped top layer 111 having a first conductivity type, such as a p-type doped top layer (PTOP). The first doped top layer 111 is disposed directly below the isolation region 105 - 1 and between the deep trench isolation structure 110 and the drain contact region 121 . In addition, the high voltage semiconductor device 100 may further include a second doped top layer 112 having a second conductivity type, such as an N-type doped top layer (NTOP). The second doped top layer 112 may be disposed directly above or directly below the first doped top layer 111 and directly below the isolation region 105-1. In one embodiment, the vertical projection areas of the first doped top layer 111 and the second doped top layer 112 may be the same and may be formed using the same mask. In some embodiments, the doping concentration of the second doped top layer 112 may be the same as the doping concentration of the first doped top layer 111. The provision of the first doped top layer 111 and the second doped top layer 112 can reduce the on-resistance (Ron) and increase the breakdown voltage. In other embodiments, the doping concentration of the second doped top layer 112 can be higher than the doping concentration of the first doped top layer 111 to further reduce the on-resistance.

As shown in FIG. 1 , the isolation region 105-1 has a first side 105S1 and a second side 105S2 opposite to each other, wherein the first side 105S1 is close to the gate electrode 115, and the second side 105S2 is close to the drain contact region 121. In some embodiments, the first doped top layer 111 and the second doped top layer 111 are 2 are vertically cut, and one side (e.g., the right side) of the first doped top layer 111 and the second doped top layer 112 is close to the second side 105S2 of the isolation region 105-1, and the other side (e.g., the left side) of the first doped top layer 111 and the second doped top layer 112 is adjacent to the deep trench isolation structure 110. In this embodiment, the deep trench isolation structure 110 is close to the first side 105S1 of the isolation region 105-1 and is far away from the first doped top layer 111 and the second doped top layer 112. The deep trench isolation structure 110 and the first doped top layer 111 and the second doped top layer 112 may be separated by a first distance d1, and the bottom surface of the deep trench isolation structure 110 is lower than the bottom surface of the first doped top layer 111.

Still referring to FIG. 1, the high voltage semiconductor device 100 further includes a buried layer 102 disposed in the substrate 101-1 and the epitaxial layer 101-2, and the buried layer 102 has a second conductivity type, such as an n-type buried layer (NBL). In addition, a second well region 103 is disposed in the epitaxial layer 101-2 and is located directly above the buried layer 102. In the horizontal direction (e.g., the X-axis direction), the lateral extension range of the second well region 103 is wider than that of the buried layer 102. For example, the buried layer 102 can extend to the second side 105S2 of the isolation region 105-1, while the second well region 103 extends to one side of another isolation region 105-2. The second well region 103 has a second conductivity type, such as an N-type high voltage well (HVNW), and the first well region 117, the deep trench isolation structure 110, the first doped top layer 111, the second doped top layer 112 and the drain contact region 121 are all located in the second well region 103. In addition, the high voltage semiconductor device 100 further includes a fourth well region 113, which has a first conductivity type, such as a P-type high voltage well (HVPW). The fourth well region 113 is disposed in the epitaxial layer 101-2, laterally separated from the second well region 103, and located outside another isolation region 105-2 and directly below a portion of the isolation region 105-2. The fifth well region 119 is disposed in the fourth well region 113, and the fifth well region 119 has a first conductivity type, such as a P-type well region (PW). The heavily doped region 127 is disposed in the fifth well region 119, and the heavily doped region 127 has a first conductivity type, such as a P-type heavily doped region (P ⁺ ). The heavily doped region 127 can be electrically connected to a conductive plug (not shown) in the interlayer dielectric layer, and electrically coupled to a wire (not shown) in the interconnect structure to provide a substrate potential to the substrate 101-1.

FIG. 2 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device 100 according to another embodiment of the present disclosure. The high-voltage semiconductor device 100 includes a deep trench isolation structure 110 disposed directly below the isolation region 105-1. The deep trench isolation structure 110 is located between the gate electrode 115 and the drain contact region 121, and in the vertical projection direction (e.g., the Z-axis direction), the deep trench isolation structure 110 partially overlaps with the gate electrode 115. In this embodiment, the deep trench isolation structure 110 is far from the first side 105S1 of the isolation region 105-1 and close to the first doped top layer 111 and the second doped top layer 112. The deep trench isolation structure 110 and the first side 105S1 of the isolation region 105-1 may be separated by a second distance d2, and the bottom surface of the deep trench isolation structure 110 is lower than the bottom surface of the first doped top layer 111. The features of other components of the high voltage semiconductor device 100 in FIG. 2 can refer to the relevant description of the high voltage semiconductor device 100 in FIG. 1, which will not be repeated here.

FIG. 3 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device 100 according to yet another embodiment of the present disclosure. The high-voltage semiconductor device 100 includes a deep trench isolation structure 110 disposed directly below the isolation region 105-1. The deep trench isolation structure 110 is located between the gate electrode 115 and the drain contact region 121, and in the vertical projection direction (e.g., the Z-axis direction), the deep trench isolation structure 110 partially overlaps with the gate electrode 115. In this embodiment, the deep trench isolation structure 110 extends from the first side 105S1 near the isolation region 105-1 to near the first doped top layer 111 and the second doped top layer 112, and the bottom surface of the deep trench isolation structure 110 is lower than the bottom surface of the first doped top layer 111. Compared with the high voltage semiconductor device 100 of FIGS. 1 and 2, the deep trench isolation structure 110 of the high voltage semiconductor device 100 of FIG. 3 has a greater length in the X-axis direction, which can reduce the electric field in a larger area around the deep trench isolation structure 110. The features of other components of the high voltage semiconductor device 100 in FIG. 3 can be found in the relevant description of the high voltage semiconductor device 100 in FIG. 1 above, and will not be repeated here.

FIG. 4 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device 100 according to yet another embodiment of the present disclosure. The high-voltage semiconductor device 100 includes a deep trench isolation structure 110 disposed directly below the isolation region 105-1. The deep trench isolation structure 110 is located between the gate electrode 115 and the drain contact region 121, and in the vertical projection direction (e.g., the Z-axis direction), the deep trench isolation structure 110 partially overlaps with the gate electrode 115. In this embodiment, the conductive portion of the deep trench isolation structure 110 includes a plurality of longitudinally separated (e.g., Z-axis direction) portions 109-1, 109-2, and 109-3, and the dielectric material 107 surrounds these longitudinally separated portions 109-1, 109-2, and 109-3. These portions 109-1, 109-2, and 109-3 can be electrically coupled to the ground terminal or the source electrode separately or in common to increase the breakdown voltage. In some embodiments, the deep trench isolation structure 110 and the first doped top layer 111 and the second doped top layer 112 may be separated by a third distance d3, the deep trench isolation structure 110 and the first side 105S1 of the isolation region 105-1 may be separated by a fourth distance d4, and the bottom surface of the deep trench isolation structure 110 is much lower than the bottom surface of the first doped top layer 111. In one embodiment, the bottom surface of the first doped top layer 111 is located in the second well region 103, and the bottom surface of the deep trench isolation structure 110 is located in the buried layer 102. The features of other components of the high voltage semiconductor device 100 in FIG. 4 can be found in the relevant description of the high voltage semiconductor device 100 in FIG. 1 above, and will not be repeated here.

FIG. 5 is a schematic cross-sectional view of the right half of a mirror-symmetrical high-voltage semiconductor device 100 according to another embodiment of the present disclosure. The high-voltage semiconductor device 100 includes a deep trench isolation structure 110 disposed directly below the isolation region 105-1. The deep trench isolation structure 110 is located between the gate electrode 115 and the drain contact region 121, and in the vertical projection direction (e.g., the Z-axis direction), the deep trench isolation structure 110 partially overlaps with the gate electrode 115. In this embodiment, the high voltage semiconductor device 100 further includes a third well region 120 disposed in the second well region 103, and the deep trench isolation structure 110 is located in the third well region 120, and the third well region 120 may surround the deep trench isolation structure 110. In one embodiment, the third well region 120 may extend from the first side 105S1 near the isolation region 105-1 to near the first doped top layer 111 and the second doped top layer 112. The third well region 120 has a second conductivity type, such as an N-type well region (NW). In some embodiments, the doping concentration of the third well region 120 is higher than the doping concentration of the second well region 103 and lower than the doping concentration of the second doped top layer 112. By adding the third well region 120, the on-resistance of the high-voltage semiconductor device 100 can be reduced. In addition, the bottom surface of the deep trench isolation structure 110 and the bottom surface of the third well region 120 are both lower than the bottom surface of the first doped top layer 111. The features of other components of the high-voltage semiconductor device 100 in FIG. 5 can refer to the relevant description of the high-voltage semiconductor device 100 in FIG. 1, which will not be repeated here.

In addition, in the embodiments of Figures 1 to 5, when viewed from a top view, the source contact region 123, the gate electrode 115, and the drain contact region 121 all have annular planar patterns, and these annular patterns are the source contact region 123, the gate electrode 115, and the drain contact region 121 from the inside to the outside. In addition, the mirror symmetry center line of the mirror symmetric high voltage semiconductor device 100 is at the substrate contact region 125.

FIG. 6, FIG. 7, FIG. 8 and FIG. 9 are cross-sectional schematic diagrams of some stages of a method for manufacturing a high voltage semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 6, in step S101, a substrate 101-1 and an epitaxial layer 101-2 grown thereon are first provided. In one embodiment, the substrate 101-1 is, for example, a P-type substrate, the epitaxial layer 101-2 is, for example, a P-type epitaxial layer, and the substrate 101-1 and the epitaxial layer 101-2 can each be composed of silicon (Si) or silicon carbide (SiC). Then, an ion implantation process and a mask are used to implant N-type dopants into the substrate 101-1 and the epitaxial layer 101-2 to form a buried layer 102, for example, an N-type buried layer (NBL). Then, an ion implantation process and another mask are used to implant N-type dopants in the epitaxial layer 101-2 to form a second well region 103 located on the buried layer 102. The second well region 103 is, for example, an N-type high voltage well region (HVNW). The vertical projection area of the second well region 103 may be larger than the vertical projection area of the buried layer 102, and the second well region 103 completely covers the buried layer 102. The doping concentration of the buried layer 102 may be higher than the doping concentration of the second well region 103. In some embodiments, the doping concentration of the buried layer 102 is, for example, about 5E15 to 1E17 cm ^-3 , and the doping concentration of the second well region 103 is, for example, about 1E15 to 5E16 cm ^-3 .

Continuing to refer to FIG. 6, in step S103, a plurality of shallow trenches 104 are etched on the surface of the epitaxial layer 101-2 using photolithography and etching processes, and then another photolithography and another etching process are used to etch deep trenches 106 in the epitaxial layer 101-2. In some embodiments, the shallow trenches 104 may be formed first, and then the deep trenches 106 may be formed, but this is not limited thereto. From a top view, the deep trench 106 may have a ring shape, and the shallow trench 104 may have two ring shapes, one inside and one outside, wherein the deep trench 106 is located directly below the inner ring-shaped shallow trench 104. The photolithography and etching processes for forming the deep trench 106 may be used to adjust the relative position of the subsequently formed deep trench isolation structure 110 and the isolation region 105-1, and to adjust the size of the deep trench isolation structure 110.

Next, referring to FIG. 7, in step S105, a deposition or thermal oxidation process may be used to sequentially form a dielectric material 107 in the shallow trench 104 and the deep trench 106. The dielectric material 107 is, for example, a silicon oxide layer, wherein the dielectric material 107 formed in the deep trench 106 serves as a part of the deep trench isolation structure 110. Then, a deposition process is used to fill the deep trench 106 with a conductive material, such as doped polysilicon or a metal material, to form a conductive portion 109 of the deep trench isolation structure 110, and the conductive material outside the deep trench 106 is removed.

Continuing to refer to FIG. 7, in step S107, in some embodiments, a deposition process and a chemical mechanical planarization process are used to fill the shallow trench 104 with a dielectric material to form isolation regions 105-1 and 105-2, such as a shallow trench isolation (STI) structure, wherein the deep trench isolation structure 110 is located directly below the isolation region 105-1. In some embodiments, the deep trench isolation structure 110 may be close to the inner edge of the isolation region 105-1, or the deep trench isolation structure 110 may be separated from the inner edge of the isolation region 105-1 by a distance.

Then, referring to FIG. 8 , in step S109, an ion implantation process and a mask are used to implant P-type dopants in the epitaxial layer 101-2 to form a fourth well region 113, such as a P-type high voltage well region (HVPW), which surrounds the isolation region 105-2 and is located below a portion of the isolation region 105-2. In some embodiments, the doping concentration of the fourth well region 113 is, for example, about 1E16 to 5E17 cm ^-3 . Next, an ion implantation process and another mask are used to implant P-type dopants in the second well region 103 to form a first doped top layer 111, such as a P-type doped top layer (PTOP). Another ion implantation process and the same mask are used to implant N-type dopants in the second well region 103 to form a second doped top layer 112, such as an N-type doped top layer (NTOP), so that the second doped top layer 112 and the first doped top layer 111 have the same vertical projection area. The second doped top layer 112 may be located above or below the first doped top layer 111. In addition, the first doped top layer 111 and the second doped top layer 112 are both located directly below the isolation region 105-1 and laterally separated from the deep trench isolation structure 110. In some embodiments, the first doped top layer 111 and the second doped top layer 112 may have the same doping concentration, for example, about 5E16 to 5E17 cm ^-3 . In some other embodiments, the doping concentration of the second doped top layer 112 may be higher than the doping concentration of the first doped top layer 111.

Continuing to refer to FIG. 8, in step S111, a gate electrode 115 is formed on the surface of the epitaxial layer 101-2 using deposition, photolithography and etching processes, and a portion of the gate electrode 115 extends laterally to a portion of the isolation region 105-1, wherein the gate electrode 115 located on the isolation region 105-1 partially overlaps with the deep trench isolation structure 110 in the vertical projection direction. In some embodiments, the gate electrode 115 is composed of, for example, polysilicon.

Next, referring to FIG. 9, in step S113, an ion implantation process and a mask are used to implant P-type dopants in the second well region 103 to form a first well region 117, such as a P-type well region (PW). At the same time, P-type dopants are implanted in the fourth well region 113 to form a fifth well region 119, such as a P-type well region (PW). In some embodiments, the first well region 117 and the fifth well region 119 may have the same doping concentration, such as about 5E16 to 5E17 cm ^-3 . Then, using another ion implantation process and another mask, N-type dopants are implanted in the second well region 103 to form a drain contact region 121, such as an N-type heavily doped region (N ⁺ ), which is located between the isolation regions 105-1 and 105-2. At the same time, N-type dopants are implanted in the first well region 117 to form a source contact region 123, such as an N-type heavily doped region (N ⁺ ). In some embodiments, the drain contact region 121 and the source contact region 123 may have the same doping concentration, such as about 5E18 to 5E19 cm ^-3 . Thereafter, another ion implantation process and another mask are used to implant P-type dopants into the first well region 117 to form a substrate contact region 125, such as a P-type heavily doped region (P ⁺ ). At the same time, P-type dopants are implanted into the fifth well region 119 to form a heavily doped region 127, such as a P-type heavily doped region (P ⁺ ). In some embodiments, the substrate contact region 125 and the heavily doped region 127 may have the same doping concentration, such as approximately 5E18 to 5E19 cm ^-3 . According to the manufacturing methods of FIGS. 6 , 7 , 8 and 9 , the high voltage semiconductor device 100 of some embodiments of the present disclosure may be completed.

According to some embodiments of the present disclosure, a deep trench isolation structure is provided directly below the isolation region between the gate electrode and the drain contact region of a high voltage semiconductor device to reduce the surface electric field, thereby reducing the impact ionization (I.I.) and electric field strength occurring at the corner of the isolation region near the gate electrode while maintaining the same cell size, thereby increasing the breakdown voltage.

Compared to a high voltage semiconductor device that does not include the second doped top layer 112 and the deep trench isolation structure 110 of some embodiments of the present disclosure, and a high voltage semiconductor device that does not include the deep trench isolation structure 110 of some embodiments of the present disclosure, under the condition of the same element cell pitch, the high voltage semiconductor device 100 of some embodiments of the present disclosure can increase the static breakdown voltage (BVoff) by more than about 26% and reduce the maximum impact ionization (Max.I.I.) occurring on the first side 105S1 of the isolation region 105-1 by more than about 96%. In addition, under the condition of maintaining the same static breakdown voltage (BVoff), the high voltage semiconductor device 100 of some embodiments disclosed herein can reduce the component unit spacing, thereby reducing the on-resistance (Ron).

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: High voltage semiconductor device

101-1: Base

101-2: Epitaxial layer

102: buried layer

103: Second well area

105-1, 105-2: Isolation area

105S1: First side

105S2: Second side

106: Deep groove

107: Dielectric materials

109: Conductive part

110: Deep trench isolation structure

111: First doped top layer

112: Second doped top layer

113: Fourth Well Area

115: Gate electrode

115P: Part of the gate electrode

117: First Well Area

119: Fifth Well Area

121: Drain contact area

123: Source contact area

125: substrate contact area

127:Heavy mixing area

d1: first distance

Claims (10)

A high voltage semiconductor device comprises: a substrate having a first conductivity type; an epitaxial layer having a first conductivity type and stacked on the substrate; an isolation region disposed in the epitaxial layer; a first well region having the first conductivity type and disposed in the epitaxial layer; a source contact region having a second conductivity type and disposed in the first well region; a drain contact region having the second conductivity type and disposed in the first well region; The second conductivity type is arranged in the epitaxial layer; a gate electrode is arranged on the epitaxial layer, and a portion of the gate electrode extends laterally to the isolation region; and a deep trench isolation structure is arranged directly below the isolation region, between the gate electrode and the drain contact region, and in the vertical projection direction, the deep trench isolation structure partially overlaps with the gate electrode. The high voltage semiconductor device as described in claim 1 further comprises: a first doped top layer having the first conductivity type, disposed directly below the isolation region and between the deep trench isolation structure and the drain contact region; and a second doped top layer having the second conductivity type, disposed directly above or directly below the first doped top layer and directly below the isolation region. The high voltage semiconductor device as described in claim 2 further comprises: a second well region having the second conductivity type and disposed in the epitaxial layer, wherein the first well region, the deep trench isolation structure, the first doped top layer, the second doped top layer and the drain contact region are all located in the second well region; a third well region having the second conductivity type and disposed in the second well region, and the deep trench isolation structure is located in the third well region. A high voltage semiconductor device as described in claim 3, wherein the doping concentration of the third well region is higher than the doping concentration of the second well region and lower than the doping concentration of the second doped top layer. A high voltage semiconductor device as described in claim 2, wherein a first side of the isolation region is close to the gate electrode, a second side of the isolation region is close to the drain contact region, and the deep trench isolation structure is close to the first side and away from the first doped top layer and the second doped top layer. A high voltage semiconductor device as described in claim 2, wherein a first side of the isolation region is close to the gate electrode, a second side of the isolation region is close to the drain contact region, and the deep trench isolation structure is away from the first side and close to the first doped top layer and the second doped top layer. A high voltage semiconductor device as described in claim 2, wherein a first side of the isolation region is close to the gate electrode, a second side of the isolation region is close to the drain contact region, and the deep trench isolation structure extends from close to the first side to close to the first doped top layer and the second doped top layer. A high voltage semiconductor device as described in claim 2, wherein the deep trench isolation structure directly contacts a portion of the isolation region, the portion of the gate electrode extends laterally onto the portion of the isolation region, and the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first doped top layer. A high voltage semiconductor device as described in claim 1, wherein the deep trench isolation structure comprises: a deep trench disposed in the epitaxial layer; a conductive portion disposed in the deep trench and electrically coupled to a ground terminal or a source electrode; and a dielectric material filled in the deep trench and surrounding the conductive portion. A high voltage semiconductor device as described in claim 9, wherein the conductive portion includes a plurality of longitudinally separated parts, and the dielectric material surrounds the plurality of parts.

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