TWI805981B - Semiconductor light-emitting device - Google Patents

Abstract

A semiconductor light-emitting device includes: a substrate; a semiconductor stack formed on the substrate; a recess region; a first protective structure formed on the semiconductor stack, and including a first upper surface and a bending region formed corresponding to the recess region; and a second protective structure covering the bending region and including a second upper surface; wherein the first protective structure includes a seam extending from the first upper surface into the first protective structure, the second protective structure is disposed in the seam, wherein a portion of the second upper surface corresponding to the bending region is flatter or smoother than a portion of the first upper surface corresponding to the recess region.

Description

Semiconductor light emitting element

This case relates to a semiconductor element, especially a semiconductor light emitting element.

Light-emitting diodes (Light-Emitting Diodes, LEDs) have good characteristics such as low power consumption, low heat generation, long operating life, shock resistance, small size, and fast response speed, so they are suitable for various lighting and display applications. In addition to requiring good luminous efficiency, LEDs also need to have good reliability. An LED often needs to go through many strict reliability tests to prove its durability for a certain service life. How to make LEDs have better reliability is a goal that the industry is striving for.

A semiconductor light-emitting element, comprising a substrate; a semiconductor stack formed on the substrate; a recessed area; a first protection structure formed on the semiconductor stack, and including a first upper surface and a turning area corresponding to the recess region formation; and a second protection structure covering the turning region and comprising a second upper surface; wherein the first protection structure comprises a crack extending from the first upper surface into the first protection structure, and the second protection structure is located in the crack Among them, the part of the second upper surface corresponding to the turning area is flatter or smoother than the part of the first upper surface corresponding to the concave area.

A semiconductor light-emitting element, comprising a substrate; a semiconductor stack formed on the substrate; a plurality of recessed regions; a first protection structure formed above the semiconductor stack and the substrate, including a first upper surface and a first lower surface The surface is opposite to the first upper surface; a second protection structure is formed between the first protection structure and the semiconductor stack and/or substrate and is located in the recessed region, wherein the second protection structure includes a second upper surface and a The second lower surface is opposite to the second upper surface; wherein, the first upper surface of the first protection structure corresponding to the recessed area and/or the second upper surface of the second protection structure corresponding to the recessed area is a substantially flat surface.

In order to make the description of this disclosure more detailed and complete, please refer to the description of the following embodiments together with the relevant figures. However, the following examples are used to illustrate the semiconductor light-emitting device of the present disclosure, and the present disclosure is not limited to the following examples. In addition, the size, material, shape, relative arrangement, etc. of the components described in the embodiments in this specification are not limited, and the scope of the present disclosure is not limited thereto, but is merely a description. In addition, the size and positional relationship of components shown in the drawings may be exaggerated for clarity. In the following description, in order to appropriately omit detailed description, members of the same or similar nature are shown with the same names and symbols.

FIG. 1 is a top view of an embodiment of a semiconductor light emitting device 1 of the present disclosure. Fig. 2 is a cross-sectional view of the semiconductor light emitting element 1 along the line segment A-A' in Fig. 1 .

Please refer to FIG. 1 and FIG. 2. According to an embodiment of the present disclosure, a semiconductor light emitting device 1 includes a substrate 10, a semiconductor stack 20, a first electrode 30, a second electrode 40, a first protection structure 50, and a second protection structure. 60 , the third electrode 70 and the fourth electrode 80 . The semiconductor stack 20 is located on the upper surface 10 a of the substrate 10 . The semiconductor stack 20 sequentially includes a first semiconductor layer 201 , an active layer 203 and a second semiconductor layer 202 from the upper surface 10 a of the substrate. The first semiconductor layer 201 has an upper surface 201 a not covered by the active layer 203 and the second semiconductor layer 202 . The upper surface 10 a of the substrate 10 has an exposed region 100 not covered by the first semiconductor layer 201 , the active layer 203 and the second semiconductor layer 202 . In one embodiment, the exposed region 100 surrounds the semiconductor stack 20 . The first electrode 30 includes a first contact portion 31 and a first extension portion 32 . The second electrode 40 includes a second contact portion 41 and a second extension portion 42 . The first protection structure 50 covers the semiconductor stack 20 , the substrate 10 , the first electrode 30 and the second electrode 40 . As shown in FIG. 1 , the first protection structure 50 includes two openings 501 , 502 corresponding to the first contact portion 31 of the first electrode 30 and the second contact portion 41 of the second electrode 40 . The second protection structure 60 covers part or all of the first protection structure 50 . The third electrode 70 and the fourth electrode 80 are respectively formed on the first electrode 30 and the second electrode 40 . The third electrode 70 is electrically connected to the first contact portion 31 of the first electrode 30 through the opening 501 of the first protective structure 50, and the fourth electrode 80 is electrically connected to the second electrode 40 through the opening 502 of the first protective structure 50. The first contact portion 41 .

The substrate 10 is a growth substrate for epitaxial growth of the semiconductor stack 20 . The substrate 10 includes a gallium arsenide (GaAs) wafer for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or for growing gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride ( AlGaN) sapphire (Al2O3) wafers, gallium nitride (GaN) wafers silicon carbide (SiC) wafers, or aluminum nitride (AlN) wafers. Alternatively, the substrate 10 is a supporting substrate, including conductive materials such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), carbonized Silicon (SiC) or alloys of the above materials, or thermally conductive materials such as diamond, graphite, or aluminum nitride. The growth substrate originally used to epitaxially grow the semiconductor stack 20 can be selectively removed according to the needs of the application, and then the semiconductor stack 20 is transferred to the aforementioned supporting substrate.

Please refer to FIG. 2 , the surface of the substrate 10 in contact with the semiconductor stack 20 has a roughened surface, and the roughened surface can be a surface with an irregular shape or a surface with a regular shape. For example, the substrate 10 includes one or more characteristic parts 11 protruding or recessed on the upper surface 10 a of the substrate 10 , and the characteristic parts 11 are components including a hemispherical shape, a conical shape, or a polygonal pyramid shape. In other embodiments, the side of the substrate 10 in contact with the semiconductor stack 20 is a flat surface.

In one embodiment, by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating method to A semiconductor stack is formed on the substrate 10, such as a semiconductor stack 20 having optoelectronic properties, such as a light-emitting stack, wherein the physical vapor deposition method includes sputtering or evaporation. Next, a platform is formed on the semiconductor stack 20 to expose the upper surface 201 a of the first semiconductor layer 201 by an etching process, and part of the semiconductor stack 20 is removed to form an exposed region 100 on the substrate 10 .

By changing the physical and chemical composition of one or more layers in the semiconductor stack 20 (such as the first semiconductor layer 201 , the second semiconductor layer 202 and the active layer 203 ), the wavelength of the light emitted by the semiconductor light emitting element 1 can be adjusted. The material of the semiconductor stack 20 includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, wherein x≧0, y≦1, and ( x+y)≦1. When the material of the semiconductor stack 20 is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack 20 is an InGaN series material, it can emit blue light with a wavelength between 400 nm and 490 nm. When the material of the semiconductor stack 20 is AlGaN series or AlInGaN series materials, it can emit ultraviolet light with a wavelength between 400 nm and 250 nm.

The first semiconductor layer 201 and the second semiconductor layer 202 can be cladding layers (cladding layer), both of which have different conductivity types, electric properties, polarities, or provide electrons or holes according to doped elements, such as the first The first semiconductor layer 201 is an n-type semiconductor, and the second semiconductor layer 202 is a p-type semiconductor. The active layer 203 is formed between the first semiconductor layer 201 and the second semiconductor layer 202 . Electrons and holes are driven by a current to recombine in the active layer 203 to convert electrical energy into light energy to emit a light. The active layer 203 can be single heterostructure (single heterostructure, SH), double heterostructure (double heterostructure, DH), double-side double heterostructure (double-side double heterostructure, DDH), or multi-layer quantum well structure (multi-quantum well, MQW). The material of the active layer 203 can be neutral, p-type or n-type semiconductor. The first semiconductor layer 201 , the second semiconductor layer 202 , or the active layer 203 can be a single layer or a structure including multiple layers.

In addition, the semiconductor stack 20 also includes a buffer layer (not shown) located between the first semiconductor layer 201 and the substrate 10 to release the stress between the substrate 10 and the semiconductor stack 20 due to material lattice mismatch. , to reduce misalignment and lattice defects, thereby improving epitaxy quality. The buffer layer can be a single layer or a structure comprising multiple layers. The material of the buffer layer includes GaN, AlGaN or AlN. In one embodiment, the buffer structure includes multiple sub-layers (not shown). The sublayers comprise the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the growth method of the first sublayer is sputtering, and the growth method of the second sublayer is MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The growth method of the third sublayer is MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sub-layers comprise the same material, such as AlN, or different materials, such as a combination of AlN, GaN and AlGaN. In other embodiments, PVD-aluminum nitride (PVD-AlN) is used as a buffer layer, and the target material used to form PVD-aluminum nitride is composed of aluminum nitride, or a target material composed of aluminum is used and Aluminum nitride is reactively formed in the presence of a nitrogen source.

The materials of the first electrode 30 and the second electrode 40 include metals, such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), Metals such as nickel (Ni), rhodium (Rh) or platinum (Pt), or alloys or laminates of the above materials. In some embodiments, the first electrode 30 and/or the second electrode 40 is a single layer, or a structure including multiple layers such as Ti/Au layer, Ti/Al layer, Ti/Pt/Au layer, Cr/Au layer layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer, Ti/Al/Ti/Au layer, Cr/Ti/Al/Au layer, Cr/Al/Ti/Au layer, Cr/ Al/Ti/Pt layer or Cr/Al/Cr/Ni/Au layer, or a combination thereof.

Please refer to FIG. 2 , the first protection structure 50 is a single-layer or multi-layer structure, and includes a first upper surface 50a. In one embodiment, the first protection structure 50 is a single-layer structure, including non-conductive materials such as dielectric materials such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), Titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). In another embodiment, the first protection structure 50 is a structure comprising a plurality of layers, for example, two or more material layers with different refractive indices are alternately stacked to form a distributed Bragg reflector (DBR) structure, which is used to Light from the active layer 203 is reflected to one side of the substrate 10 . For example, a high-reflectivity DBR structure is formed by stacking layers such as SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ . When the wavelength of light emitted by the semiconductor light emitting element 1 is λ, the optical thickness of the distributed Bragg reflector (DBR) structure is set to be an integer multiple of λ/4. The optical thickness of the distributed Bragg reflector (DBR) structure may have a deviation of ±30% on the basis of integer multiples of λ/4. In one embodiment, the formation method of the first protection structure 50 includes physical vapor deposition (PVD), electron beam evaporation (E-gun Evaporation), thermal evaporation (Thermal Evaporation), atomic layer deposition (Atomic Layer Deposition, ALD) or plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD).

The material of the second protection structure 60 includes flowable material. Since the material of the second protection structure 60 has flowability, it can be anisotropically formed in the turning region 52 and/or the crack 54 of the first protection structure 50 , which will be described in detail later. In one embodiment, the second protection structure 60 is formed by a spin coating medium. The flowable material includes organic material or inorganic material. Organic materials include photosensitive materials, polymer materials or combinations thereof. Photosensitive materials include Su-8, benzocyclobutene (BCB). Polymer materials include perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalic acid Ethylene glycol ester (PET), polycarbonate (PC), polyetherimide (PI), or fluorocarbon polymer. Inorganic materials include silicon-containing materials such as siloxanes. The second protection structure 60 can be formed on the semiconductor light emitting device 1 by anisotropically forming the above-mentioned flowable material. The anisotropic forming method includes a spin coating method.

The materials of the third electrode 70 and the fourth electrode 80 include metals, such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), Metals such as nickel (Ni), rhodium (Rh) or platinum (Pt), or alloys or laminates of the above materials. In some embodiments, the third electrode 70 and/or the fourth electrode 80 is a single layer, or includes a multi-layer structure. In some embodiments, an electrode bonding pad (not shown) is formed above the third electrode 70 and/or the fourth electrode 80 respectively. In another embodiment, the electrode bonding pad can be formed in the same process as the third electrode 70 and/or the fourth electrode 80, or a suitable material can be selected for the third electrode 70 and/or the fourth electrode 80, which are respectively An electrode bonding pad. The electrode bonding pads contain metal materials such as Sn, Au and other metal elements or a single layer or multi-layer stack structure such as Sn/Ag, Sn/Au, Sn/AuSn, SnAg/Sn, SnAg/AuSn, SnAg/Sn/ AuSn, or a combination thereof, is used to connect the carrier board in the wire bonding or soldering process, so as to electrically connect the semiconductor light-emitting element 1 with an external power source or external electronic components.

In some embodiments, the first electrode 30 , the second electrode 40 , the third electrode 70 and the fourth electrode 80 respectively include a thickness between 1 μm and 100 μm, preferably between 1.2 μm and 60 μm, more preferably Between 1.5μm and 6μm.

In some embodiments, a transparent conductive layer 28 is formed on the upper surface 202 a of the second semiconductor layer 202 and is in electrical contact with the second semiconductor layer 202 for laterally spreading current. The first electrode 30 is located on the upper surface 201 a of the first semiconductor layer 201 and is electrically connected to the first semiconductor layer 201 . The second electrode 40 is located on the upper surface 202 a of the second semiconductor layer 202 and is electrically connected to the second semiconductor layer 202 through the transparent conductive layer 28 . The material of the transparent conductive layer 28 includes a material transparent to the light emitted by the active layer 203 , such as metal or transparent conductive oxide. The metal transparent conductive layer 28 is selected from thin metal layers with light transmission. Transparent conductive oxides include graphene, indium tin oxide (ITO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO), or indium zinc oxide (IZO).

Please refer to FIG. 2, the semiconductor light emitting element 1 may further include a current blocking layer 26 located between the transparent conductive layer 28 and the second semiconductor layer 202, and/or between the first electrode 30 and the first semiconductor layer 201 (not shown in the figure). ). The transparent conductive layer 28 includes an opening (not shown) located below the second contact portion 41 of the second electrode 40, exposing the second semiconductor layer 202 and/or the current blocking layer 26, and the second contact portion 41 can pass through the transparent conductive layer 28. The opening contacts the second semiconductor layer 202 . In other embodiments, the current blocking layer located between the first electrode 30 and the first semiconductor layer 201, and/or the current blocking layer 26 between the transparent conductive layer 28 and the second semiconductor layer 201 also includes a plurality of discontinuous current The blocking blocks are respectively arranged corresponding to the first electrode 30 and the second electrode 40 . In one embodiment, the current blocking block is located below the first contact portion 31 and the first extension portion 32, and/or below the second contact portion 41 and the second extension portion 42, and the width of the current blocking block is respectively larger or smaller than the first contact portion 31 and the second extension portion 42. A width of the contact portion 31 and the first extension portion 32 and/or the second contact portion 41 and the second extension portion 42 .

The current blocking layer 26 is formed of non-conductive materials, including dielectric materials such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). In an alternative example, the current blocking layer 26 may include a distributed Bragg reflector (DBR) structure, wherein the DBR structure is formed by stacking insulating materials with different refractive indices. In order to increase the light extraction efficiency of the semiconductor light emitting element 1 , the current blocking layer 26 has a light reflectance of more than 80% for the light emitted by the active layer 203 .

FIG. 3 is a partial cross-sectional SEM photo of an embodiment of a semiconductor light-emitting element 1 of the present disclosure, showing part of the substrate 10, the first semiconductor layer 201 in FIG. The protection structure 50 and the second protection structure 60 .

Referring to Figures 2 and 3, the structure of the semiconductor light emitting element 1 itself has one or more recessed regions 12 caused by height differences. For example, the height difference between the first semiconductor layer 201 and the first electrode 30, such as the first extension 32, forms the recessed region 12; and the height difference between the semiconductor stack 20 and the surface of the substrate 10 forms the recessed region 12; and the substrate 10 itself The difference in elevation of the roughened surface results in a plurality of depressed regions 12 . In one embodiment, the recessed region 12 is located at the junction of the first semiconductor layer 201 and the first electrode 30 (such as the first extension 32 ), at the junction of the semiconductor stack 20 and the substrate 10 , and/or at between the feature portions 11 of the substrate 10 . In other embodiments, such as between the first semiconductor layer 201 and the first contact portion 31 of the first electrode 30, between the second contact portion 41 of the second electrode 40 and/or the second extension portion 42 and the second semiconductor layer 202 And/or the height difference between the transparent conductive layers 28 will also cause a recessed area (not shown).

Since the first protection structure 50 covers the recessed region 12 , especially conforms to the topography of the recessed region, the film properties of the first protection structure 50 are affected, such as uneven film thickness or insufficient film quality. In one embodiment, the film layer of the first protective structure 50 located at the recessed region 12 is thinner than the region outside the recessed region 12 , or the film thickness is uneven due to the height difference of the recessed region 12 . In another embodiment, the plating rate of the first protective structure 50 located in the recessed region 12 is uneven due to the difference in height of the recessed region 12 , which makes the thin film in the recessed region 12 not dense enough to produce defects such as gaps or discontinuous films.

FIG. 4 is a partially enlarged SEM photo of the first extension portion 32 and the first semiconductor layer 201 in FIG. 3 .

Please refer to FIG. 3 and FIG. 4 together. When the first protection structure 50 covers the recessed region 12 , the first protection structure 50 generates a turning region 52 at a position corresponding to the recessed region 12 . In this embodiment, if the angle θ between the side surface of the first extension portion 32 of the first electrode 30 and the upper surface 201a of the first semiconductor layer 201 below it is too large (for example, greater than 30 degrees, or greater than 40 degrees, or greater than 60 degrees ), it will cause the turning range of the turning region 52 of the first protective structure 50 to be too large, and then make the film properties of the first protective structure 50 not good, for example, the poor coverage of the steps makes the film thickness uneven, which will cause defects or denseness. bad. In other embodiments, if the angle θ between the second extension portion 42 of the second electrode 40 and the upper surface 202a of the second semiconductor layer 202 below is too large (for example greater than 30 degrees, or greater than 40 degrees, or greater than 60 degrees ), will also lead to poor film properties of the first protective structure 50 .

Due to the height difference of the semiconductor light-emitting element 1 itself, there is a problem of poor coating step coverage, which in turn results in poor properties of the film, such as the first protective structure 50 , and affects the life of the semiconductor light-emitting element 1 . In this embodiment, the turning region 52 and/or the crack 54 of the first protection structure 50 is filled or repaired by covering part or all of the turning region 52 of the first protection structure 50 with the second protection structure 60 . In one embodiment, the second protection structure 60 directly contacts and covers at least the first upper surface 50 a of the first protection structure 50 located at the turning region 52 . In this embodiment, the second protection structure 60 is non-compliantly formed on the first protection structure 50 . The second protection structure 60 has a second upper surface 60 a, and the second upper surface 60 a is flatter or smoother than the first upper surface 52 at a position corresponding to the turning region 52 . In an embodiment, the material constituting the second protection structure 60 can be selected to have flowability. Due to the flowability of the material, it can be anisotropically deposited in the turning region 52 by, for example, spin coating. In one embodiment, after the second protective structure is formed by spin coating, it can be further cured by heating. According to the material of the second protection structure 60 , an appropriate heating temperature is selected. For example, when the second protective structure 60 includes organic materials, the heating temperature is not higher than 300°C, such as about 100°C to 300°C, or about 100°C to 200°C; when the second protective structure 60 includes inorganic materials, heating The temperature is about 300°C to 400°C. Therefore, the thickness of the second protective structure 60 at the position corresponding to the turning region 52 is not uniform, and the thickness of the film coverage increases as the turning range of the turning region 52 increases, and the thickness gradually decreases toward the direction away from the turning region 52 . For example, when the included angle θ increases, that is, when the inflection range of the recessed area 12 and the inflection area 52 increases, the thickness of the second protection structure 60 at the position corresponding to the inflection area 52 will also increase, and the thickness will increase in the direction away from the inflection area 52. Decrease gradually, the minimum can be reduced to 0.

In one embodiment, the second upper surface 60 a of the second protection structure 60 presents a substantially flat surface at a position corresponding to the turning region 52 . In some embodiments, the second upper surface 60 a of the second protection structure 60 presents a smooth and curved surface at a position corresponding to the turning region 52 . When the turning region 52 of the first protecting structure 50 is covered by the second protecting structure 60 , the second upper surface 60a of the second protecting structure 60 is formed at a position corresponding to the turning region 52 than the first upper surface 50a of the first protecting structure 50 A flatter or smoother shape can effectively alleviate the unevenness of the surface of the semiconductor light emitting element 1 caused by the turning region 52, and enable subsequent processes such as other film layers formed above the first protective structure 50 to obtain a better surface quality. In another embodiment, due to the flowability of the material of the second protection structure 60, the second protection structure 60 can be filled into the crack 54 to further prevent moisture from infiltrating, or electrodes formed in the subsequent process, for example, when the device operates At this time, the metal diffuses and intrudes into the semiconductor stack 20 along the crack 54 to reduce the reliability of the semiconductor light emitting element 1, or because the structural strength of the crack 54 is weak, the stress generated in the subsequent process will affect it and cause further structural damage.

FIG. 5 is a SEM photograph of a semiconductor light emitting device 1 according to another embodiment, showing partial structures of a part of the substrate 10 , the first semiconductor layer 201 , the first protection structure 50 and the second protection structure 60 .

As shown in Figure 5, in this embodiment, the main structure and materials of the semiconductor light emitting element 1 are similar to those of the foregoing embodiments, the difference is that the first protective structure 50 of the semiconductor light emitting element 1 of this embodiment includes a DBR structure 56 and A bottom layer 58 is located between the DBR structure 56 and the substrate 10 and/or the semiconductor layer (eg, the first semiconductor layer 201 ). The bottom layer 58 comprises a single layer or multiple sub-layers. In one embodiment, bottom layer 58 comprises a single layer, and DBR structure 56 is positioned above bottom layer 58 . In another embodiment, the bottom layer 58 includes a plurality of sublayers, and the DBR structure is formed between the plurality of bottom layers 58 . In a specific embodiment, the first protection structure 50 is formed by sequentially stacking the bottom layer 58 /DBR structure 56 /bottom layer 58 (not shown), such as SiO2/DBR/SiO2. In one embodiment, the formation methods of the bottom layer 58 and the DBR structure 56 include physical vapor deposition (PVD), electron beam evaporation (E-gun Evaporation), thermal evaporation (Thermal Evaporation), atomic layer deposition (Atomic Layer Deposition) , ALD) or plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). In one embodiment, the bottom layer 58 and the DBR structure are formed in different ways. The bottom layer 58 is formed by plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) or atomic layer deposition (Atomic Layer Deposition, ALD). The structures are formed by physical vapor deposition (PVD).

In one embodiment, the first protection structure 50 includes a turning region 52 , and at least one crack 54 is formed corresponding to the turning region 52 . When the first protective structure 50 covers the recessed region 12, if the recessed region 12 turns too large, or the depth of the recessed region 12 increases due to a large height difference, a crack will be formed in the turning region 52 of the first protective structure 50. 54, and extend into the first protection structure 50 from the first upper surface 50a. External moisture and metals during the process invade into the semiconductor stack 20 along the crack 54 to reduce the reliability of the semiconductor light emitting device 1 .

Please continue to refer to FIG. 5 , in some embodiments, a part of the second protection structure 60 is located in the crack 54 and fills it up, and another part of the second protection structure 60 covers the turning region 52 and the crack 54 thereof. As mentioned above, since the second upper surface 60a of the second protective structure 60 located on the turning region 52 has a flatter shape than the first upper surface 50a located in the turning region 52, the film layer covering it subsequently A certain level of flatness can be maintained to avoid defects. Furthermore, filling the crack 54 with the second protection structure 60 can effectively prevent metal and moisture from unintentionally diffusing into the semiconductor stack 20 through the crack 54 , thereby greatly improving the reliability of the device surface. In other embodiments, the second protection structure 60 only fills the crack 54 and does not cover the turning area 52, so that the second upper surface 60a of the second protection structure 60 will be located at the opening of the crack 54 (not shown in the figure). ).

FIG. 6 is a cross-sectional view of an embodiment of another semiconductor light emitting device 1' of the present disclosure, showing the partial structures of the substrate 10, the first semiconductor layer 201, the first protection structure 50 and the second protection structure 60.

Please refer to FIG. 6, the main structure of the semiconductor light emitting element 1' is similar to that of the semiconductor light emitting element 1, the difference is that the second protection structure 60 of the semiconductor light emitting element 1' is located between the substrate 10 and the first protection structure 50. In this embodiment, the semiconductor light emitting element 1' includes a substrate 10 on which a semiconductor stack 20 is formed, and the substrate 10 has an exposed region 100 not covered by the semiconductor stack 20. The substrate 10 includes a plurality of characteristic parts 11 located on the upper surface 10 a of the substrate 10 and protruding upwards. The height difference between the characteristic parts 11 of the substrate 10 forms a plurality of recessed regions 12 . In another embodiment, like the light-emitting device described in the foregoing embodiments, the recessed region 12 may be formed at the junction of the electrode (not shown) and the semiconductor stack 20 . The first protection structure 50 is formed on the substrate 10 and/or the semiconductor stack 20, including a first upper surface 50a and a first lower surface 50b opposite to the first upper surface 50a, and the first upper surface 50a is a substantially flat surface . The second protection structure 60 is formed between the first protection structure 50 and the substrate 10 and/or the semiconductor stack 20, including the second upper surface 60a overlapping with the first lower surface 50b of the first protection structure 50, and a second The lower surface 60b is opposite to the second upper surface 60a.

The second protection structure 60 covers the exposed region 100 of the upper surface 10 a of the substrate 10 . Due to the flowability of the material of the second protective structure 60, it can be anisotropically deposited in the recessed region 12, such as the recessed region 12 between the feature portions 11 or on the semiconductor stack 20, by, for example, spin coating. recessed area (not shown). In one embodiment, after the second protective structure is formed by spin coating, it can be further cured by heating. According to the material of the second protection structure 60 , an appropriate heating temperature is selected. For example, when the second protective structure 60 includes organic materials, the heating temperature is not higher than 300°C, such as about 100°C to 300°C, or for example 100°C to 200°C; when the second protective structure 60 includes inorganic materials, the heating temperature About 300°C to 400°C. By virtue of the characteristics of the second protection structure 60 , the level difference caused by the recessed region 12 can be alleviated or filled. In one embodiment, the second protection structure 60 completely covers the characteristic portion 11 of the substrate 10 such that the top 11 a of the characteristic portion 11 is located below the second upper surface 60 a of the second protection structure 60 . Taking the distance from the top 11a of the feature portion 11 to the upper surface 10a of the substrate 10 as D1, and taking the distance between the second upper surface 60a of the second protective structure 60 and the upper surface 10a of the substrate 10 as D2, then the second protective structure 60 The distance D2 between the second upper surface 60a and the upper surface 10a of the substrate 10 is greater than the distance D1 between the top 11a of the characteristic portion 11 and the upper surface 10a of the substrate 10 (ie, the height of the characteristic portion 11 ).

In another embodiment, the top 11a of the characteristic portion 11 is coplanar with the second upper surface 60a of the second protection structure 60 (not shown in the figure), that is, the second upper surface 60a of the second protection structure 60 and the exposed area 100 The distance D2 from the upper surface 10 a of the middle substrate 10 is equal to the distance D1 (not shown) from the top 11 a of the feature portion 11 to the upper surface 10 a of the exposed region 100 of the substrate 10 .

By forming the second protection structure 60 between the first protection structure 50 and the substrate 10, and contacting the first lower surface 50b of the first protection structure 50 with the second upper surface 60a of the second protection structure 60, that is, the second A protective structure 50 is directly formed on the second upper surface 60a of the second protective structure 60, thereby greatly improving the flatness of the first protective structure 50, and reducing or avoiding the formation of turning regions and/or defects such as cracks, and improving the first protective structure 50. Thin-film properties of the protective structure 50, and improve device reliability.

FIG. 7 is a schematic diagram of a light emitting device L1 according to an embodiment of the present disclosure. The semiconductor light-emitting elements 1, 1' in the foregoing embodiments are mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of flip chip. The first spacer 511 and the second spacer 512 are electrically insulated by an insulating portion 513 including insulating material. In flip-chip mounting, the side of the growth substrate opposite to the surface where the electrode pads are formed is set upward as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device L1, a reflective structure RF may be provided around the semiconductor light emitting elements 1, 1'.

FIG. 8 is a schematic diagram of a light emitting device L2 according to an embodiment of the present disclosure. The light emitting device L2 is a bulb lamp including a lampshade 602 , a reflector 604 , a light emitting module 610 , a lamp holder 612 , a heat sink 614 , a connection portion 616 and an electrical connection element 618 . The light-emitting module 610 includes a carrying portion 606, and a plurality of light-emitting units 608 are located on the carrying portion 606, wherein the plurality of light-emitting units 608 can be the semiconductor light-emitting elements 1, 1' or the light-emitting device L1 in the foregoing embodiments.

FIG. 9 is a schematic top view of a display M according to an embodiment of the present disclosure. As shown in Figure 9, the display M includes a display substrate 90, wherein the display substrate 90 includes a display area 901 and a non-display area 902, and a plurality of pixel units PX are arranged in the display area 901 of the display substrate 90, and each pixel The unit PX respectively includes a first sub-pixel PX_A, a second sub-pixel PX_B and a third sub-pixel PX_C. The data line driving circuit DL and the scanning line driving circuit SL are arranged in the non-display area 902 . The data line driving circuit DL is connected to data lines (not shown) of each pixel unit PX to transmit data signals to each pixel unit PX. The scan line driving circuit SL is connected to scan lines (not shown) of each pixel unit PX to transmit scan signals to each pixel unit PX. The pixel unit PX includes the semiconductor light emitting elements 1, 1' of any of the aforementioned embodiments. Each sub-pixel emits light of different colors. In some embodiments, the first sub-pixel PX_A, the second sub-pixel PX_B, and the third sub-pixel PX_C are, for example, red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. Dice pixels. Light-emitting elements that emit light of different wavelengths can be selected as sub-pixels, so that each sub-pixel presents different colors. In some embodiments, any sub-pixel includes the semiconductor light-emitting element 1, 1' of any of the foregoing embodiments, and the light emitted by the semiconductor light-emitting element 1, 1' passes through a wavelength conversion element (not shown), so that each sub-pixel Pixels appear in different colors. Through the combination of red, green and blue light emitted by each sub-pixel, the display M can emit full-color images. However, the number and arrangement of the sub-pixels of the pixel unit PX in this embodiment are not limited thereto, and there may be different implementations according to user requirements, such as color saturation, resolution, contrast, etc.

FIG. 10 is a cross-sectional view of a pixel unit PX in FIG. 9 . As mentioned above, the pixel unit PX includes the semiconductor light-emitting elements 1, 1' of any of the above-mentioned embodiments. In some embodiments, any sub-pixel includes a light-emitting element package PKG, and the light-emitting element package PKG is sealed with the semiconductor light-emitting element 1, 1' of any of the above-mentioned embodiments. The light emitting element package PKG is flip-chip bonded on the display substrate 90 . A circuit layer 91 and circuit bonding pads 6 a and 6 b are disposed on the display substrate 90 . The circuit layer 91 is electrically connected to the circuit bonding pads 6a, 6b, and the circuit layer 91 may include active electronic components, such as transistors. The electrodes 6c and 6d of the light-emitting element package PKG are respectively bonded to the circuit bonding pads 6a and 6b by soldering, and electrically connected to the display driving circuit (ie, the data line driving circuit DL and the scanning line driving circuit SL) through the circuit layer 91 . sexual connection. In this way, the semiconductor light emitting elements 1, 1' in the pixel unit PX can be controlled by the data line driving circuit DL, the scanning line driving circuit SL and the circuit layer 91. In some embodiments (not shown in the figure), the pixel unit PX includes a light-emitting element package PKG, and a plurality of semiconductor light-emitting elements 1, 1' are simultaneously sealed in a single light-emitting element package PKG, and each semiconductor light-emitting element 1, 1' Constitute a sub-pixel. In some embodiments (not shown in the figure), any sub-pixel includes the semiconductor light emitting element 1, 1' according to any embodiment of the present disclosure, and the first electrode 30 of the semiconductor light emitting element 1, 1' is flip-chip and the second electrode 40 , or the third electrode 70 and the fourth electrode 80 are respectively bonded to the circuit bonding pads 6 a and 6 b on the display substrate 90 .

FIG. 11 is a cross-sectional view of a display backlight unit BL according to an embodiment of the present disclosure. The display backlight unit BL includes a bottom case 700 in which a light source module 71 is accommodated, and an optical film 72 is disposed above the light source module 71 . The optical film 72 is, for example, a light diffuser. In some embodiments, the backlight unit BL is a direct type backlight unit. The light source module 71 includes a circuit carrier 710 and a plurality of light sources 711 arranged on the upper surface thereof. In some embodiments, the light source 711 includes the semiconductor light emitting elements 1, 1' of any of the foregoing embodiments, and is mounted on the upper surface of the circuit carrier 710 in a flip-chip manner. In some embodiments, the light source 711 includes a light-emitting element package PKG, in which the semiconductor light-emitting element 1, 1' of any of the above-mentioned embodiments is encapsulated, and mounted on the upper surface of the circuit carrier 710 in a flip-chip manner. In some embodiments, a single light emitting device package PKG encapsulates a plurality of semiconductor light emitting devices 1, 1'.

However, the above-mentioned embodiments are only illustrative to illustrate the principles and functions of the present application, and are not intended to limit the present application. Anyone with ordinary knowledge in the technical field to which this application belongs can modify and change the above-mentioned embodiments without violating the technical principle and spirit of this application. All equal changes and modifications made in accordance with the shape, structure, characteristics and spirit described in the patent scope of this application shall be included in the scope of patent application of this application.

1, 1': semiconductor light emitting element 10: Substrate 100: Exposure area 10a: Upper surface 11:Characteristic part 11a: top 12: Depressed area 20: Semiconductor stack 20b: side surface 201: the first semiconductor layer 201a: upper surface 202: the second semiconductor layer 202a: upper surface 203: active layer 30: the first electrode 31: first contact part 32: Second extension 40: Second electrode 41: Second contact part 42: Second extension 50: The first protective structure 50a: first upper surface 50b: first lower surface 52: Turning area 54: crack 60: Second protection structure 60a: second upper surface 60b: second lower surface 70: The third electrode 80: The fourth electrode D1, D2: distance θ: included angle L1: light emitting device 51: Package substrate 511: The first gasket 512: second gasket 53: Insulation part RF: reflective structure L2: light emitting device 602: lampshade 604: Mirror 606: bearing part 608: Lighting unit 610: Lighting module 612: lamp holder 614: heat sink 616: connection part 618: Electrical connection components M: Monitor 90: Display substrate 901: display area 902: non-display area PX: pixel unit PX_A: the first sub-pixel PX_B: Second sub-pixel PX_C: The third sub-pixel PKG: Light emitting element package 6a, 6b: Circuit Bonding Pads 6c, 6d: electrodes BL: backlight unit 700: Bottom shell 71:Light source module 710: circuit board 711: light source 72:Optical film

FIG. 1 is a top view of an embodiment of a semiconductor light emitting device of the present disclosure.

Fig. 2 is a cross-sectional view of the semiconductor light-emitting element along the line segment A-A' in Fig. 1.

FIG. 3 is a scanning electron microscope (SEM) photo of a partial section of an embodiment of a semiconductor light-emitting device of the present disclosure.

Fig. 4 is a partially enlarged SEM photo of the electrode and the first semiconductor layer in Fig. 3, and the recessed region formed between them.

FIG. 5 is a cross-sectional view of another embodiment of a semiconductor light emitting device of the present disclosure.

FIG. 6 is a cross-sectional view of an embodiment of another semiconductor light emitting device of the present disclosure.

FIG. 7 is a schematic diagram of an embodiment of a light emitting device L1 of the present disclosure.

FIG. 8 is a schematic top view of an embodiment of a light emitting device L2 of the present disclosure.

FIG. 9 is a schematic top view of an embodiment of a display M of the present disclosure.

FIG. 10 is a cross-sectional view of a pixel unit PX in FIG. 9 .

FIG. 11 is a cross-sectional view of an embodiment of a display backlight unit BL of the present disclosure.

none

10: Substrate

11:Characteristic part

12: Depressed area

201: the first semiconductor layer

201a: upper surface

32: The first extension

50: The first protective structure

50a: first upper surface

52: Turning area

60: Second protection structure

60a: second upper surface

Claims (10)

A semiconductor light-emitting element, comprising: a substrate; a semiconductor stack formed on the substrate; a recessed area; a first protection structure formed on the semiconductor stack, and including a first upper surface and a turning area formed corresponding to the recessed area; and a second protective structure covering the turning area and including a second upper surface; wherein the first protective structure includes a crack extending from the first upper surface into the first protective structure wherein, the second protection structure is located in the crack, wherein the part of the second upper surface corresponding to the turning region is flatter or smoother than the part of the first upper surface corresponding to the concave region. A semiconductor light-emitting element, comprising: a substrate, including an upper surface, and a plurality of characteristic parts located on the upper surface, wherein the characteristic parts each have a height; a semiconductor stack formed on the substrate; a recessed area , located between the feature portions; a first protection structure, formed on the semiconductor stack and the substrate, including a first upper surface corresponding to the recessed region; and a second protection structure, formed on the first protection structure Between the structure and the substrate, and covering the recessed area and the features, wherein, the second protection structure includes a second upper surface corresponding to the recessed area; wherein, the second upper surface of the second protection structure and the There is a distance between the upper surfaces of the substrate greater than or equal to the height of one of the features, and the first upper surface of the first protection structure and/or the second upper surface of the second protection structure is a roughly flat surface. The semiconductor light emitting device according to claim 1 or 2, wherein the semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer. The semiconductor light emitting device as claimed in claim 1, wherein the substrate includes an upper surface, and a plurality of feature portions are located on the upper surface, wherein the semiconductor light emitting device further includes an electrode located on the semiconductor stack. The semiconductor light emitting device as claimed in claim 4, wherein the recessed region is located between the semiconductor stack and the electrode, and/or between the characteristic parts. The semiconductor light emitting device as described in claim 2, further comprising: an electrode located on the semiconductor stack; and another recessed area located between the semiconductor stack and the electrode, wherein the second protection structure covers the other In a recessed area, the second protection structure includes another second upper surface corresponding to the other recessed area, and the other second upper surface is a substantially flat surface. The semiconductor light emitting device according to claim 1, wherein the crack is formed corresponding to the recessed region. The semiconductor light emitting device according to claim 1 or 2, wherein the first protection structure comprises a DBR structure. The semiconductor light emitting device as claimed in claim 8, wherein the first protective structure further includes a bottom layer, and the DBR structure is located above the bottom layer. The semiconductor light emitting device according to claim 1 or 2, wherein the second protection structure comprises a flowable material.

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