TWI868197B - Light-emitting device and manufacturing method thereof - Google Patents

Abstract

A light-emitting device is disclosed. The light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region, a second semiconductor layer and an exposed region, wherein the exposed region includes a sidewall of the semiconductor stack and an upper surface of the first semiconductor layer; a first protective layer covering the exposed region and a portion of the second semiconductor layer; a dielectric stack located on the semiconductor stack and including a plurality of dielectric pairs composed of dielectric layers with different refractive indexes alternately stacked and one or a plurality of first openings; and a metal structure located on the dielectric stack and filling in the first opening to electrically connect the second semiconductor layer; wherein the first protective layer includes a first part on the upper surface of the first semiconductor layer and has a first thickness and a second part on the second semiconductor layer and has a second thickness, and the first thickness is smaller than the second thickness.

Description

Light-emitting element and method for manufacturing the same

This application relates to a light-emitting element, and more specifically, to a light-emitting element with improved brightness.

Light-emitting diodes (LEDs) in solid-state light-emitting devices have low power consumption, low heat generation, long life, small size, fast response speed and good photoelectric properties, such as stable luminous wavelength, so they have been widely used in household appliances, indicator lights and optoelectronic products.

A conventional LED includes a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer formed on the substrate, as well as p- and n-electrodes formed on the p-type and n-type semiconductor layers, respectively. When the LED is energized through the electrodes and at a forward bias of a specific value, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer combine in the active layer to emit light. However, as LEDs are applied to various optoelectronic products, the brightness specifications of LEDs are also improved. How to improve their brightness is one of the research and development goals of researchers in this technical field.

This application discloses a light-emitting element, comprising a first semiconductor layer, an active layer, a second semiconductor layer and an exposed area, wherein the exposed area comprises the sidewall of the semiconductor stack and the upper surface of the first semiconductor layer; a first protective layer, covering the exposed area and part of the semiconductor stack; a dielectric material stack, located on the semiconductor stack, comprising a plurality of dielectric material pairs alternately stacked by dielectric materials with different refractive indices and one or more first openings; and a metal structure, located on the dielectric material stack, filling the first opening and electrically connected to the second semiconductor layer; wherein the first protective layer comprises a first portion located on the upper surface of the first semiconductor layer in the exposed area and having a first thickness, and a second portion located on the second semiconductor layer and having a second thickness, wherein the first thickness is less than the second thickness.

The present application discloses a light-emitting element, comprising a semiconductor stack, comprising a first semiconductor layer, an active layer, a second semiconductor layer and an exposed area, wherein the exposed area comprises an upper surface of the first semiconductor layer and a side wall of the semiconductor stack; a lower protective layer, covering the exposed area; a dielectric material stack, covering the semiconductor stack, comprising a plurality of dielectric material pairs alternately stacked by dielectric materials with different refractive indices and one or more first openings; a metal structure, located between the dielectric On the material stack, a first opening is filled and electrically connected to the second semiconductor layer; the upper protective layer covers the semiconductor stack and the metal structure, and includes a plurality of second openings that expose the exposed area and the metal structure respectively; and the first electrode is located on the upper protective layer; wherein the dielectric material stack is located between the upper protective layer and the lower protective layer, the second opening of the upper protective layer includes a second inclined side wall, and the first electrode conformally covers the second inclined side wall and contacts the exposed area.

1, 2: Light-emitting element

3, 4: Light-emitting device

10: Substrate

10a: Upper surface of substrate

12: Semiconductor stacking

121: First semiconductor layer

121a: Upper surface of the first semiconductor layer

122: Second semiconductor layer

123: Active layer

18: Transparent conductive layer

180: Transparent conductive layer opening

26: Etch stop layer

28: Exposed area

20: First electrode

30: Second electrode

36: Second reflection structure

360: Second reflection structure opening

27: Laser

23a: Lower protective layer

23b: Upper protective layer

23: First protective layer

230, 231: Opening of the first protective layer

232: Upper protective layer opening

25: Second protective layer

251, 252: Second protective layer opening

50: First reflection structure

50a, 50b, 50c, 50d: first sublayer, second sublayer, third sublayer, fourth sublayer

501, 502: first reflection structure opening

51: Carrier board

511, 512: Gasket

53: Insulation Department

54: Reflection structure

602: Lampshade

604: Reflector

606: Carrying unit

608: Light-emitting unit

610: Light-emitting module

612: Lamp holder

614: Heat sink

616:Connection part

618:Electrical connection element

t1, t1’, T, T’: thickness

MS: High platform

ISO: Aisle area

[Figure 1A] shows a top view of the light-emitting elements 1 and 2 of an embodiment of the present application.

[Figure 1B] shows a cross-sectional view of the light-emitting element 1 of an embodiment of the present application.

[Figure 1C] shows a partial cross-sectional view of the light-emitting element 1 of the first embodiment of the present application.

[Figure 1D] shows a cross-sectional view of the light-emitting element 2 of the first embodiment of the present application.

[Figure 1E] shows a partial cross-sectional view of the light-emitting element 2 of the first embodiment of the present application.

[Figures 2A to 2H] show views of the light-emitting element 1 at various stages of the manufacturing method of the first embodiment of the present application.

[Figures 3A to 3F] show cross-sectional views at various stages of the manufacturing method of the light-emitting element 1 of the first embodiment of the present application.

[Figures 4A to 4C] show cross-sectional views of some stages in the manufacturing method of the light-emitting element 1 of the first embodiment of the present application.

[Figures 5A and 5B] show cross-sectional views of some stages in the manufacturing method of the light-emitting element 1 of the first embodiment of the present application. [Figures 6A and 6B] show a partial enlarged cross-sectional view of the first reflective structure in the light-emitting element 1 of the first embodiment of the present application.

[Figures 7A to 7I] show views of the various stages in the manufacturing method of the light-emitting element 2 of the first embodiment of the present application.

[Figures 8A to 8G] show cross-sectional views at various stages of the manufacturing method of the light-emitting element 2 in the first embodiment of the present application.

[Figures 9A to 9C] show cross-sectional views of some stages in the manufacturing method of the light-emitting element 2 of the first embodiment of the present application.

[Figure 10A and Figure 10B] show cross-sectional views of some stages in the manufacturing method of the light-emitting element 2 of the first embodiment of the present application.

[Figure 11] shows a schematic diagram of the light-emitting device 3 of the first embodiment of the present application.

[Figure 12] shows a schematic diagram of the light-emitting element 4 of the first embodiment of the present application.

Hereinafter, the exemplary embodiments of the present invention will be described in detail with reference to the diagrams, so that the technical personnel in the field of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some identical symbols, which represent components with the same or similar structures, functions, and principles, and can be inferred by those with general knowledge in the industry based on the teachings of this specification. For the sake of brevity in the specification, components with the same symbols will not be repeated.

FIG1A shows a top view of a light-emitting element 1 in an embodiment of the present application. FIG2A to FIG2H show top views of various stages in a method for manufacturing a light-emitting element 1 in an embodiment of the present application; and FIG3A to FIG3F show cross-sectional views of various stages in the method for manufacturing the light-emitting element 1. The method for manufacturing the light-emitting element 1 is described in detail as follows. First, referring to FIG2A , a semiconductor stack 12 is formed above a substrate 10, and a lower protective layer 23a is formed on the semiconductor stack 12. Next, referring to FIG2B , a transparent conductive layer 18 is formed on the semiconductor stack 12. FIG3A shows a cross-sectional view along the line segment A-A’ after the steps of FIG2A and FIG2B are completed. The substrate 10 can be a wafer, and together with the semiconductor stack 12 formed thereon, it forms a semiconductor wafer. The semiconductor wafer is separated into a plurality of light-emitting elements 1 after a subsequent cutting process. The following embodiment diagrams and descriptions will be represented by a single light-emitting element 1.

The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for growing gallium indium phosphide (AlGaInP), or a sapphire (Al ₂ O ₃ ) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing gallium indium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate 10 includes an upper surface 10a. The substrate 10 may be a patterned substrate, that is, the substrate 10 has a patterned structure (not shown) on its upper surface 10a. In one embodiment, light emitted from the semiconductor stack 12 may be refracted by the patterned structure of the substrate 10, thereby increasing the brightness of the light-emitting element. In addition, the patterned structure reduces or suppresses the misalignment between the substrate 10 and the semiconductor stack 12 due to lattice mismatch, thereby improving the epitaxial quality of the semiconductor stack 12.

In one embodiment of the present application, the method for forming the semiconductor stack 12 on the substrate 10 includes metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydrogen vapor phase epitaxy (HVPE) or ion plating, such as sputtering or evaporation.

A buffer structure (not shown), a first semiconductor layer 121, an active layer 123, and a second semiconductor layer 122 are sequentially formed on a substrate 10. The buffer structure, the first semiconductor layer 121, the active layer 123, and the second semiconductor layer 122 constitute a semiconductor stack 12. The buffer structure can reduce the above-mentioned lattice mismatch and suppress dislocation, thereby improving the epitaxial quality. The material of the buffer layer includes GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes a plurality of sub-layers (not shown). The sub-layers include the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the growth method of the first sublayer is sputtering, and the growth method of the second sublayer is MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The growth method of the third sublayer is MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sublayers include the same material, such as AlN, or different materials, such as AN, GaN, AlGaN. In one embodiment of the present application, the first semiconductor layer 121 and the second semiconductor layer 122, such as a cladding layer or a confinement layer, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 121 is an n-type semiconductor, and the second semiconductor layer 122 is a p-type semiconductor. The active layer 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. The electrons and holes are combined in the active layer 123 under the current drive, and the electrical energy is converted into light energy to emit light. The wavelength of light emitted by the light-emitting element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 12.

x，y

1；x+y

1。根據活性層的材料，當半導體疊層12的材料是AlInGaP系列時，可以發出波長介於610nm和650nm之間的紅光或波長介於550nm和570nm之間的黃光。當半導體疊層12的材料是InGaN系列時，可以發出波長介於400nm和490nm之間的藍光或深藍光或波長介於490nm和550nm之間的綠光。當半導體疊層12的材料是AlGaN系列時，可以 發出波長介於400nm和250nm之間的UV光。活性層123可以是單異質結構(single heterostructure；SH)、雙異質結構(double heterostructure；DH)、雙面雙異質結構(double-side double heterostructure；DDH)、多重量子井(multi-quantum well；MQW)。活性層123的材料可以是i型、p型或n型半導體。 The material of the _{semiconductor} stack 12 includes a III-V semiconductor material of _{AlxInyGa (1-xy) N} or _{AlxInyGa (1-xy)} P, wherein 0

x,y

1; x+y

1. Depending on the material of the active layer, when the material of the semiconductor stack 12 is AlInGaP series, red light with a wavelength between 610nm and 650nm or yellow light with a wavelength between 550nm and 570nm can be emitted. When the material of the semiconductor stack 12 is InGaN series, blue light or deep blue light with a wavelength between 400nm and 490nm or green light with a wavelength between 490nm and 550nm can be emitted. When the material of the semiconductor stack 12 is AlGaN series, UV light with a wavelength between 400nm and 250nm can be emitted. The active layer 123 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active layer 123 may be an i-type, p-type, or n-type semiconductor.

Next, a step of forming an exposed region 28 is performed. Referring to FIG. 3A , in this step, a portion of the active layer 123 and the first semiconductor layer 121 are removed downward from the upper surface of the second semiconductor layer 122 to expose the upper surface 121a of the first semiconductor layer 121, thereby forming an exposed region 28. Referring to FIG. 2A , relative to the exposed region 28, the semiconductor stack 12 in other regions forms a mesa MS. In this embodiment, the exposed region 28 includes a surrounding region surrounding the semiconductor stack 12 and an inner region distributed within the semiconductor stack 12. Each exposed area 28 includes a side wall formed by the side surface of the semiconductor stack 12 and a bottom formed by the upper surface 121a of the first semiconductor layer 121. Then, in one embodiment, the first semiconductor layer 121 located around the semiconductor stack 12 and outside the surrounding area is further removed to expose the upper surface 10a of the substrate to form an aisle area ISO. The aisle area ISO separates and defines a plurality of light-emitting units 1 and serves as the location of the prepared dividing line (not shown) in the subsequent cutting process. In one embodiment, as shown in FIG. 2A, the contour of the platform MS is wavy, sawtooth, square wave or other non-straight line pattern. The light extraction efficiency of the light-emitting element 1 can be improved by the pattern design of the contour of the platform MS.

Next, referring to FIG. 2A and FIG. 3A , a lower protective layer 23a is formed on the exposed area 28. The lower protective layer 23a covers the bottom, sidewalls and a portion of the second semiconductor layer 122 of the exposed area 28. The lower protective layer 23a is transparent to the light emitted by the semiconductor stack 12, and its material is a non-conductive material, including an organic material or an inorganic material. The organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide or fluorocarbon polymer. Inorganic materials include, for example, silicone, glass, or dielectric materials, and dielectric materials include, for example _, silicon oxide ( _SiNx ), silicon nitride ( _SiNx ), silicon _oxynitride ( _SiOxNy ), niobium oxide ( _Nb2O5 ), niobium oxide ( _HfO2 ), titanium _oxide ( _TiOx ), magnesium fluoride ( _MgF2 ), aluminum oxide ( _Al2O3 ), etc. The lower protective layer 23a is formed by atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. In another embodiment, around the semiconductor stack 12, the lower protection layer 23a further covers the sidewall of the first semiconductor layer 121.

In order to clearly show the top views of each stage in the manufacturing method of the light-emitting element 1, Figures 2B to 2H only show the platform MS, the layer formed in the current step, or even the layer formed in the step before the current step.

After the lower protective layer 23a is formed, a step of forming a transparent conductive layer 18 is performed with reference to FIG. 2B and FIG. 3A. FIG. 2B only shows the high platform MS and the transparent conductive layer 18. The transparent conductive layer 18 covers the upper surface of the second semiconductor layer 122 and is in electrical contact with the second semiconductor layer 122, including an opening 180 formed corresponding to the exposed area 28. The transparent conductive layer 18 can be a metal or a transparent conductive material, wherein the metal can be selected from a thin metal layer with light transmittance, and the transparent conductive material is transparent to the light emitted by the active layer 123, and includes materials such as graphene, indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc oxide (ZnO) or indium zinc oxide (IZO). In one embodiment, the transparent conductive layer 18 covers part of the lower protective layer 23a. In another embodiment, the transparent conductive layer 18 does not cover the lower protective layer 23a. In another embodiment, the transparent conductive layer 18 can be formed first, and then the lower protective layer 23a is formed.

Next, referring to FIG. 2C, FIG. 3B and FIG. 3C, a step of forming a first reflective structure 50 is performed. FIG. 3B shows a cross-sectional view along the line segment A-A' after the steps of FIG. 2A to FIG. 2C are completed. FIG. 2C only shows the platform MS and the first reflective structure 50. The first reflective structure 50 is first formed on the upper surface of the second semiconductor layer 122, and then the openings 501 and 502 separated from each other are formed in the first reflective structure 50 by processes such as developing and etching. The position of the opening 501 corresponds to the exposed area 28 and the transparent conductive layer opening 180, and the opening 502 is distributed on the second semiconductor layer 122 and exposes the transparent conductive layer 18 thereunder. [0018] In one embodiment, FIG. 6A shows a partially enlarged cross-sectional view of the first reflective structure 50, and the first reflective structure 50 is formed by a pair or a plurality of pairs of materials with different refractive indices being alternately stacked. In this embodiment, as shown in FIG. 5A, the first reflective structure 50 includes a set of material stacks, such as dielectric materials, which are composed of a first sublayer 50a and a second sublayer 50b alternately stacked. A first sublayer 50a and a second sublayer 50b form a dielectric material pair. The first sublayer 50a has a higher refractive index than the second sublayer 50b. In one embodiment, the first sublayer 50a has a smaller thickness than the second sublayer 50b. The dielectric material includes, for example, silicon oxide, silicon nitride, silicon oxynitride, niobium oxide, niobium oxide, titanium oxide, magnesium fluoride, aluminum oxide, etc. By selecting materials with different refractive indices and stacking them in a thickness design to form a material stack to form a first reflective structure 50, a reflective function is provided for light within a specific wavelength range, such as a distributed Bragg reflector (DBR).

In one embodiment, the first reflective structure 50 may further include other layers besides the first sublayer 50a and the second sublayer 50b. For example, the first reflective structure 50 further includes a bottom layer (not shown) located between the first sublayer 50a (and/or the second sublayer 50b) and the semiconductor stack 12. In other words, the bottom layer is first formed on the semiconductor stack 12, and then the first sublayer 50a and the second sublayer 50b are formed. The bottom layer is a non-conductive material, including an organic material or an inorganic material, wherein the inorganic material may be a dielectric material. The thickness of the bottom layer is greater than the thickness of the first sublayer 50a and the second sublayer 50b. In one embodiment, the bottom layer is formed by a different method from the first sublayer 50a and the second sublayer 50b. For example, the bottom layer is formed by chemical vapor deposition (CVD), preferably by plasma enhanced chemical vapor deposition (PECVD). The first sublayer 50a and the second sublayer 50b are formed by sputtering.

In another embodiment, as shown in FIG. 6B , the first reflective structure 50 includes a plurality of material stacks, the first material stack is composed of a first sublayer 50a and a second sublayer 50b alternately stacked, and the second material stack is composed of a third sublayer 50c and a fourth sublayer 50d alternately stacked. In one embodiment, the second material stack is, for example, a dielectric material, and a dielectric material pair is composed of a third sublayer 50c and a fourth sublayer 50d. The third sublayer 50c has a higher refractive index than the fourth sublayer 50d. In one embodiment, the third sublayer 50c has a smaller thickness than the fourth sublayer 50d. The third sublayer 50c has a different thickness from the first sublayer 50a, and the third sublayer 50c and the first sublayer 50a can be made of the same material or different materials. The fourth sublayer 50d has a different thickness from the second sublayer 50b, and the fourth sublayer 50d and the second sublayer 50b can be made of the same material or different materials.

In another embodiment, the first reflective structure 50 may further include an upper layer (not shown) located on the first sublayer 50a (and/or the second sublayer 50b) on the other side of the second semiconductor layer 122. In other words, the first sublayer 50a and the second sublayer 50b are first formed on the semiconductor stack 12, and then the upper layer is formed. The upper layer is a non-conductive material, including an organic material or an inorganic material, wherein the inorganic material can be a dielectric material. The thickness of the upper layer is greater than the thickness of the first sublayer 50a and the second sublayer 50b. In one embodiment, the upper layer is formed by a different method from the first sublayer 50a and the second sublayer 50b. For example, the upper layer is formed by chemical vapor deposition, preferably by plasma enhanced chemical vapor deposition (PECVD). The first sublayer 50a and the second sublayer 50b are formed by sputtering.

In another embodiment, the first reflective structure 50 includes a plurality of material stacks and a bottom layer and/or an upper layer. In another embodiment, before forming the first reflective structure 50, a dense layer (not shown) is formed on one surface of the substrate 10 and the semiconductor stack 20 by atomic deposition to directly cover the surface of the semiconductor stack 12. In one embodiment, the dense layer can more densely cover and fill the surface defects of the semiconductor stack 12 to prevent the intrusion of moisture. The material of the dense layer includes inorganic materials, such as silicon oxide, aluminum oxide, tantalum oxide, tantalum oxide, zirconium oxide, yttrium oxide, tantalum oxide, tantalum oxide, silicon nitride, aluminum nitride or silicon oxynitride. In this embodiment, the interface between the dense layer and the semiconductor stack 12 includes metal elements and oxygen, wherein the metal elements include aluminum, tantalum, tantalum, zirconium, yttrium, tantalum or tantalum. The dense layer includes a thickness between 50Å and 2000Å, preferably between 100Å and 1500Å.

In one embodiment, the thickness of the first reflective structure 50 is between 0.3 μm and 6 μm. In one embodiment, the inner angle between the sidewalls of the first reflective structure 50, such as the sidewalls of the openings 501 and 502, and the transparent conductive layer 18 is between 5 degrees and 80 degrees.

In one embodiment, the first reflective structure 50 does not have an opening 502 between adjacent openings 501.

In another embodiment, the first reflective structure 50 does not have a plurality of openings 501, 502 as shown in FIG. 2C, but is distributed on the second semiconductor layer 122 in the form of a plurality of separate islands (not shown).

Next, referring to FIG. 2D and FIG. 3C , a second reflective structure 36 formation step is performed. FIG. 3C shows a cross-sectional view along the line segment A-A’ after the steps of FIG. 2A to FIG. 2D are completed. FIG. 2D only shows the high platform MS and the second reflective structure 36. The second reflective structure 36 is formed on the transparent conductive layer 18 and the first reflective structure 50 correspondingly, and is electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 through the opening 502 of the first reflective structure 50, and includes a plurality of openings 360 corresponding to the opening 501 of the first reflective structure 50, formed on the exposed area 28. The second reflective structure 36 includes a metal structure, which may include a single layer of metal or a stack formed by a plurality of layers of metal. In one embodiment, the second reflective structure 36 includes a barrier layer (not shown) and a reflective layer (not shown). The barrier layer is formed and covers the reflective layer. The barrier layer can prevent the migration, diffusion or oxidation of the metal elements of the reflective layer. The material of the reflective layer includes a metal material with high reflectivity for the light emitted by the semiconductor stack 12, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru) or alloys or stacks of the above materials. The material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn) or alloys or stacks of the above materials. In one embodiment, when the barrier layer is a metal stack, the barrier layer is formed by alternately stacking two or more metal layers, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc. In another embodiment (not shown), the first reflective structure 50 includes a plurality of islands distributed on the second semiconductor layer 122, and the second reflective structure 36 is electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 through the gaps between the islands.

Next, referring to FIG. 2E and FIG. 3D, a step of forming an upper protective layer 23b is performed. FIG. 3D shows a cross-sectional view along the line segment A-A’ after the steps of FIG. 2A to FIG. 2E are completed. FIG. 2E only shows the platform MS, the second reflective structure 36 and the upper protective layer 23b. The upper protective layer 23b is formed on the second reflective structure 36, covering a portion of the upper surface of the second reflective structure 36, and covering the lower protective layer 23a. In the exposed area 28 and near the exposed area 28, the upper protective layer 23b overlaps and connects with the lower protective layer 23a.

The upper protective layer 23b includes openings 230, 231, and 232. Referring to FIG. 2E, a plurality of openings 230 are disposed at intervals around the upper protective layer 23b to expose the bottom of the exposed area 28 around the semiconductor stack 12, that is, the upper surface 121a of the first semiconductor layer. Its function and corresponding cross-sectional structure will be described in detail below. A plurality of openings 231 are disposed in the exposed area 28 inside the semiconductor stack 12 to expose the upper surface 121a of the first semiconductor layer at the bottom of the exposed area 28. The opening 232 exposes the second reflective structure 36. In this embodiment, only a single opening 232 is shown, but the present invention is not limited thereto. The upper protective layer 23b may include a plurality of openings 232 to expose the second reflective structure 36 respectively. In one embodiment, an insulating material is first formed to cover the second reflective structure 36 and the exposed area 28, and then openings 230, 231 and 232 are formed by developing etching or the like to form the upper protective layer 23b. When the openings 230 and 231 are formed, the lower protective layer 23a directly below the openings 230 and 231 is also removed. The upper protective layer 23b and the lower protective layer 23a constitute a first protective layer 23, and the upper protective layer 23b and the lower protective layer 23a can be the same material or different materials. That is, the first protective layer 23 has a plurality of openings 230 disposed at intervals around it to expose the upper surface 121a of the first semiconductor layer, and a plurality of openings 231 disposed in the exposed area 28 inside the semiconductor stack 12 to expose the upper surface 121a of the first semiconductor layer. The upper protective layer 23b is transparent to the light emitted by the semiconductor stack 12, and its material is a non-conductive material, including an organic material or an inorganic material. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyimide, polyetherimide or fluorocarbon polymer. Inorganic materials include silicone, glass or dielectric materials. Dielectric materials include, for example, silicon _oxide ( _SiNx ), silicon nitride ( _SiNx ), _silicon oxynitride ( _SiOxNy ), niobium oxide ( _Nb2O5 ), _{niobium oxide} (HfO2), titanium oxide ( _TiOx ), magnesium fluoride ( _MgF2 ), aluminum oxide ( _Al2O3 ), etc. The lower protective layer 23a is formed by atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. Since the first protective layer 23 covers the sidewalls of the exposed area 28, that is, the sidewalls of the semiconductor stack 12, the semiconductor stack 12 can be protected to avoid possible damage to the semiconductor stack 12 in subsequent processes. In another embodiment, around the semiconductor stack 12, the upper protective layer 23b further covers the sidewalls of the first semiconductor layer 121.

Next, referring to FIG. 2F and FIG. 3E , an electrode forming step is performed. FIG. 3E shows a cross-sectional view along the line segment A-A’ after the steps of FIG. 2A to FIG. 2F are completed. FIG. 2F only shows the high platform MS, the upper protective layer 23b and the electrode. The electrode includes a first electrode 20 and a second electrode 30, wherein the first electrode 20 covers the upper protective layer 23b, and contacts the first semiconductor layer 121 at the bottom of the exposed area 28 through the openings 230 and 231 of the upper protective layer 23b and forms an electrical connection therewith. The second electrode 30 is separated from the first electrode 20 and formed in the opening 232 of the upper protective layer 23b, contacts the second reflective structure 36 and is electrically connected to the second semiconductor layer 122. The electrode includes a metal material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn) or an alloy or a stack of the above materials.

Next, referring to FIG2G, a second protective layer forming step is performed. Referring to FIG2H, a pad forming step is performed. FIG3F shows a cross-sectional view along the line segment A-A' after the steps of FIG2A to FIG2G are completed. FIG2G only shows the high platform MS, the first electrode 20, the second electrode 30 and the second protective layer 25.

The second protective layer 25 is formed on the first electrode 20, the second electrode 30 and the exposed area 28, and extends to cover the sidewalls and the walkway area ISO of the first semiconductor layer 121. The second protective layer 25 includes openings 251 and 252, wherein the opening 251 exposes the first electrode 20, and the opening 252 exposes the second electrode 30. In this embodiment, only a single opening 251 and a single opening 252 are shown, but the present invention is not limited thereto, and the upper protective layer 23b may include a plurality of openings 251 and openings 252. The material of the second protective layer 25 includes a non-conductive material, including an organic material or an inorganic material. The organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide or fluorocarbon polymer. Inorganic materials include silicone, glass or dielectric materials, such as silicon oxide ( _SiNx ), _silicon nitride ( _SiNx ), silicon oxynitride ( _SiOxNy ), niobium oxide (Nb2O5), niobium oxide ( _HfO2 ), _titanium oxide ( _TiOx ), magnesium fluoride ( _MgF2 ), aluminum oxide ( _Al2O3 ), etc. In one embodiment, the second protective layer 25 is formed by stacking one or more pairs of materials _with different refractive indices alternately. By selecting materials with different refractive indices _and designing their thicknesses, the second protective layer 25 forms a reflective structure, which provides a reflective function for light in a specific wavelength range, such as a distributed Bragg reflector. In one embodiment, similar to the first reflective structure 50, the second protective layer 25 includes one or more sets of material stacks, and a bottom layer and/or an upper layer. In one embodiment, the second protective layer 25 with a distributed Bragg reflector covers the side wall of the semiconductor stack 12 located in the aisle area ISO, which is beneficial to the light extraction near the aisle area ISO and improves the brightness of the light-emitting element 1. In one embodiment, the second protective layer 25 with a distributed Bragg reflector includes m pairs of dielectric material pairs, and the first reflective structure 50 includes n pairs of dielectric material pairs, where m is greater than n. In one embodiment, the thickness of the second protective layer is greater than the thickness of the first reflective structure 50.

In one embodiment, the thickness of the second protective layer 25 may be 1 μm to 6 μm. If the thickness of the second protective layer 25 is less than 1 μm, the thinner thickness may weaken the insulation and moisture resistance of the second protective layer 25, thereby reducing the reliability of the light-emitting element 1. In one embodiment, the thickness of the second protective layer 25 is greater than the thickness of the upper protective layer 23b.

Next, referring to FIG. 2H , a first pad 80a and a second pad 80b are formed in the openings 251 and 252 , respectively. FIG. 2H only shows the platform MS, the first electrode 20, the second electrode 30, the second protective layer 25 and the pads. The first pad 80a is connected to the first electrode 20 and is electrically connected to the first semiconductor layer 121. The second pad 80b is connected to the second electrode 30 and is electrically connected to the second semiconductor layer 122. The first pad 80a and the second pad 80b include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or a stack or alloy of the above materials. The first pad 80a and the second pad 80b may be composed of a single layer or multiple layers. For example, the first pad 80a and the second pad 80b may include Ti/Au, Ti/Pt/Au, Cr/Au, Cr/Pt/Au, Ni/Au, Ni/Pt/Au, or Cr/Al/Cr/Ni/Au. After the subsequent dicing process is completed and an independent light-emitting element 1 is formed, the first pad 80a and the second pad 80b are bonded to a circuit on a carrier (not shown) in a flip chip manner to achieve connection with an external electronic component or an external power source. In another embodiment, the first pad 80a and/or the second pad 80b can be covered on the second protective layer 25. In another embodiment, the first pad 80a and/or the second pad 80b can be distributed in an inner area of the semiconductor stack 12 to avoid the exposed area 28, so as to avoid the peeling of the interfaces between the pads and the semiconductor stack 12 due to the height difference. The surfaces of the first solder pad 80a and the second solder pad 80b have a plurality of recesses (not shown) formed corresponding to the opening 502 of the first reflective structure 50. Through these recesses, the bonding force between the solder pad and the carrier can be enhanced in the subsequent packaging process to improve the process yield.

Finally, the semiconductor wafer is divided into a plurality of light-emitting elements 1 along the aisle area ISO, that is, around each light-emitting element 1. In one embodiment, as shown in FIG. 3F, the lower surface of the substrate 10 is irradiated with a laser 27, and the laser 27 is focused inside the substrate 10 to form a metamorphic region (not shown) inside the substrate 10, and then cracks are formed along the crystal plane of the substrate 10 from the metamorphic region to separate each light-emitting element 1. However, the cutting method of this embodiment is not limited to this, and any other method suitable for cutting a wafer into light-emitting elements can also be applied.

In one embodiment, FIG. 4A to FIG. 4C show partial cross-sectional views along A-A" in the steps of FIG. 2A to FIG. 2E in the method for manufacturing the light-emitting element 1. FIG. 4A shows that a lower protective layer 23a, a transparent conductive layer 18 and a first reflective structure 50 material layer are formed on the semiconductor stack 12. The thickness of the lower protective layer 23a on the exposed area 28 is t1. Then, referring to FIG. 4B, openings 501 and 502 are formed in the first reflective structure 50 material layer by etching to remove the first reflective structure 50 material layer above the exposed area 28. The etching includes dry etching, such as inductively coupled plasma (ICP). In one embodiment, the etching includes dry etching combined with wet etching. When etching the first reflective structure 50 material layer to form the opening 502, the second semiconductor layer 122 will not be damaged by etching because the transparent conductive layer 18 covers the second semiconductor layer 122. When etching the first reflective structure 50 material layer to form the opening 501 and removing the first reflective structure 50 material layer above the exposed area 28, the first semiconductor layer 121 at the bottom of the exposed area 28 will not be damaged by etching because the lower protective layer 23a covers the exposed area 28. After the step of etching the first reflective structure 50 is completed, , the lower protective layer 23a located in the exposed area 28 has a thickness t1'. The thickness t1' is greater than 100Å and the thickness t1' is less than the thickness t1. By covering the exposed area 28 with the lower protective layer 23a to protect the first semiconductor layer 121, it can be ensured that the opening 501 of the first reflective structure 50 can be completely opened, and its material layer is not left above the exposed area 28, and the first semiconductor layer 121 can be ensured not to be damaged. In another embodiment, not all the material layers of the first reflective structure 50 on the exposed area 28 are removed, but only the material layers of the first reflective structure 50 on the exposed area 28 in the inner area of the semiconductor stack 12 are removed.

Next, referring to FIG. 4C , the second reflective structure 36, the upper protective layer 23b, and the openings 231, 232, and 230 of the upper protective layer are formed in sequence (not shown in FIG. 4C ). The upper protective layer 23b and the lower protective layer 23a constitute the first protective layer 23. On the exposed area 28 and the second semiconductor layer 122 near the exposed area 28, the upper protective layer 23b is superimposed on the lower protective layer 23a and connected thereto. While the openings 230 and 231 are formed, the lower protective layer 23a directly below the openings 230 and 231 is also removed. That is, the first protective layer 23 has a plurality of openings 230 disposed at intervals around it, exposing the upper surface 121a of the first semiconductor layer, and a plurality of openings 231 disposed in the exposed area 28 inside the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. The thickness of the first protective layer 23 above the bottom of the exposed area 28 (i.e., the sum of the thickness t1' of the lower protective layer 23a located in the exposed area 28 and the thickness of the upper protective layer 23b) is T, and the thickness of the first protective layer 23 on the second semiconductor layer 122 (i.e., the sum of the thickness of the lower protective layer 23a located there and the thickness of the upper protective layer 23b) is T', and T is less than T'. In one embodiment, the difference between T and T' is greater than 2000Å. In another embodiment, the difference between T and T' is greater than 3000Å. In one embodiment, the thickness t1' of the lower protective layer 23a located in the exposed area 28 is less than the thickness t1 of the lower protective layer 23a located on the upper surface of the second semiconductor layer 122. Then, according to the steps in Figures 2F to 2H above, the light-emitting element 1 is completed.

FIG5A and FIG5B respectively show cross-sectional views along the line segment B-B' and the line segment C-C' after the steps of FIG2A to FIG2F are completed. Referring to FIG2F and FIG5A, the first electrode 20 contacts the upper surface 121a of the first semiconductor stack exposed by the opening 230 of the first protective layer 23. Referring to FIG2F and FIG5B, in the area without the opening 230, the first protective layer 23 covers the exposed area 28 around the semiconductor stack 12, so that the first electrode 20 does not contact the upper surface 121a of the first semiconductor stack. In this way, around the semiconductor stack 12, the first electrode 20 contacts the upper surface 121a of the first semiconductor stack at intervals through the openings 230 arranged at intervals, so that the current is evenly diffused around the semiconductor stack 12.

FIG1A shows a top view of the light-emitting element 1 manufactured according to the manufacturing method of this embodiment, FIG1B shows a cross-sectional view along the line segment A-A’ in FIG1A, and FIG1C shows a partial enlarged view of FIG1B.

1A, 1B and 1C, the light-emitting element 1 includes a substrate 10, a semiconductor stack 12 located on the substrate 10, an exposed area 28 located around and inside the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer, a transparent conductive layer 18 located on the second semiconductor layer 122, a first reflective structure 50 located on the transparent conductive layer 18, including a plurality of openings 502 to expose the transparent conductive layer 18, and a second reflective structure 36 located on the first reflective structure 50, and electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 through the first reflective structure opening 502. The second reflective structure 36 and the first reflective structure 50 form an omnidirectional reflector (ODR) to enhance the reflection of light and the brightness of the light-emitting element 1. The first protective layer 23 covers the exposed area 28 and extends to cover a portion of the upper surface of the second semiconductor layer 122. The first protective layer 23 includes a lower protective layer 23a and an upper semiconductor layer 23b. The lower protective layer 23a contacts the semiconductor stack 12. More specifically, the lower protective layer 23a contacts the side wall and a portion of the bottom of the exposed area 28. The upper protective layer 23b extends from the exposed area 28 to cover the second reflective structure 36 and includes an opening 232 to expose the second reflective structure 36. In addition, the first protective layer 23 includes an opening 231 located in the exposed area 28 in the inner area of the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. In one embodiment, the first protective layer 23 further includes an opening 230 located in an exposed area 28 around the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. The thickness of the first protective layer 23 above the bottom of the exposed area 28 is T, and the thickness of the first protective layer 23 on the second semiconductor layer 122 is T', and T is less than T'. In one embodiment, the difference between T and T' is greater than 2000Å. In another embodiment, the difference between T and T' is greater than 3000Å.

The first electrode 20 covers the first protective layer 23 and is electrically connected to the first semiconductor layer 121 through the first protective layer openings 231 and 230. The second electrode 30 is separated from the first electrode 20 and contacts the second reflective structure 36 through the upper protective layer opening 232 and is electrically connected to the second semiconductor layer 122. In one embodiment, the second electrode 30 is located in the upper protective layer opening 232. In another embodiment, the second electrode 30 is located in the upper protective layer opening 232 and further extends to the upper protective layer 23b. The second protective layer 25 is located on the first electrode 20 and the second electrode 30, including an opening 251 exposing the first electrode 20 and an opening 252 exposing the second electrode 30. As shown in FIG1B , the second protective layer 25 further covers the sidewalls around the semiconductor stack 12 and the upper surface 10a of the substrate. In one embodiment, the second protective layer 25 includes a distributed Bragg reflection structure, which can increase the reflection of light around the semiconductor stack 12 and enhance the brightness of the light-emitting element 1. The first pad 80a is located at the opening 251 and contacts the first electrode 20. The second pad 80b is located at the opening 252 and contacts the second electrode 30.

FIG. 1A shows a top view of the light-emitting element 2 of the first embodiment of the present application. FIG. 7A to FIG. 7I show top views of each stage in the manufacturing method of the light-emitting element 2 of the first embodiment of the present application; FIG. 8A to FIG. 8G show cross-sectional views of each stage in the manufacturing method of the light-emitting element 2. The manufacturing method of the light-emitting element 2 is described in detail as follows. Some processes and structures of the light-emitting element 2 are similar to those of the light-emitting element 1. For similar processes and structures, please refer to the description and drawings of the light-emitting element 1. The differences will be described in detail later. First, referring to FIG. 7A to FIG. 7B and FIG. 8A, the steps are as described in FIG. 2A to FIG. 2B and FIG. 3A, so they will not be described here.

Next, referring to FIG. 7C and FIG. 8B, an etch stop layer 26 formation step is performed. FIG. 8B shows a cross-sectional view along the line segment A-A’ after the steps of FIG. 7A to FIG. 7C are completed. FIG. 7C only shows the platform MS, the transparent conductive layer 18 and the etch stop layer 26. First, an etch stop material layer (not shown) is formed on the upper surface of the transparent conductive layer 18, and then an etch stop layer 26 is formed on the upper surface of the transparent conductive layer 18 by a process such as image etching or lift-off. The etch stop layer 26 is a plurality of island structures separated from each other.

In one embodiment, the etch stop layer 26 comprises a metal, and the metal material comprises a reflective metal having a high reflectivity to the light emitted by the light-emitting element 2, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), or alloys or stacks of the above materials.

In one embodiment, the etch stop layer 26 includes a barrier layer (not shown) and a contact layer (not shown). The contact layer is located between the transparent conductive layer 18 and the barrier layer. The barrier layer can prevent the migration, diffusion or oxidation of the metal elements of the contact layer. The material of the contact layer includes a metal material with high reflectivity for the light emitted by the semiconductor stack 12, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru) or alloys or stacks of the above materials. The material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn) or alloys or stacks of the above materials. In one embodiment, when the barrier layer is a metal stack, the barrier layer is formed by alternating stacking of two or more metal layers, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W, Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc.

Next, referring to FIG. 7D and FIG. 8C , a step of forming a first reflective structure 50 is performed. FIG. 8C shows a cross-sectional view along the line segment A-A’ after the steps of FIG. 7A to FIG. 7D are completed. FIG. 7D only shows the high platform MS and the first reflective structure 50. First, a reflective material layer is formed on the upper surface of the second semiconductor layer 122, and then, by a process such as developing and etching, mutually separated openings 501 and 502 are formed in the reflective material layer to form the first reflective structure 50. The position of the opening 501 corresponds to the exposed area 28 and the transparent conductive layer opening 180, and the opening 502 is distributed on the second semiconductor layer 122 and exposes the etching stop layer 26 thereunder. The material, stacking, thickness and formation method of the first reflective structure 50 are described in FIGS. 6A to 6B , so they will not be described here in detail.

In one embodiment, the etch stop layer 26 includes a central portion exposed by the opening 502 and an edge portion overlapping the first reflective structure 50. When the first reflective structure 50 is etched by imaging, the central portion of the etch stop layer 26 may be overetched, so that the thickness of the central portion of the etch stop layer 26 is smaller than that of the edge portion of the etch stop layer 26.

Next, referring to FIG. 7E and FIG. 8D , a second reflective structure 36 formation step is performed. FIG. 8D shows a cross-sectional view along the line segment A-A’ after the steps of FIG. 7A to FIG. 7E are completed. FIG. 7E only shows the high platform MS and the second reflective structure 36. The second reflective structure 36 is formed on the transparent conductive layer 18, the etch stop layer 26 and the first reflective structure 50, and is electrically connected to the etch stop layer 26, the transparent conductive layer 18 and the second semiconductor layer 122 through the opening 502 of the first reflective structure 50, and includes a plurality of openings 360 corresponding to the opening 501 of the first reflective structure 50, formed on the exposed area 28. The second reflective structure 36 includes a metal structure, which may include a single metal layer or a stack formed by a plurality of metal layers. In one embodiment, the ratio of the projection area of the second semiconductor layer 122 on the substrate 10 to the projection area of the second reflective structure 36 on the substrate 10 is 100% to 120%. By adjusting the area of the second reflective structure 36 to be close to the projection area of the second semiconductor layer 122 on the substrate 10, the reflection area of the second reflective structure 36 is increased, and the light extraction efficiency of the light-emitting element is improved. The material, stacking, thickness and formation method of the second reflective structure 36 are described in Figures 2D and 3C, so they are not repeated here.

Finally, referring to Figures 7F to 7I and Figures 8E to 8G, the steps are as described in Figures 2E to 2H and Figures 3D to 3F, so they will not be repeated here.

In one embodiment, FIG. 9A to FIG. 9C show partial cross-sectional views along A-A" in the steps of FIG. 7A to FIG. 7F in the method for manufacturing the light-emitting element 2. FIG. 9A shows the formation of a lower protective layer 23a, a transparent conductive layer 18, an etching stop layer 26 and a first reflective structure 50 on the semiconductor stack 12. Part of the first reflective structure 50 material layer is formed on the lower protective layer 23a located in the exposed area 28, and the thickness of the lower protective layer 23a on the exposed area 28 is t1. Then, referring to FIG. 9B, openings 501 and 502 are formed in the first reflective structure 50 material layer by etching, and the first reflective structure 50 material layer above the exposed area 28 is removed. The etching includes dry etching, such as inductively coupled plasma (ICP). In one embodiment, the etching includes dry etching combined with wet etching. When etching the material layer of the first reflective structure 50 to form the opening 502, since the etching stop layer 26 covers the transparent conductive layer 18, the transparent conductive layer 18 will not be damaged by etching. When etching the material layer of the first reflective structure 50 to form the opening 501 and removing the first reflective structure 50 above the exposed area 28, since the lower protective layer 23a covers the exposed area 28, the first semiconductor layer 121 at the bottom of the exposed area 28 will not be damaged by etching. After the step of etching the first reflective structure 50 is completed, the lower protective layer 23a located in the exposed area 28 has a thickness t1'. The thickness t1' is greater than 100Å and the thickness t1' is less than the thickness t1. By covering the exposed area 28 with the lower protective layer 23a to protect the first semiconductor layer 121, it can be ensured that the opening 501 of the first reflective structure 50 can be completely opened, and no material layer is left above the exposed area 28, and the first semiconductor layer 121 is not damaged. In another embodiment, not all the material layers of the first reflective structure 50 on the exposed area 28 are removed, but only the first reflective structure 50 on the exposed area 28 in the inner area of the semiconductor stack 12 is removed. Referring to FIG. 9C, the stacking relationship between the first protective layer 23 and other layers and the thickness difference at different positions are as described in FIG. 4C, so it is not repeated here.

FIG. 10A and FIG. 10B respectively show the cross-sectional views of FIG. 7G along the B-B’ line segment and the C-C’ line segment after the steps of FIG. 7A to FIG. 7G are completed. Referring to FIG. 7G and FIG. 10A to FIG. 10B, the stacking position relationship of the first electrode 20, the first protective layer 23 and the semiconductor stack 12 is as described in FIG. 2F and FIG. 5A to FIG. 5B, so it will not be repeated here.

FIG1A shows a top view of the light-emitting element 2 manufactured according to the manufacturing method of this embodiment, FIG1D shows a cross-sectional view along the line segment A-A’ in FIG1A, and FIG1E shows a partial enlarged view of FIG1D.

1A, 1D and 1E, the light emitting element 2 includes a substrate 10, a semiconductor stack 12 located on the substrate 10, an exposed area 28 located around and inside the semiconductor stack 12 to expose the upper surface 121a of the first semiconductor layer, a transparent conductive layer 18 located on the second semiconductor layer 122, and an etch stop layer 26 located on the transparent conductive layer 18, including a plurality of The first reflective structure 50 is located on the transparent conductive layer 18 and the etch stop layer 26, and includes a plurality of openings 502 that expose the etch stop layer 26. The second reflective structure 36 is located on the first reflective structure 50, and is electrically connected to the etch stop layer 26, the transparent conductive layer 18, and the second semiconductor layer 122 through the first reflective structure openings 502. The second reflective structure 36 and the first reflective structure 50 form an omnidirectional reflector (ODR) to enhance light reflection and the brightness of the light-emitting element 1. However, the stacking relationship between the first protective layer 23 and other layers and the thickness relationship at different positions, as well as the stacking relationship between the first electrode 20, the second electrode 30, the first pad 80a and the second pad 80b and other layers have been described in FIG. 1B and FIG. 1C, so they will not be repeated here.

FIG. 11 is a schematic diagram of a light-emitting device 3 according to an embodiment of the present invention. The light-emitting elements 1 and 2 in the above-mentioned embodiment are mounted on the first pad 511 and the second pad 512 of the carrier 51 in the form of a flip chip. The first pad 511 and the second pad 512 are electrically insulated by an insulating portion 53 containing an insulating material. The flip chip mounting is to turn the substrate 10 opposite to the pad forming surface upward as the main light-emitting surface. In order to increase the light extraction efficiency of the light-emitting device 3, a reflective structure 54 can be set around the light-emitting elements 1 and 2.

FIG. 12 is a schematic diagram of a light-emitting device 4 according to an embodiment of the present invention. The light-emitting device 4 includes a lampshade 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616, and an electrical connection element 618. The light-emitting module 610 includes a carrier 606, and a plurality of light-emitting units 608 located on the carrier 606, wherein the plurality of light-emitting units 608 may be the light-emitting elements 1, 2, or the light-emitting device 3 in the aforementioned embodiment.

However, the above embodiments are only for illustrative purposes to illustrate the principles and effects of this application, and are not intended to limit this application. Anyone with common knowledge in the technical field to which this application belongs can modify and change the above embodiments without violating the technical principles and spirit of this application. For example, all equivalent changes and modifications made according to the shape, structure, features and spirit described in the patent scope of this application should be included in the patent scope of this application.

1: Light-emitting element

10: Substrate

12: Semiconductor stacking

121: First semiconductor layer

121a: Upper surface of the first semiconductor layer

122: Second semiconductor layer

123: Active layer

18: Transparent conductive layer

28: Exposed area

20: First electrode

30: Second electrode

36: Second reflection structure

23a: Lower protective layer

23b: Upper protective layer

23: First protective layer

231: Opening of the first protective layer

232: Upper protective layer opening

25: Second protective layer

252: Second protective layer opening

50: First reflection structure

502: First reflection structure opening

T, T’: thickness

Claims (12)

A light-emitting element comprises: a semiconductor stack, comprising a first semiconductor layer, an active layer, a second semiconductor layer and an exposed area, wherein the exposed area comprises a side wall of the semiconductor stack and an upper surface of the first semiconductor layer; a first protective layer, covering the exposed area and a portion of the semiconductor stack; a dielectric material stack, located on the semiconductor stack, comprising a plurality of dielectric material pairs formed by alternating dielectric material layers with different refractive indices. A stack and one or more first openings; and a metal structure located on the dielectric material stack, filling the first opening or the first openings and electrically connected to the second semiconductor layer; wherein the first protective layer includes a first portion located on the upper surface of the first semiconductor layer in the exposed area and having a first thickness, and a second portion located on the second semiconductor layer and having a second thickness, the first thickness being less than the second thickness. The light-emitting element as described in claim 1, wherein: the first protective layer includes a lower protective layer and an upper protective layer, the lower protective layer contacts the semiconductor stack; and the dielectric material stack is located between the lower protective layer and the upper protective layer. A light-emitting element as described in claim 2, wherein the metal structure is located below the upper protective layer. The light-emitting element as described in claim 1 further comprises a first electrode located on the first protective layer; and the first protective layer comprises one or more third openings located in the exposed area, and the first electrode contacts the upper surface of the first semiconductor layer through the third opening or the third openings. A light-emitting element comprises: a semiconductor stack, comprising a first semiconductor layer, an active layer, a second semiconductor layer and an exposed area, wherein the exposed area comprises an upper surface of the first semiconductor layer and a side wall of the semiconductor stack; a lower protective layer, covering the exposed area; a dielectric material stack, covering the semiconductor stack, comprising a plurality of dielectric material pairs alternately stacked by dielectric materials with different refractive indices and one or more first openings; a metal structure, located on the dielectric material stack, filling the first opening or the first openings and the metal structure; The second semiconductor layer is electrically connected; an upper protective layer, covering the semiconductor stack, the exposed area and the metal structure, including a plurality of second openings respectively exposing the exposed area and the metal structure; and a first electrode, located on the upper protective layer; wherein the dielectric material stack is located between the upper protective layer and the lower protective layer, the second opening of the upper protective layer includes a second inclined sidewall located in the exposed area, and the first electrode conformally covers the second inclined sidewall and contacts the exposed area; wherein the upper protective layer contacts the lower protective layer. The light-emitting element as described in claim 1 or 5 further comprises an etch stop layer located between the second semiconductor layer and the dielectric material stack, and the first opening or the first openings expose the etch stop layer. A light-emitting element as described in claim 6, wherein the etch stop layer comprises a transparent conductive layer or a metal layer. The light-emitting element as described in claim 2 or 5 further comprises: a second electrode located on the upper protective layer; a second protective layer located on the second electrode, covering the exposed area, and comprising a third opening to expose the second electrode; and a solder pad connected to the second electrode through the third opening. The light-emitting element as described in claim 8, wherein the second protective layer comprises another dielectric material stack, the other dielectric material stack comprises a plurality of dielectric material pairs alternately stacked by dielectric materials of different refractive indices; wherein the second protective layer comprises m pairs of dielectric material pairs, the dielectric material stack comprises n pairs of dielectric material pairs, wherein m is greater than n. A light-emitting element as described in claim 1 or 5, wherein the exposure area includes a plurality of first exposure areas located in the inner area of the semiconductor stack and a plurality of second exposure areas located in the surrounding area of the semiconductor stack when viewed from above. The light-emitting element as described in claim 10, wherein the distribution density of the first openings between two adjacent first exposed areas is less than the distribution density of the first openings in other areas when viewed from above. A light-emitting element as described in claim 1 or 5, wherein the first opening comprises a first inclined side wall, and the first inclined side wall has an angle between 5 degrees and 80 degrees.

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