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TWI799231B - Light-emitting element and manufacturing method thereof - Google Patents

Light-emitting element and manufacturing method thereof Download PDF

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TWI799231B
TWI799231B TW111113900A TW111113900A TWI799231B TW I799231 B TWI799231 B TW I799231B TW 111113900 A TW111113900 A TW 111113900A TW 111113900 A TW111113900 A TW 111113900A TW I799231 B TWI799231 B TW I799231B
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light
semiconductor
conductive
conductive layers
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TW202230832A (en
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柯竣騰
陳昭興
王佳琨
郭彥良
陳誌濠
鍾偉榮
王志銘
彭韋智
洪詳竣
林予堯
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晶元光電股份有限公司
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Abstract

A light-emitting device is disclosed. The light-emitting device comprises a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; one or more via-like exposed regions formed within the semiconductor stack and exposing the first semiconductor layer; a first insulating layer formed on the semiconductor stack and including one or more first openings corresponding to the one or more via-like exposed regions and one or more second openings on the second semiconductor; one or more first conductive layers corresponding to the one or more via-like exposed regions and electrically connected to the first semiconductor layer through the one or more first openings; one or more second conductive layers formed on the second semiconductor and electrically connected to the second semiconductor layer through the one or more second openings; a first electrode layer formed on the one or more first conductive layers and electrically connected to the first semiconductor layer; a bonding layer formed on the first electrode layer; a conductive substrate, wherein the semiconductor stack is located on one side of the bonding layer, and the conductive substrate is located on an opposite side of the bonding layer; an exposed region formed on a side or a corner of the light-emitting device and not overlapping with the semiconductor stack; and a wire-bonding pad formed on the exposed region and electrically connected to the one or more first conductive layers or the one or more second conductive layers.

Description

發光元件及其製造方法Light emitting element and manufacturing method thereof

本發明係關於一種發光元件及其製造方法，更詳言之，係關於一種具有高亮度之發光元件。The present invention relates to a light-emitting element and its manufacturing method, more specifically, to a light-emitting element with high brightness.

發光二極體(light-emitting diode, LED)為P型半導體與N型半導體所組成之光電元件，透過P-N接面上載子的結合放出光線，加上具有體積小、低耗電量、壽命長、反應速度快等優點，廣泛地使用於光學顯示裝置、交通號誌、資料儲存裝置、通訊裝置、照明裝置與醫療器材等。Light-emitting diode (light-emitting diode, LED) is a photoelectric element composed of P-type semiconductor and N-type semiconductor. It emits light through the combination of carriers on the P-N junction, and has small size, low power consumption, and long life. , fast response and other advantages, widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices and medical equipment.

一發光元件，包含：一半導體疊層具有一第一半導體層，一第二半導體層，以及一活性層位於第一半導體層及第二半導體層之間；一或多個孔部暴露區，位於半導體疊層內，暴露出第一半導體層；一第一絕緣層，位於半導體疊層上，包含一或多個第一開口對應一或多個孔部暴露區，及一或多個第二開口位於第二半導體層上；一或多個第一導電層，對應一或多個孔部暴露區，藉由一或多個第一開口與第一半導體層電性連接；一或多個第二導電層，位於第二半導體層上，藉由一或多個第二開口與第二半導體層電性連接；一第一電極層，位於一或多個第一導電層上，且與第一半導體層電性連接；一接合層，位於第一電極層上；一導電基板，其中半導體疊層位於接合層之一側，導電基板位於接合層相對於半導體疊層之另一側；一暴露區域，位於發光元件之一邊或一角落，與半導體疊層不重疊；以及一打線墊，位於暴露區域上，，電性連接於該一或多個第一導電層或該一或多個第二導電層。A light-emitting element, comprising: a semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; one or more hole exposure regions located at In the semiconductor stack, the first semiconductor layer is exposed; a first insulating layer, located on the semiconductor stack, includes one or more first openings corresponding to one or more hole exposure regions, and one or more second openings Located on the second semiconductor layer; one or more first conductive layers, corresponding to one or more hole exposure regions, electrically connected to the first semiconductor layer through one or more first openings; one or more second a conductive layer located on the second semiconductor layer and electrically connected to the second semiconductor layer through one or more second openings; a first electrode layer located on the one or more first conductive layers and connected to the first semiconductor layer Layers are electrically connected; a bonding layer is located on the first electrode layer; a conductive substrate, wherein the semiconductor stack is located on one side of the bonding layer, and the conductive substrate is located on the other side of the bonding layer relative to the semiconductor stack; an exposed area, Located on one side or a corner of the light-emitting element, not overlapping with the semiconductor stack; and a wiring pad, located on the exposed area, electrically connected to the one or more first conductive layers or the one or more second conductive layers .

本申請案之實施例會被詳細地描述，並且繪製於圖式中，相同或類似的部分會以相同的號碼在各圖式以及說明出現。Embodiments of the present application will be described in detail and drawn in the drawings, and the same or similar parts will appear with the same numbers in the drawings and descriptions.

第11B係本申請案一實施例中所揭示之一發光元件1；第1A~11B圖係揭示本申請案發光元件1的製造方法。Fig. 11B is a light-emitting element 1 disclosed in an embodiment of the present application; Figs. 1A-11B disclose the manufacturing method of the light-emitting element 1 of the present application.

如第1A圖之上視圖及第1B圖沿第1A圖線段A-A’之剖面圖所示，發光元件1的製造方法包含一平台形成步驟，其包含提供一成長基板11；以及形成一半導體疊層10於成長基板11上。其中半導體疊層10包含一第一半導體層101、一第二半導體層102，以及一活性層103位於第一半導體層101及第二半導體層102之間。半導體疊層10藉由微影、蝕刻之方式移除部分的第二半導體層102及活性層103，以暴露出第一半導體層101及第二半導體層102及活性層103之側壁，形成複數個暴露區。其中，暴露區包含位於半導體疊層10週圍的環繞暴露區15，以及位於半導體疊層10內部的一或多個孔部暴露區17。由上視觀之，其中環繞暴露區15中寬度較寬之區域為一區域E1。於本實施例中，除部分區域之第二半導體層102及活性層103被移除外，還更進一步移除部分第一半導體層101，在環繞暴露區15內形成一第一表面S1及在孔部暴露區17形成一第二表面S2。其中，第一半導體層101、第二半導體層102及活性層103之側壁構成環繞暴露區15及一或多個孔部暴露區17之側壁；第一半導體層101次露出的第一表面S1構成環繞暴露區15之底面，第二表面S2構成孔部暴露區17之底面。由上視觀之，環繞暴露區15圍繞所有活性層103及第二半導體層102。第一表面S1與第二表面S2可於相同的蝕刻製程中形成，因此第一表面S1與第二表面S2相對於半導體疊層10之頂面102s具有相同的深度。孔部暴露區17的形狀包含圓形、橢圓形、矩形、多邊形、或是任意形狀，於本實施例中，包含多個孔部暴露區17，其形狀呈條狀，其中，多個孔部暴露區17的配置、數量及大小可依電流分佈的需求及發光元件之大小而有不同的設計。As shown in the top view of FIG. 1A and the cross-sectional view of FIG. 1B along the line AA' of FIG. 1A, the manufacturing method of the light-emitting element 1 includes a step of forming a platform, which includes providing a growth substrate 11; and forming a semiconductor The stack 10 is on the growth substrate 11 . The semiconductor stack 10 includes a first semiconductor layer 101 , a second semiconductor layer 102 , and an active layer 103 located between the first semiconductor layer 101 and the second semiconductor layer 102 . The semiconductor stack 10 removes part of the second semiconductor layer 102 and the active layer 103 by means of lithography and etching to expose the sidewalls of the first semiconductor layer 101 and the second semiconductor layer 102 and the active layer 103, forming a plurality of exposed area. Wherein, the exposed area includes a surrounding exposed area 15 located around the semiconductor stack 10 , and one or more hole exposed areas 17 located inside the semiconductor stack 10 . Viewed from above, the wider area surrounding the exposed area 15 is an area E1. In this embodiment, in addition to removing part of the second semiconductor layer 102 and the active layer 103, part of the first semiconductor layer 101 is further removed to form a first surface S1 in the surrounding exposed region 15 and a The hole exposure area 17 forms a second surface S2. Wherein, the sidewalls of the first semiconductor layer 101, the second semiconductor layer 102, and the active layer 103 constitute the sidewalls surrounding the exposed region 15 and one or more hole exposed regions 17; the exposed first surface S1 of the first semiconductor layer 101 constitutes Surrounding the bottom surface of the exposed region 15 , the second surface S2 constitutes the bottom surface of the hole exposed region 17 . Viewed from above, the surrounding exposed region 15 surrounds all the active layer 103 and the second semiconductor layer 102 . The first surface S1 and the second surface S2 can be formed in the same etching process, so the first surface S1 and the second surface S2 have the same depth relative to the top surface 102 s of the semiconductor stack 10 . The shape of the hole exposed area 17 includes circular, elliptical, rectangular, polygonal, or any shape. In this embodiment, it includes a plurality of hole exposed areas 17, which are strip-shaped, wherein the plurality of hole The configuration, quantity and size of the exposed regions 17 can be designed in different ways according to the requirement of current distribution and the size of the light emitting element.

於本申請案之一實施例中，半導體疊層10可僅包含環繞暴露區15而不包含孔部暴露區17。In an embodiment of the present application, the semiconductor stack 10 may only include the surrounding exposed area 15 without including the hole exposed area 17 .

於本申請案實施例中成長基板11之尺寸包含晶圓級基板或晶粒級基板，半導體疊層10包含晶圓級半導體疊層或晶粒級半導體疊層。此處所指的晶圓不限於圓形，包含多邊形或不規則形狀。此處所指的晶圓，可於後續製程中分割成複數個晶粒等級的發光元件；亦可以不進行分割直接形成發光元件。於本申請案之各實施例中，為方便說明，圖式中所繪示之各步驟之結構，例如成長基板11、半導體疊層10係以單一發光元件表示，但本實施例並不限於此，平台形成步驟與後續各製程皆可在晶圓等級下完成。In the embodiment of the present application, the size of the growth substrate 11 includes a wafer-level substrate or a grain-level substrate, and the semiconductor stack 10 includes a wafer-level semiconductor stack or a grain-level semiconductor stack. The wafers referred to here are not limited to circular shapes, but include polygonal or irregular shapes. The wafer referred to here can be divided into a plurality of light-emitting elements at the grain level in subsequent manufacturing processes; light-emitting elements can also be directly formed without dividing. In each embodiment of this application, for the convenience of description, the structure of each step shown in the drawings, such as the growth substrate 11 and the semiconductor stack 10 is represented by a single light emitting element, but this embodiment is not limited thereto , platform formation steps and subsequent processes can be completed at the wafer level.

於本申請案之一實施例中，成長基板11包括用以成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓，或用以成長氮化銦鎵(InGaN)之藍寶石(Al 2O 3)晶圓、氮化鎵(GaN)晶圓或碳化矽(SiC)晶圓。在成長基板11欲形成半導體疊層10之表面上，可具有圖案化結構(圖未示)。此外，於此成長基板11上可利用有機金屬化學氣相沉積法(MOCVD)、分子束磊晶(MBE)、氫化物氣相沉積法(HVPE)、蒸鍍法或離子電鍍方法形成具有光電特性之半導體疊層10，例如發光(light-emitting)疊層。 In one embodiment of the present application, the growth substrate 11 includes a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al 2 O 3 ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer. There may be a patterned structure (not shown) on the surface of the growth substrate 11 where the semiconductor stack 10 is to be formed. In addition, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), vapor deposition, or ion plating methods can be used to form photoelectric properties on the growth substrate 11 . The semiconductor stack 10 is, for example, a light-emitting (light-emitting) stack.

於本申請案之一實施例中，在形成半導體疊層10之前，可在成長基板11上先形成一緩衝層(圖未示)。緩衝層可減緩成長基板11與半導體疊層10之間晶格常數的不匹配，以改善磊晶品質。In an embodiment of the present application, before forming the semiconductor stack 10 , a buffer layer (not shown) may be formed on the growth substrate 11 . The buffer layer can slow down the lattice constant mismatch between the growth substrate 11 and the semiconductor stack 10 to improve epitaxial quality.

於本申請案之一實施例中，第一半導體層101與第二半導體102層具有不同之導電性、電性、極性或摻雜物以分別提供電洞與電子。極性可為n型或p型，使得電子與電洞可於活性層103中複合以產生光線。舉例而言，第一半導體層101可為n型半導體層，第二半導體層102可為p型半導體層。半導體疊層10之材料包含Ⅲ-Ⅴ族半導體材料，例如Al xIn yGa (1-x-y)N或Al xIn yGa (1-x-y)P，其中0≦x，y≦1；(x+y)≦1。依據活性層之材料，當半導體疊層10材料為AlInGaP系列材料時，可發出波長介於610 nm及650 nm之間的紅光，波長介於530 nm及570 nm之間的綠光，當半導體疊層10材料為InGaN系列材料時，可發出波長介於450 nm及490 nm之間的藍光，或是當半導體疊層10材料為AlGaN、AlGaInN系列材料時，可發出波長介於400 nm及250 nm之間的紫外光。活性層103可為單異質結構(single heterostructure, SH )，雙異質結構(double heterostructure, DH)，雙側雙異質結構( double-side double heterostructure, DDH)，多層量子井結構(multi-quantum well, MQW)。活性層材料可為不摻雜摻雜物、摻雜p型摻雜物或摻雜n型摻雜物的半導體。 In one embodiment of the present application, the first semiconductor layer 101 and the second semiconductor layer 102 have different conductivity, electrical properties, polarity or dopants to provide holes and electrons respectively. The polarity can be n-type or p-type, so that electrons and holes can recombine in the active layer 103 to generate light. For example, the first semiconductor layer 101 can be an n-type semiconductor layer, and the second semiconductor layer 102 can be a p-type semiconductor layer. The material of the semiconductor stack 10 includes III-V group semiconductor materials, such as Al x In y Ga (1-xy) N or Al x In y Ga (1-xy) P, wherein 0≦x, y≦1; (x +y)≦1. According to the material of the active layer, when the material of the semiconductor stack 10 is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, and a green light with a wavelength between 530 nm and 570 nm. When the material of the stack 10 is an InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the material of the semiconductor stack 10 is an AlGaN or AlGaInN series material, it can emit blue light with a wavelength between 400 nm and 250 nm. UV light between nm. The active layer 103 can be a single heterostructure (single heterostructure, SH), a double heterostructure (double heterostructure, DH), a double-side double heterostructure (double-side double heterostructure, DDH), a multi-layer quantum well structure (multi-quantum well, MQW). The material of the active layer can be a semiconductor not doped with dopants, doped with p-type dopants or doped with n-type dopants.

接續平台形成步驟，如第2A圖之上視圖及第2B圖係為沿著第2A圖線段A-A’之剖面圖所示，發光元件1的製造方法包含一第一絕緣層20形成步驟。第一絕緣層20可藉由蒸鍍或沉積等方式形成一絕緣材料層於半導體疊層10上，再藉由微影、蝕刻之方式圖案化絕緣材料層，得到第一絕緣層20覆蓋環繞暴露區15之底面S1及孔部暴露區17之底面S2，並包覆半導體疊層10之側壁。其中第一絕緣層20包含一第一絕緣層環繞區20a，覆蓋環繞暴露區15的第一半導體層101之第一表面S1及半導體疊層10之側壁；以及一第一絕緣層覆蓋區20b，覆蓋孔部暴露區17的第一半導體層101之第二表面S2及半導體疊層10之側壁。第一絕緣層覆蓋區20b係彼此分離且分別對應多個孔部暴露區17。第一絕緣層20可為單層或多層之構造。當第一絕緣層20為單層膜時，第一絕緣層20可保護半導體疊層10之側壁以避免活性層103被後續製程所破壞。當第一絕緣層20為多層膜時，第一絕緣層20除了可保護半導體疊層10之側壁外，更可包含不同折射率的兩種以上之材料交替堆疊以形成一布拉格反射鏡(DBR)結構，選擇性地反射特定波長之光。第一絕緣層20係為非導電材料所形成，包含有機材料，例如Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、或氟碳聚合物(Fluorocarbon Polymer)，或是無機材料，例如矽膠(Silicone)、玻璃(Glass)，或是介電材料，例如氧化鋁(Al 2O 3)、氮化矽(SiN x)、氧化矽(SiO x)、氧化鈦(TiO x)，或氟化鎂(MgF x)。 Following the platform forming step, as shown in the top view of FIG. 2A and the cross-sectional view along the line AA' of FIG. 2A in FIG. 2B , the manufacturing method of the light-emitting element 1 includes a step of forming a first insulating layer 20 . The first insulating layer 20 can form an insulating material layer on the semiconductor stack 10 by evaporation or deposition, and then pattern the insulating material layer by means of lithography and etching, so that the first insulating layer 20 is covered and exposed. The bottom surface S1 of the region 15 and the bottom surface S2 of the hole portion expose the region 17 and cover the sidewall of the semiconductor stack 10 . Wherein the first insulating layer 20 includes a first insulating layer surrounding region 20a covering the first surface S1 of the first semiconductor layer 101 surrounding the exposed region 15 and the sidewall of the semiconductor stack 10; and a first insulating layer covering region 20b, The second surface S2 of the first semiconductor layer 101 covering the hole exposed region 17 and the sidewall of the semiconductor stack 10 are covered. The first insulating layer covering regions 20 b are separated from each other and respectively correspond to the plurality of hole exposure regions 17 . The first insulating layer 20 can be a single-layer or multi-layer structure. When the first insulating layer 20 is a single-layer film, the first insulating layer 20 can protect the sidewall of the semiconductor stack 10 to prevent the active layer 103 from being damaged by subsequent processes. When the first insulating layer 20 is a multilayer film, in addition to protecting the sidewall of the semiconductor stack 10, the first insulating layer 20 can also include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR). Structures that selectively reflect specific wavelengths of light. The first insulating layer 20 is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), or fluorine Carbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ).

於本發明之一實施例中，接續第一絕緣層形成步驟，如第3A圖之上視圖及第3B圖係為沿著第3A圖線段A-A’之剖面圖所示，發光元件1的製造方法包含一電流分散層18形成步驟。電流分散層18可藉由蒸鍍或沉積等方式形成於未被第一絕緣層20覆蓋的第二半導體層102上，且與第二半導體層102電性接觸，電流分散層18可以是金屬或是透明導電材料，其中金屬可選自具有透光性的薄金屬層，透明導電材料對於活性層103所發出的光線為透明，包含銦錫氧化物(ITO)、氧化鋁鋅(AZO)、氧化鎵鋅(GZO)、或銦鋅氧化物(IZO)等材料。In one embodiment of the present invention, following the step of forming the first insulating layer, as shown in the top view of FIG. 3A and the cross-sectional view along the line segment AA' of FIG. 3A in FIG. 3B , the light-emitting element 1 The manufacturing method includes a current spreading layer 18 forming step. The current spreading layer 18 can be formed on the second semiconductor layer 102 not covered by the first insulating layer 20 by evaporation or deposition, and is in electrical contact with the second semiconductor layer 102. The current spreading layer 18 can be made of metal or It is a transparent conductive material, wherein the metal can be selected from a thin metal layer with light transmission, and the transparent conductive material is transparent to the light emitted by the active layer 103, including indium tin oxide (ITO), aluminum zinc oxide (AZO), oxide Gallium zinc (GZO), or indium zinc oxide (IZO) and other materials.

於本申請案之一實施例中，於平台形成步驟之後，可先進行電流分散層18形成步驟，再進行第一絕緣層20形成步驟。In one embodiment of the present application, after the step of forming the platform, the step of forming the current spreading layer 18 can be performed first, and then the step of forming the first insulating layer 20 can be performed.

於本申請案之一實施例中，於平台形成步驟之後，可省略第一絕緣層20之形成步驟，直接進行電流分散層18形成步驟。In one embodiment of the present application, after the step of forming the platform, the step of forming the first insulating layer 20 can be omitted, and the step of forming the current spreading layer 18 can be directly performed.

接續電流分散層形成步驟，如第4A圖之上視圖及第4B係為沿著第4A圖線段A-A’之剖面圖所示，發光元件1的製造方法包含一反射結構16形成步驟。反射結構16可由一反射層(圖未示)及/或一阻障層(圖未示)所組成，可藉由蒸鍍或沉積等方式直接形成於電流分散層18上，其中反射層位於電流分散層18及阻障層(圖未示)之間。於本申請案實施例中，於第4A圖上視圖，反射結構16的外緣可設置於電流分散層18的外緣之內側、外側、或者與電流分散層18的外緣重合對齊，阻障層的外緣可設置於反射層的外緣之內側、外側、或者設置成與反射層的外緣重合對齊。於本申請案之另一實施例中，可省略電流分散層18，以反射結構16直接形成於第二半導體層102上。Following the step of forming the current spreading layer, as shown in the top view of FIG. 4A and the cross-sectional view along the line A-A' of FIG. 4A in FIG. 4B , the manufacturing method of the light-emitting element 1 includes a step of forming a reflective structure 16. The reflective structure 16 can be composed of a reflective layer (not shown) and/or a barrier layer (not shown), and can be directly formed on the current spreading layer 18 by evaporation or deposition, wherein the reflective layer is located on the current Between the dispersion layer 18 and the barrier layer (not shown). In the embodiment of the present application, in the upper view of FIG. 4A, the outer edge of the reflective structure 16 can be arranged inside, outside, or coincidently aligned with the outer edge of the current spreading layer 18 to block The outer edge of the layer can be disposed inside, outside, or coincidently aligned with the outer edge of the reflective layer. In another embodiment of the present application, the current spreading layer 18 can be omitted, and the reflective structure 16 can be directly formed on the second semiconductor layer 102 .

反射層可為一或多層之結構，多層結構例如為一布拉格反射(DBR)結構。反射層之材料包含反射率較高的金屬材料，例如銀(Ag)、鋁(Al)、金(Au)、鈦(Ti)、銅(Cu)、鉑(Pt)、鎳(Ni)或銠(Rh)等金屬或上述材料之合金。在此所述具有較高的反射率係指對於活性層103所發出光線的波長具有80%以上的反射率。於本申請案之一實施例中，阻障層包覆反射層以避免反射層表面氧化而使反射層之反射率劣化。阻障層之材料包含金屬材料，例如鈦(Ti)、鎢(W)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、鉻(Cr)、或鋅(Zn)等金屬或上述材料之合金。阻障層可為一或多層之結構，多層結構例如為鈦(Ti)/鋁(Al)，及/或鈦(Ti)/鎢(W)。The reflective layer can be one or multi-layer structure, such as a Bragg reflection (DBR) structure. The material of the reflective layer includes metal materials with high reflectivity, such as silver (Ag), aluminum (Al), gold (Au), titanium (Ti), copper (Cu), platinum (Pt), nickel (Ni) or rhodium (Rh) and other metals or alloys of the above materials. The high reflectivity mentioned here refers to having a reflectivity of more than 80% for the wavelength of the light emitted by the active layer 103 . In one embodiment of the present application, the barrier layer covers the reflective layer to prevent the surface oxidation of the reflective layer from deteriorating the reflectivity of the reflective layer. The material of the barrier layer includes metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), chromium (Cr), Or metals such as zinc (Zn) or alloys of the above materials. The barrier layer can be one or multilayer structure, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W).

接續反射結構形成步驟，如第5A之上視圖、第5B係為第5A圖沿著A-A’之剖面圖所示，發光元件1的製造方法包含一第二絕緣層50形成步驟。第二絕緣層50可藉由蒸鍍或沉積等方式形成一絕緣材料層於半導體疊層10上，再藉由微影、蝕刻之方式圖案化絕緣材料層，以形成第二絕緣層50，其包含一第一群組的第二絕緣層開口501以裸露出第一半導體層101，以及一第二群組的第二絕緣層開口502以裸露出反射結構16。其中在圖案化的過程中，於前述第一絕緣層20形成步驟中覆蓋於環繞暴露區15的第一絕緣層環繞區20a及孔部暴露區17內的第一絕緣層覆蓋區20b被部分蝕刻移除，以裸露出第一半導體層101之第一表面S1與第二表面S2，以形成一第一群組的第二絕緣層開口501、第一絕緣層環繞區20a’及第一絕緣層覆蓋區20b’。於本實施例中，於第5A圖上視圖所示，第一群組的第二絕緣層開口501及第二群組的第二絕緣層開口502具有不同的寬度、數目。第一群組的第二絕緣層開口501及第二群組的第二絕緣層開口502形狀包含圓形、橢圓形、矩形、多邊形、環形或是任意形狀。於本實施例中，如第5A圖所示，第一群組的第二絕緣層開口501為長條狀，彼此分離且分別對應多個孔部暴露區17，第二群組的第二絕緣層開口502為圓形，彼此分離且分佈於第一群組的第二絕緣層開口501週圍，呈矩陣式排列。Following the step of forming the reflective structure, as shown in the top view of FIG. 5A , and FIG. 5B is the cross-sectional view along A-A' of FIG. 5A , the manufacturing method of the light-emitting element 1 includes a second insulating layer 50 forming step. The second insulating layer 50 can form an insulating material layer on the semiconductor stack 10 by evaporation or deposition, and then pattern the insulating material layer by means of lithography and etching to form the second insulating layer 50. A first group of second insulating layer openings 501 are included to expose the first semiconductor layer 101 , and a second group of second insulating layer openings 502 is included to expose the reflective structure 16 . During the patterning process, the first insulating layer covering region 20b covering the first insulating layer surrounding region 20a surrounding the exposed region 15 and the hole exposed region 17 in the aforementioned first insulating layer 20 forming step is partially etched. removed to expose the first surface S1 and the second surface S2 of the first semiconductor layer 101 to form a first group of second insulating layer openings 501, the first insulating layer surrounding region 20a' and the first insulating layer Coverage area 20b'. In this embodiment, as shown in the top view of FIG. 5A , the first group of second insulating layer openings 501 and the second group of second insulating layer openings 502 have different widths and numbers. The shapes of the first group of second insulating layer openings 501 and the second group of second insulating layer openings 502 include circular, elliptical, rectangular, polygonal, circular or arbitrary shapes. In this embodiment, as shown in FIG. 5A, the second insulating layer openings 501 of the first group are elongated, separated from each other and respectively correspond to a plurality of hole exposure regions 17, and the second insulating layer openings 501 of the second group are elongated. The layer openings 502 are circular, separated from each other and distributed around the second insulating layer openings 501 of the first group, arranged in a matrix.

當第二絕緣層50為單層膜時，第二絕緣層50可保護半導體疊層10之側壁以避免活性層103被後續製程所破壞。當第二絕緣層50為多層膜時，第二絕緣層50可保護半導體疊層10之側壁，且可包含不同折射率的兩種以上之材料交替堆疊以形成一布拉格反射鏡(DBR)結構，選擇性地反射特定波長之光。第二絕緣層50係為非導電材料所形成，包含有機材料，例如Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、或氟碳聚合物(Fluorocarbon Polymer)，或是無機材料，例如矽膠(Silicone)、玻璃(Glass)，或是介電材料，例如氧化鋁(Al 2O 3)、氮化矽(SiN x)、氧化矽(SiO x)、氧化鈦(TiO x)、氧化鈮(Nb 2O 5)，或氟化鎂(MgF x)。 When the second insulating layer 50 is a single-layer film, the second insulating layer 50 can protect the sidewall of the semiconductor stack 10 to prevent the active layer 103 from being damaged by subsequent processes. When the second insulating layer 50 is a multilayer film, the second insulating layer 50 can protect the sidewall of the semiconductor stack 10, and can include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, Selectively reflect specific wavelengths of light. The second insulating layer 50 is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), or fluorine Carbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), niobium oxide (Nb 2 O 5 ), or magnesium fluoride (MgF x ).

接續第二絕緣層形成步驟，如第6A圖之上視圖、第6B圖係為沿著第6A圖線段A-A’之剖面圖所示，發光元件1的製造方法包含一導電層60形成步驟。導電層60可藉由蒸鍍或沉積等方式於第一半導體層101及第二半導體層102上形成一導電材料層，再藉由微影、蝕刻之方式圖案化導電材料層形成導電層60。如第6A圖所示，導電層60包含一第一導電區60a與一第二導電區60b，彼此藉由一環形縫隙60c在空間上相互分離。導電層60之第一導電區60a接觸環繞暴露區15內的第一半導體層101(即第一表面S1)，同時透過第一群組的第二絕緣層開口501與所有孔部暴露區17內的第一半導體層101(即第二表面S2)接觸，並延伸覆蓋環繞暴露區15與孔部暴露區17之側壁至一部份第二絕緣層50上表面。其中，區域E1的第一表面S1包含部份表面未被第一導電區60a覆蓋，為一區域S3。於本實施例中，由上視觀之，半導體疊層10之輪廓為一矩形，區域S3沿矩形之一邊設置。於本申請案另一實施例中，區域E1及區域S3可位於矩形之一或多個角落。導電層60之第二導電區60b分別填入各第二群組的第二絕緣層開口502，以接觸反射結構16，於本實施例中第二導電區60b與反射結構16之阻障層接觸，並覆蓋另一部份第二絕緣層50上表面。如此一來，第一導電區60a與第一半導體層101形成電性連接，並藉由第二絕緣層50與第二半導體層102電性絕緣，而第二導電區60b與第二半導體層102形成電性連接。導電層60之材料包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、或鉑(Pt)等金屬或上述材料之合金或疊層。Following the step of forming the second insulating layer, as shown in the top view of FIG. 6A and the cross-sectional view along the line AA' of FIG. 6A in FIG. 6B , the manufacturing method of the light-emitting element 1 includes a step of forming a conductive layer 60 . The conductive layer 60 can form a conductive material layer on the first semiconductor layer 101 and the second semiconductor layer 102 by evaporation or deposition, and then pattern the conductive material layer by lithography and etching to form the conductive layer 60 . As shown in FIG. 6A, the conductive layer 60 includes a first conductive region 60a and a second conductive region 60b, which are spatially separated from each other by an annular gap 60c. The first conductive region 60a of the conductive layer 60 is in contact with the first semiconductor layer 101 (i.e. the first surface S1) in the surrounding exposed region 15, and at the same time passes through the first group of second insulating layer openings 501 and all holes in the exposed region 17. The first semiconductor layer 101 (that is, the second surface S2 ) contacts and extends to cover the sidewalls surrounding the exposed region 15 and the hole exposed region 17 to a part of the upper surface of the second insulating layer 50 . Wherein, the first surface S1 of the region E1 includes a part of the surface not covered by the first conductive region 60a, which is a region S3. In this embodiment, viewed from above, the outline of the semiconductor stack 10 is a rectangle, and the region S3 is arranged along one side of the rectangle. In another embodiment of the present application, the area E1 and the area S3 may be located at one or more corners of the rectangle. The second conductive region 60b of the conductive layer 60 is respectively filled into the second insulating layer openings 502 of each second group to contact the reflective structure 16. In this embodiment, the second conductive region 60b is in contact with the barrier layer of the reflective structure 16 , and cover another part of the upper surface of the second insulating layer 50 . In this way, the first conductive region 60a is electrically connected to the first semiconductor layer 101, and is electrically insulated from the second semiconductor layer 102 by the second insulating layer 50, while the second conductive region 60b is electrically insulated from the second semiconductor layer 102. form an electrical connection. The material of the conductive layer 60 includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), Or metals such as platinum (Pt) or alloys or laminates of the above materials.

於本申請案之一實施例中，由上視觀之，導電層60之面積大於所有活性層103之面積。In one embodiment of the present application, viewed from above, the area of the conductive layer 60 is larger than the area of all the active layers 103 .

於本申請案之一實施例中，當發光元件1同時具有環繞暴露區15與一或多個孔部暴露區17，一外部電流注入發光元件1時，電流藉由第一導電區60a同時傳導至環繞暴露區15內與孔部暴露區17內的第一半導體層101，藉由將一或多個孔部暴露區17分散配置，以及將環繞暴露區15圍繞孔部暴露區17，可使發光元件1的光場分佈均勻化，並可降低發光元件的正向電壓。In one embodiment of the present application, when the light-emitting element 1 has the surrounding exposed region 15 and one or more hole exposed regions 17, when an external current is injected into the light-emitting element 1, the current is simultaneously conducted through the first conductive region 60a To the first semiconductor layer 101 in the surrounding exposed region 15 and the hole exposed region 17, by distributing one or more hole exposed regions 17, and surrounding the hole exposed region 17 with the surrounding exposed region 15, it is possible to The light field distribution of the light emitting element 1 is uniform, and the forward voltage of the light emitting element can be reduced.

於本申請案之一實施例中，當半導體疊層10不具有一或多個孔部暴露區17，第一導電區60a仍可藉由接觸環繞暴露區15內的第一半導體層101與其達成電性連接。當一外部電流注入發光元件1時，電流藉由第一導電區60a傳導至環繞暴露區15內的第一半導體層101，亦即電流的注入區域相當於環繞半導體疊層10，可使發光元件1的光場分佈均勻化，並可降低發光元件的正向電壓。In one embodiment of the present application, when the semiconductor stack 10 does not have one or more hole exposure regions 17, the first conductive region 60a can still be achieved by contacting the first semiconductor layer 101 in the surrounding exposure region 15. electrical connection. When an external current is injected into the light-emitting element 1, the current is conducted to the first semiconductor layer 101 in the surrounding exposed area 15 through the first conductive region 60a, that is, the injection region of the current is equivalent to surrounding the semiconductor stack 10, which can make the light-emitting element 1, the light field distribution is uniform, and the forward voltage of the light-emitting element can be reduced.

接續導電層形成步驟，如第7A圖之上視圖、第7B圖係為沿著第7A圖線段A-A’之剖面圖所示，發光元件1的製造方法包含一電極層30形成步驟。電極層30可藉由蒸鍍或沉積等方式於第一半導體層101及第二半導體層102上形成一導電材料層，再藉由微影、蝕刻之方式圖案化導電材料層以形成電極層30。如第7A圖所示，電極層30包含一電極墊30a、一由電極墊延伸出之環形電極層30b，以及一與電極墊30a和環形電極層30b在空間上皆相互分離之連接電極層30c。電極墊30a及環形電極層30b係沿著環繞暴露區15設置，其形狀大致上對應於環繞暴露區15。更詳言之，環形電極層30b形成於環繞暴露區15內的第一導電區60a上，並接觸第一導電區60a，亦即，由上視觀之，環形電極層30b接觸第一導電區60a的週圍；電極墊30a形成於區域S3上，並接觸區域S3的第一半導體層101。電極墊30a鄰近半導體疊層10之一側與第一導電區60a的邊緣接觸並重疊。如此一來，電極墊30a與環形電極層30b與第一半導體層101達成電性連接。於本實施例中，由上視觀之，電極墊30a為單一長條矩形並設置於基板11之一邊，電極墊30a與環形電極層30b構成一封閉圖案，此封閉圖案即對應環繞暴露區15。多個連接電極層30c對應形成於各第二導電區60b上，連接電極層30c之面積小於第二導電區60b之面積，且不超出各第二導電區60b範圍。電極層30之材料包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、或鉑(Pt)等金屬或上述材料之合金或疊層。Following the step of forming the conductive layer, as shown in the top view of FIG. 7A and the cross-sectional view along the line segment A-A' of FIG. 7A in FIG. 7B , the manufacturing method of the light-emitting element 1 includes a step of forming an electrode layer 30. The electrode layer 30 can form a conductive material layer on the first semiconductor layer 101 and the second semiconductor layer 102 by evaporation or deposition, and then pattern the conductive material layer by means of lithography and etching to form the electrode layer 30 . As shown in FIG. 7A, the electrode layer 30 includes an electrode pad 30a, an annular electrode layer 30b extending from the electrode pad, and a connecting electrode layer 30c that is spaced apart from the electrode pad 30a and the annular electrode layer 30b. . The electrode pads 30 a and the annular electrode layer 30 b are arranged along the surrounding exposed area 15 , and their shapes roughly correspond to the surrounding exposed area 15 . More specifically, the annular electrode layer 30b is formed on the first conductive region 60a surrounding the exposed region 15 and contacts the first conductive region 60a, that is, viewed from above, the annular electrode layer 30b contacts the first conductive region 60a; the electrode pad 30a is formed on the region S3 and contacts the first semiconductor layer 101 in the region S3. One side of the electrode pad 30 a adjacent to the semiconductor stack 10 contacts and overlaps the edge of the first conductive region 60 a. In this way, the electrode pad 30 a and the ring electrode layer 30 b are electrically connected to the first semiconductor layer 101 . In this embodiment, viewed from above, the electrode pad 30a is a single long rectangle and is arranged on one side of the substrate 11. The electrode pad 30a and the annular electrode layer 30b form a closed pattern, which corresponds to surrounding the exposed area 15 . A plurality of connection electrode layers 30c are correspondingly formed on each second conductive region 60b, and the area of the connection electrode layer 30c is smaller than that of the second conductive region 60b, and does not exceed the range of each second conductive region 60b. The material of the electrode layer 30 includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt). Such metals or alloys or laminates of the above materials.

於本申請案一實施例中，電極層30可包含一或多個電極墊30a，一或多個電極墊30a可設置於基板11之一或多個角落。In an embodiment of the present application, the electrode layer 30 may include one or more electrode pads 30 a, and the one or more electrode pads 30 a may be disposed on one or more corners of the substrate 11 .

於本申請案一實施例中，電極墊30a、環形電極層30b與連接電極層30c可同時形成，且電極墊30a、環形電極層30b與連接電極層30c具有相同材料。In an embodiment of the present application, the electrode pad 30a, the ring electrode layer 30b and the connection electrode layer 30c can be formed simultaneously, and the electrode pad 30a, the ring electrode layer 30b and the connection electrode layer 30c have the same material.

於本申請案一實施例中，可先形成電極墊30a與環形電極層30b，再形成連接電極層30c；亦可先形成連接電極層30c，再形成電極墊30a與環形電極層30b，且電極墊30a、環形電極層30b與連接電極層30c可具有不同材料。In an embodiment of the present application, the electrode pad 30a and the ring electrode layer 30b can be formed first, and then the connecting electrode layer 30c can be formed; the connecting electrode layer 30c can also be formed first, and then the electrode pad 30a and the ring electrode layer 30b can be formed, and the electrode The pad 30a, the ring electrode layer 30b and the connection electrode layer 30c may have different materials.

接續電極層形成步驟，發光元件1的製造方法包含一第三絕緣層70形成步驟，在第三絕緣層70形成步驟完成後，則形成如第8A圖之上視圖及第8B圖係為沿著第8A圖線段A-A’之剖面圖所示之疊層1’。第三絕緣層70可藉由蒸鍍或沉積等方式於疊層1’上形成一絕緣材料層，並覆蓋電極層30及導電層60，再藉由微影、蝕刻之方式圖案化絕緣材料層，以形成第三絕緣層70中的第一群組的第三絕緣層開口701。第一群組的第三絕緣層開口701對應形成於第二群組的第二絕緣層開口502與第二導電區60b上，以裸露出連接電極層30c與第二導電區60b。第一群組的第三絕緣層開口701之寬度不大於第二導電區60b之寬度，且不小於連接電極層30c之寬度，使得各連接電極層30c可藉由第一群組的第三絕緣層開口701完整裸露出。如同第二絕緣層50，第三絕緣層70可為單層或多層之構造。當第三絕緣層70為多層膜時，可包含不同折射率的兩種以上之材料交替堆疊以形成一布拉格反射鏡(DBR)結構，選擇性地反射特定波長之光。Following the step of forming the electrode layer, the manufacturing method of the light-emitting element 1 includes a step of forming the third insulating layer 70. After the step of forming the third insulating layer 70 is completed, the top view of FIG. 8A and the system of FIG. 8B are formed along the The laminated layer 1' shown in the sectional view of the line segment AA' in Fig. 8A. The third insulating layer 70 can form an insulating material layer on the stack 1' by evaporation or deposition, and cover the electrode layer 30 and the conductive layer 60, and then pattern the insulating material layer by means of lithography and etching. , to form a first group of third insulating layer openings 701 in the third insulating layer 70 . The first group of third insulating layer openings 701 are correspondingly formed on the second group of second insulating layer openings 502 and the second conductive region 60b to expose the connecting electrode layer 30c and the second conductive region 60b. The width of the third insulating layer opening 701 of the first group is not greater than the width of the second conductive region 60b, and is not smaller than the width of the connecting electrode layer 30c, so that each connecting electrode layer 30c can be insulated by the third insulating layer of the first group. The layer opening 701 is completely exposed. Like the second insulating layer 50, the third insulating layer 70 can be a single-layer or multi-layer structure. When the third insulating layer 70 is a multi-layer film, two or more materials with different refractive indices may be alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength.

於本申請案一實施例中，電極層可不具有連接電極層30c。當電極層30不具有連接電極層30c時，第一群組的第三絕緣層開口701裸露出各第二導電區60b。In an embodiment of the present application, the electrode layer may not have the connecting electrode layer 30c. When the electrode layer 30 does not have the connecting electrode layer 30c, the openings 701 of the third insulating layer of the first group expose the respective second conductive regions 60b.

接續第三絕緣層形成步驟，發光元件1的製造方法包含一接合步驟，如第9A圖與第9B圖之之剖面圖所示，形成一第一金屬層26a於第三絕緣層70上，接著形成一第一接合層28a於第一金屬層26a上；以及提供一導電基板12，形成一第二金屬層26b於導電基板12上，接著形成一第二接合層28b於第二金屬層26b上。於高於室溫之加熱溫度下，接合第一接合層28a及第二接合層28b，於本實施例中，加熱溫度低於200℃。其中導電基板12之材料可包含半導體材料例如矽(Si)，或金屬材料例如銅(Cu)、鉬(Mo)、鎢(W)或前述材料之合金或複合材料。第一金屬層26a材料包含具有較高熔點之金屬材料，例如鎳(Ni)、鈦(Ti)、銅(Cu)、金(Au)、鉑(Pt)、銠(Rh)。第二金屬層26b材料包含具有較低熔點之金屬材料，例如鎘(Cd)、錫(Sn)、銦(In)。於本申請案之一實施例中，所述具有較低熔點之金屬材料係指熔點低於200 ℃之金屬材料，例如銦(In)。所述具有較高熔點之金屬材料係指熔點高於200 ℃之金屬材料，例如鈦(Ti)、金(Au)。接合方式可倒置疊層1’於導電基板12上對位接合，或者倒置導電基板12於疊層1’上對位接合。當接合步驟完成後，第一金屬層26a、第一接合層28a、第二金屬層26b及第二接合層28b形成一接合結構28’，如第9B圖所示。接合結構28’填入第一群組的第三絕緣層開口701，與連接電極層30c及第二導電區60b接觸。如此一來，導電基板12經由第一群組的第三絕緣層開口701，與第二導電區60b及第二半導體層102達成電性連接。Following the step of forming the third insulating layer, the manufacturing method of the light-emitting element 1 includes a bonding step, as shown in the cross-sectional views of FIG. 9A and FIG. 9B, forming a first metal layer 26a on the third insulating layer 70, and then forming a first bonding layer 28a on the first metal layer 26a; and providing a conductive substrate 12, forming a second metal layer 26b on the conductive substrate 12, and then forming a second bonding layer 28b on the second metal layer 26b . The first bonding layer 28a and the second bonding layer 28b are bonded at a heating temperature higher than room temperature, and in this embodiment, the heating temperature is lower than 200°C. The material of the conductive substrate 12 may include semiconductor materials such as silicon (Si), or metal materials such as copper (Cu), molybdenum (Mo), tungsten (W), or alloys or composite materials of the aforementioned materials. The material of the first metal layer 26 a includes metal materials with relatively high melting points, such as nickel (Ni), titanium (Ti), copper (Cu), gold (Au), platinum (Pt), and rhodium (Rh). The material of the second metal layer 26b includes a metal material with a relatively low melting point, such as cadmium (Cd), tin (Sn), and indium (In). In an embodiment of the present application, the metal material with a lower melting point refers to a metal material with a melting point lower than 200° C., such as indium (In). The metal material with a higher melting point refers to a metal material with a melting point higher than 200° C., such as titanium (Ti) and gold (Au). The bonding method can be reversed laminated layer 1' and aligned on the conductive substrate 12, or inverted conductive substrate 12 is aligned and bonded on the laminated layer 1'. After the bonding step is completed, the first metal layer 26a, the first bonding layer 28a, the second metal layer 26b and the second bonding layer 28b form a bonding structure 28', as shown in FIG. 9B. The bonding structure 28' fills the first group of openings 701 of the third insulating layer, and contacts the connecting electrode layer 30c and the second conductive region 60b. In this way, the conductive substrate 12 is electrically connected to the second conductive region 60 b and the second semiconductor layer 102 through the first group of third insulating layer openings 701 .

於本申請案之一實施例中導電基板12之尺寸包含晶圓級基板或晶粒級基板。此處所指的晶圓不限於圓形，包含多邊形或不規則形狀。此處所指的晶圓，可於後續製程中分割成複數個晶粒等級的發光元件；亦可以不進行分割直接形成發光元件。In one embodiment of the present application, the size of the conductive substrate 12 includes a wafer-level substrate or a die-level substrate. The wafers referred to here are not limited to circular shapes, but include polygonal or irregular shapes. The wafer referred to here can be divided into a plurality of light-emitting elements at the grain level in subsequent manufacturing processes; light-emitting elements can also be directly formed without dividing.

當形成第一金屬層26a及第一接合層28a時，連接電極層30c可減緩因第三絕緣層70的厚度在第一群組的第三絕緣層開口701內所形成的高低落差，以提升接合的良率。於本申請案一實施例中，電極層30不具有連接電極層30c，第一金屬層26a填入第一群組的第三絕緣層開口701，與第二導電區60b接觸。當接合步驟完成後，導電基板12可同樣與第二導電區60b及第二半導體層102達成電性連接。When forming the first metal layer 26a and the first bonding layer 28a, the connection electrode layer 30c can alleviate the height difference formed in the third insulating layer opening 701 of the first group due to the thickness of the third insulating layer 70, so as to improve bonding yield. In an embodiment of the present application, the electrode layer 30 does not have the connecting electrode layer 30c, and the first metal layer 26a fills the first group of openings 701 of the third insulating layer and contacts the second conductive region 60b. After the bonding step is completed, the conductive substrate 12 can also be electrically connected to the second conductive region 60 b and the second semiconductor layer 102 .

於本申請案一實施例中，在第一金屬層26a之形成步驟中，可藉由分次在疊層1’上不同區域形成金屬材料來達成。例如，如第18圖所示，當疊層1’中各層結構之厚度差異太大時，特別是在環繞暴露區15之邊緣以及電極墊30a之鄰近區域，易發生第一金屬層26a高低落差大的問題；因此，可先在整個第三絕緣層70上形成一厚金屬材料261，接著在厚金屬材料261高低落差大之區域，再分次形成金屬材料262與263，以形成一較平坦之第一金屬層26a，提升接合步驟的良率。分次形成的金屬材料可為相同材料或不同材料。In one embodiment of the present application, in the step of forming the first metal layer 26a, it can be achieved by forming the metal material in different regions on the stack 1' in stages. For example, as shown in FIG. 18, when the thickness difference of each layer structure in the laminated layer 1' is too large, especially around the edge of the exposed area 15 and the adjacent area of the electrode pad 30a, the height difference of the first metal layer 26a is likely to occur. Therefore, a thick metal material 261 can be formed on the entire third insulating layer 70 first, and then metal materials 262 and 263 are formed in stages in the area where the thick metal material 261 has a large height difference to form a relatively flat surface. The first metal layer 26a improves the yield of the bonding step. The metallic materials formed in stages may be the same material or different materials.

接續接合步驟，發光元件1的製造方法包含一移除成長基板11步驟，如第10A圖之剖面圖所示，於本實施例中，疊層1’倒置接合於導電基板12後，接著利用例如雷射剝離(Laser Lift-Off)製程，自成長基板11的背面，即成長基板11遠離導電基板12之表面提供一雷射(圖未示)，以移除成長基板11並裸露出半導體疊層10之表面10s。Following the bonding step, the manufacturing method of the light-emitting element 1 includes a step of removing the growth substrate 11, as shown in the cross-sectional view of FIG. Laser lift-off (Laser Lift-Off) process, a laser (not shown) is provided from the back of the growth substrate 11, that is, the surface of the growth substrate 11 away from the conductive substrate 12, to remove the growth substrate 11 and expose the semiconductor stack 10 surface 10s.

於本申請案一實施例中，接續移除成長基板步驟，發光元件1的製造方法可包含一粗化步驟。如第10B圖之剖面圖所示，提供一蝕刻液對半導體疊層10的表面10s進行蝕刻，以在表面10s形成粗化結構TS，可增進發光元件之出光效率。粗化結構TS可以是規則或不規則的粗糙面。蝕刻液之材料可包含鹼性溶液，例如氫氧化鉀(KOH)或是氫氧化鈉(NaOH)。In an embodiment of the present application, following the step of removing the growth substrate, the manufacturing method of the light emitting device 1 may include a roughening step. As shown in the cross-sectional view of FIG. 10B , providing an etchant to etch the surface 10s of the semiconductor stack 10 to form a roughened structure TS on the surface 10s can improve the light extraction efficiency of the light emitting device. The roughening structure TS can be a regular or irregular rough surface. The material of the etchant may include an alkaline solution, such as potassium hydroxide (KOH) or sodium hydroxide (NaOH).

於本申請案一實施例中，在移除成長基板11後，可進一步利用乾式蝕刻、濕式蝕刻或兩者搭配來移除殘留在表面10s之緩衝層(圖未示)，再進行粗化步驟。In one embodiment of the present application, after the growth substrate 11 is removed, the buffer layer (not shown) remaining on the surface 10s can be further removed by dry etching, wet etching or a combination of the two, and then roughened step.

於本申請案一實施例中，在移除殘留在表面10s之緩衝層(圖未示)之同時，可藉由調整蝕刻的製程條件來形成粗化結構TS。In an embodiment of the present application, while removing the buffer layer (not shown) remaining on the surface 10s, the roughened structure TS can be formed by adjusting the etching process conditions.

接續粗化步驟，發光元件1的製造方法包含一打線墊36形成步驟。首先，如第11A圖之剖面圖所示，可在粗化步驟前或後，利用乾蝕刻及/或濕蝕刻之方式，由半導體疊層10之表面10s或粗化結構TS移除電極墊30a上方局部的第一半導體層101，使得電極墊30a裸露出來。此裸露區域可視為一非封閉式開口38，其形狀由上視觀之，大致上對應於電極墊30a。在非封閉式開口38未形成之前，環繞暴露區15內第一表面S1具有一寛度W1。W1大於非封閉式開口38之一寛度W2，因此環繞暴露區15及非封閉式開口38先後形成後，電極墊30a連接於第一表面S1側，且形成於環繞暴露區15中而與非封閉式開口38對應，電極墊30a並具有一寬度W3大於W2，由上視觀之，電極墊30a設置於發光元件1之一邊；當電極層30包含一或多個電極墊30a，電極墊30a可設置於發光元件1之一或多個角落。電極墊30a之上表面301具有一接觸區域301a連接第一半導體層101之第一表面S1，於一實施例中，接觸區域301a經由第一導電區60a連接於第一半導體層101之第一表面S1；於另一實施例中，接觸區域301a除了經由第一導電區60a電性連接於第一表面S1外，更可包含一區域直接連接第一半導體層101之第一表面S1；電極墊30a之上表面301另具有一被非封閉式開口38所暴露之暴露區域301b，與半導體疊層10不重疊。第一半導體層101之厚度可為3~4μm之間，可區分為第一部分101a與第二部分101b。第一部分101a之厚度與非封閉式開口38深度相當，約為1.5~3μm，第二部分101b之厚度對應環繞暴露區15，約為1~1.5μm。電極墊30a可電性連接於第一半導體層101但並非形成於出光面上，因此不會對發光元件1的光線產生遮光效應。Following the roughening step, the manufacturing method of the light-emitting device 1 includes a step of forming a bonding pad 36 . First, as shown in the cross-sectional view of FIG. 11A, the electrode pad 30a can be removed from the surface 10s of the semiconductor stack 10 or the roughened structure TS by dry etching and/or wet etching before or after the roughening step. The upper portion of the first semiconductor layer 101 exposes the electrode pad 30a. The exposed area can be regarded as a non-closed opening 38, and its shape is roughly corresponding to the electrode pad 30a viewed from above. Before the non-closed opening 38 is formed, the first surface S1 surrounding the exposed area 15 has a width W1. W1 is greater than the width W2 of the non-enclosed opening 38, so after the surrounding exposed area 15 and the non-enclosed opening 38 are successively formed, the electrode pad 30a is connected to the first surface S1 side, and is formed in the surrounding exposed area 15 instead of the non-enclosed opening 38. Corresponding to the closed opening 38, the electrode pad 30a has a width W3 greater than W2. Viewed from above, the electrode pad 30a is arranged on one side of the light emitting element 1; when the electrode layer 30 includes one or more electrode pads 30a, the electrode pad 30a It can be arranged in one or more corners of the light emitting element 1 . The upper surface 301 of the electrode pad 30a has a contact region 301a connected to the first surface S1 of the first semiconductor layer 101. In one embodiment, the contact region 301a is connected to the first surface of the first semiconductor layer 101 through the first conductive region 60a S1; in another embodiment, in addition to being electrically connected to the first surface S1 via the first conductive region 60a, the contact region 301a may further include a region directly connected to the first surface S1 of the first semiconductor layer 101; the electrode pad 30a The upper surface 301 also has an exposed region 301 b exposed by the non-closed opening 38 , which does not overlap with the semiconductor stack 10 . The thickness of the first semiconductor layer 101 can be between 3-4 μm, and can be divided into a first part 101a and a second part 101b. The thickness of the first part 101a is equivalent to the depth of the non-closed opening 38, which is about 1.5-3 μm, and the thickness of the second part 101b corresponds to surrounding the exposed area 15, which is about 1-1.5 μm. The electrode pad 30a can be electrically connected to the first semiconductor layer 101 but is not formed on the light-emitting surface, so it will not have a light-shielding effect on the light of the light-emitting element 1 .

於本申請案一實施例中，在移除電極墊30a上方局部的第一半導體層101以形成非封閉式開口38的同時，可進一步蝕刻移除其他部分的第一半導體層101，暴露出部分第三絕緣層70，做為後續切割步驟之切割道。藉由複數個切割道定義出各發光元件1的位置及尺寸。In one embodiment of the present application, while removing part of the first semiconductor layer 101 above the electrode pad 30a to form the non-closed opening 38, other parts of the first semiconductor layer 101 can be further etched away to expose a part The third insulating layer 70 is used as a cutting line for the subsequent cutting step. The position and size of each light-emitting element 1 are defined by a plurality of cutting lines.

接著，如第11B圖所示，在暴露區域301b上形成一打線墊36，打線墊36與相鄰的半導體疊層10之間具有一間隙而不直接接觸半導體疊層10。由上視觀之，打線墊36的形狀大致上與電極墊30a相同，打線墊36的寬度及面積小於電極墊30a的寬度及面積。在後續打線作業中，可將焊球(圖未示)設置於打線墊36上方，使發光元件1與外部電源或其他電子元件連接。Next, as shown in FIG. 11B , a bonding pad 36 is formed on the exposed region 301 b, and there is a gap between the bonding pad 36 and the adjacent semiconductor stack 10 without directly contacting the semiconductor stack 10 . Viewed from above, the shape of the bonding pad 36 is substantially the same as that of the electrode pad 30a, and the width and area of the bonding pad 36 are smaller than those of the electrode pad 30a. In the subsequent wire bonding operation, solder balls (not shown) can be placed on the wire bonding pad 36 to connect the light emitting element 1 to an external power source or other electronic components.

接續打線墊形成步驟，如第11B圖之剖面圖所示，發光元件1的製造方法包含一保護層80形成步驟。保護層80可藉由蒸鍍或沉積等方式形成於發光元件1上，覆蓋發光元件1相對於導電基板12之表面，再藉由微影、蝕刻之方式進行圖案化，以形成保護層開口801，裸露出打線墊36。保護層80覆蓋半導體疊層10之表面及側壁，並覆蓋打線墊36與半導體疊層10之間隙，可對發光元件1提供保護作用，避免外在環境的溫度、溼度及靜電等對發光元件1之效能產生不良影響。於本申請案一實施例中，導電基板12及半導體疊層10為晶圓級，在保護層80形成步驟後，可對晶圓級的導電基板12進行切割，切割步驟包含經由切割道對保護層80、導電基板12與接合結構28’進行切割，以形成複數個發光元件1。切割道是在上述非封閉式開口38形成步驟中，藉由蝕刻移除第一半導體層101而形成。切割方式包含切割刀或雷射切割。Following the step of forming the bonding pad, as shown in the cross-sectional view of FIG. 11B , the manufacturing method of the light-emitting device 1 includes a step of forming a protective layer 80 . The protective layer 80 can be formed on the light-emitting element 1 by evaporation or deposition, covering the surface of the light-emitting element 1 opposite to the conductive substrate 12, and then patterned by lithography and etching to form the protective layer opening 801 , the wiring pad 36 is exposed. The protective layer 80 covers the surface and side walls of the semiconductor stack 10, and covers the gap between the wiring pad 36 and the semiconductor stack 10, which can provide protection for the light-emitting element 1 and prevent the light-emitting element 1 from being affected by the temperature, humidity and static electricity of the external environment. adversely affect its performance. In one embodiment of the present application, the conductive substrate 12 and the semiconductor laminate 10 are at the wafer level. After the protective layer 80 is formed, the conductive substrate 12 at the wafer level can be cut. The layer 80 , the conductive substrate 12 and the bonding structure 28 ′ are cut to form a plurality of light emitting elements 1 . The dicing line is formed by removing the first semiconductor layer 101 by etching during the step of forming the non-closed opening 38 . Cutting methods include cutting knife or laser cutting.

第12圖為本申請案一實施例中所揭示之一發光元件1a之剖面圖，其與發光元件1之差異在保護層80形成步驟之後，可選擇性地形成一波長轉換層42在保護層80上，波長轉換層42可為螢光粉層或量子點材料，半導體疊層10所發出的光之波長可經由波長轉換層42轉換為不同波長的光。波長轉換層42形成步驟係於切割步驟之前完成。Figure 12 is a cross-sectional view of a light-emitting element 1a disclosed in an embodiment of the present application. The difference between it and the light-emitting element 1 is that after the formation of the protective layer 80, a wavelength conversion layer 42 can be selectively formed on the protective layer. 80 , the wavelength conversion layer 42 can be a phosphor layer or a quantum dot material, and the wavelength of light emitted by the semiconductor stack 10 can be converted into light of different wavelengths through the wavelength conversion layer 42 . The step of forming the wavelength conversion layer 42 is completed before the cutting step.

經本實施例製造方法所形成之發光元件1中，如第11B圖所示，當外部電流由打線墊36及導電基板12注入發光元件1時，電流首先傳遞至電極墊30a以及環型電極層30b，再經由第一導電區60a擴散開來，同時傳導至環繞暴露區15內與孔部暴露區17內的第一半導體層101。如此一來，電流可在半導體疊層10內均勻散佈，進而使得發光元件1的光場分佈均勻化，並可降低發光元件1的正向電壓。此外，第三絕緣層70可將電極墊30a與環型電極層30b絕緣於第二半導體層102及活性層103，且電極墊30a及環型電極層30b與活性層103位於發光元件1水平方向之不同區域，而由第11B圖觀之，半導體疊層10倒置於導電基板12上，因此活性層103整體位於反射結構16及第二導電區60b上方；打線墊36設置於非封閉式開口38中，對應於電極墊30a的位置，在發光元件1對應活性層103的出光面無設置任何的電極結構；因此活性層103所發出的光線不會被發光元件1之電極結構所遮蔽，提升發光效率。In the light-emitting element 1 formed by the manufacturing method of this embodiment, as shown in FIG. 11B, when an external current is injected into the light-emitting element 1 through the bonding pad 36 and the conductive substrate 12, the current is first transmitted to the electrode pad 30a and the ring-shaped electrode layer 30b , and then diffuse through the first conductive region 60a, and conduct to the first semiconductor layer 101 in the surrounding exposed region 15 and the hole exposed region 17 at the same time. In this way, the current can be evenly distributed in the semiconductor stack 10 , thereby making the light field distribution of the light emitting element 1 uniform and reducing the forward voltage of the light emitting element 1 . In addition, the third insulating layer 70 can insulate the electrode pad 30a and the ring-shaped electrode layer 30b from the second semiconductor layer 102 and the active layer 103, and the electrode pad 30a, the ring-shaped electrode layer 30b and the active layer 103 are located in the horizontal direction of the light emitting element 1 As seen from Figure 11B, the semiconductor stack 10 is placed upside down on the conductive substrate 12, so the active layer 103 is located above the reflective structure 16 and the second conductive region 60b as a whole; the bonding pad 36 is arranged on the non-closed opening 38 Among them, corresponding to the position of the electrode pad 30a, no electrode structure is provided on the light-emitting surface of the light-emitting element 1 corresponding to the active layer 103; therefore, the light emitted by the active layer 103 will not be blocked by the electrode structure of the light-emitting element 1, which improves the light emission. efficiency.

第17B係本申請案一實施例中所揭示之一發光元件2；第13A~第17B圖係本申請案發光元件2的製造方法。Fig. 17B is a light-emitting element 2 disclosed in an embodiment of the present application; Figs. 13A-17B are the manufacturing method of the light-emitting element 2 of the present application.

發光元件2的製造方法包含平台形成步驟、第一絕緣層20形成步驟、電流分散層18形成步驟以及反射結構16形成步驟。上述步驟與各層結構與前述發光元件1之製造方法中所述相同，因此不再贅述。The manufacturing method of the light-emitting element 2 includes the step of forming the platform, the step of forming the first insulating layer 20 , the step of forming the current spreading layer 18 and the step of forming the reflective structure 16 . The above steps and the structure of each layer are the same as those described in the aforementioned manufacturing method of the light-emitting element 1 , so they will not be repeated here.

如第13A之上視圖、第13B係為第13A圖沿著A-A’之剖面圖所示，發光元件2的製造方法在完成上述反射結構形成步驟後，包含一第二絕緣層50’形成步驟。第二絕緣層50’形成步驟與前述發光元件1之製造方法相似，差別在於，第二絕緣層50’更包含一第二絕緣層突出部503朝環繞暴露區15之區域E1延伸突出，形成於環繞暴露區15之第一表面S1上。多了兩個第二絕緣層突出部503的第二絕緣層50’所覆蓋環繞暴露區15之第一表面S1的面積，相較於無第二絕緣層突出部503的矩形輪廓的第二絕緣層覆蓋環繞暴露區15之第一表面S1的面積來得大。其中，環繞暴露區15之區域E1具有較寬的的寬度，其第一表面S1包含一區域S3，其表面未被第一絕緣層20及第二絕緣層50’所覆蓋。於本實施例中，半導體疊層10為一矩形，區域S3沿矩形之一邊設置。於本申請案另一實施例中，區域S3可位於矩形之一或多個角落。As shown in the top view of FIG. 13A, and FIG. 13B is a cross-sectional view along AA' of FIG. 13A, the manufacturing method of the light-emitting element 2 includes the formation of a second insulating layer 50' after completing the above-mentioned reflective structure forming steps. step. The steps for forming the second insulating layer 50' are similar to the manufacturing method of the aforementioned light-emitting element 1, the difference is that the second insulating layer 50' further includes a second insulating layer protrusion 503 extending toward the area E1 surrounding the exposed area 15, formed in on the first surface S1 surrounding the exposed region 15 . The area of the first surface S1 surrounding the exposed region 15 covered by the second insulating layer 50 ′ with two more second insulating layer protrusions 503 , compared to the second insulating layer without the second insulating layer protrusions 503 with a rectangular outline. The layer covers the area of the first surface S1 surrounding the exposed region 15 to be larger. Wherein, the region E1 surrounding the exposed region 15 has a wider width, and its first surface S1 includes a region S3, the surface of which is not covered by the first insulating layer 20 and the second insulating layer 50'. In this embodiment, the semiconductor stack 10 is a rectangle, and the region S3 is disposed along one side of the rectangle. In another embodiment of the present application, the region S3 may be located at one or more corners of the rectangle.

如同發光單元1之製造方法，其中在第二絕緣層50’圖案化的過程中，於前述第一絕緣層20形成步驟中，覆蓋於環繞暴露區15的第一絕緣層環繞區20a及孔部暴露區17內的第一絕緣層覆蓋區20b被部分蝕刻移除，以裸露出第一半導體層101之第一表面S1與第二表面S2，形成一第一群組的第二絕緣層開口501、第一絕緣層環繞區20a’及第一絕緣層覆蓋區20b’。第二絕緣層突出部503正下方的第一絕緣層環繞區20a’被保留，如第13B圖所示。As in the manufacturing method of the light-emitting unit 1, in the process of patterning the second insulating layer 50', in the aforementioned step of forming the first insulating layer 20, the surrounding area 20a and the hole of the first insulating layer covering the exposed area 15 The first insulating layer covering region 20b in the exposed region 17 is partially etched away to expose the first surface S1 and the second surface S2 of the first semiconductor layer 101, forming a first group of second insulating layer openings 501 , the first insulating layer surrounding region 20a' and the first insulating layer covering region 20b'. The surrounding region 20a' of the first insulating layer directly under the protruding portion 503 of the second insulating layer is retained, as shown in FIG. 13B.

接續第二絕緣層50’形成步驟，如第14A圖之上視圖、第14B圖係為沿著第14A圖線段A-A’之剖面圖所示，發光元件2的製造方法包含一導電層60’形成步驟。導電層60’形成步驟與前述發光元件1之製造方法相似，差別在於，如第14A圖所示，導電層60’包含第一導電區60a’、第二導電區60b’以及一第三導電區60d’，彼此藉由一縫隙60c’在空間上相互分離。在本實施例中，第一導電區60a’呈不連續的環型條狀圖案，包含環繞半導體疊層10三個側邊的U型條狀圖案以及鄰近環繞暴露區15中區域E1的直條狀圖案。第一導電區60a’接觸環繞暴露區15內的第一半導體層101(即第一表面S1)，與第一半導體層101電性連接，並覆蓋第二絕緣層50’的週圍，與第二半導體層102電性絕緣。第二導電區60b’位於第二半導體層102上方，覆蓋第二絕緣層50’上表面並填入各第二群組的第二絕緣層開口502，以接觸反射結構16，與第二半導體層102電性連接。其中，如第14A圖所示，第二導電區60b’包含一與第二絕緣層突出部503對應的第二導電區突出部603，第二導電區突出部603自第二導電區60’延伸出，覆蓋並接觸第二絕緣層突出部503，如此一來，第二導電區突出部603與第一表面S1之間具有第二絕緣層突出部503，因此第二導電區突出部603與第一半導體層101為電性絕緣。由上視觀之，除了第二導電區突出部603的區域以外，第二導電區60b’之邊緣不會超出第二半導體層102之範圍；在本實施例中，兩個第二導電區突出部603設置於第一導電區60a’的不連續處，即U型條狀圖案的第一導電區60a’與直條狀圖案的第一導電區60a’之間。第三導電區60d’對應孔部暴露區17，並經由第一群組的第二絕緣層開口501與第一半導體層101之第二表面S2接觸，與第一半導體層101電性連接，並覆蓋孔部暴露區17附近的第二絕緣層50’。導電層60’之材料與前述發光元件1的導電層60之材料相同，因此不再贅述。Following the step of forming the second insulating layer 50', as shown in the top view of FIG. 14A and the cross-sectional view along the line AA' of FIG. 14A in FIG. 14B, the manufacturing method of the light-emitting element 2 includes a conductive layer 60 'Formation step. The formation steps of the conductive layer 60' are similar to the manufacturing method of the aforementioned light-emitting element 1, the difference is that, as shown in FIG. 14A, the conductive layer 60' includes a first conductive region 60a', a second conductive region 60b' and a third conductive region 60d', which are spatially separated from each other by a gap 60c'. In this embodiment, the first conductive region 60a' is a discontinuous ring-shaped strip pattern, including a U-shaped strip pattern surrounding the three sides of the semiconductor stack 10 and a straight strip adjacent to the region E1 surrounding the exposed region 15. pattern. The first conductive region 60a' is in contact with the first semiconductor layer 101 (namely the first surface S1) in the surrounding exposed region 15, is electrically connected with the first semiconductor layer 101, and covers the periphery of the second insulating layer 50', and is connected with the second The semiconductor layer 102 is electrically insulated. The second conductive region 60b' is located above the second semiconductor layer 102, covers the upper surface of the second insulating layer 50' and fills the openings 502 of each second group of the second insulating layer to contact the reflective structure 16, and the second semiconductor layer. 102 is electrically connected. Wherein, as shown in FIG. 14A, the second conductive region 60b' includes a second conductive region protrusion 603 corresponding to the second insulating layer protrusion 503, and the second conductive region protrusion 603 extends from the second conductive region 60' out, covering and contacting the second insulating layer protruding portion 503, so that there is a second insulating layer protruding portion 503 between the second conductive region protruding portion 603 and the first surface S1, so the second conductive region protruding portion 603 and the first surface S1 A semiconductor layer 101 is electrically insulating. Viewed from above, except for the area of the protruding part 603 of the second conductive region, the edge of the second conductive region 60b' will not exceed the range of the second semiconductor layer 102; in this embodiment, the two second conductive regions protrude The portion 603 is disposed at a discontinuity of the first conductive region 60 a ′, that is, between the first conductive region 60 a ′ of the U-shaped strip pattern and the first conductive region 60 a ′ of the straight strip pattern. The third conductive region 60d' corresponds to the hole exposure region 17, and is in contact with the second surface S2 of the first semiconductor layer 101 through the first group of second insulating layer openings 501, electrically connected to the first semiconductor layer 101, and Covering the second insulating layer 50 ′ near the exposed region 17 of the hole. The material of the conductive layer 60' is the same as that of the conductive layer 60 of the aforementioned light-emitting element 1, so it will not be repeated here.

於本申請案之一實施例中，由上視觀之，導電層60’之面積大於所有活性層103之面積。In one embodiment of the present application, viewed from above, the area of the conductive layer 60' is larger than the area of all the active layers 103.

於本申請案之一實施例中，當發光元件2同時具有分散配置的孔部暴露區17以及環繞暴露區15圍繞孔部暴露區17的結構配置，當一外部電流注入發光元件2時，電流可藉由第一導電區60a’分別與環繞暴露區15內的第一半導體層101，以及孔部暴露區17內的第一半導體層101接觸形成多個電流注入區，可使注入電流均勻分散，進而降低發光元件2的正向電壓，並可使發光元件2的光場分佈均勻化。In one embodiment of the present application, when the light-emitting element 2 has the hole exposure area 17 in a dispersed arrangement and the structure configuration surrounding the hole exposure area 17 around the exposure area 15, when an external current is injected into the light-emitting element 2, the current A plurality of current injection regions can be formed by contacting the first conductive region 60a' with the first semiconductor layer 101 in the surrounding exposed region 15 and the first semiconductor layer 101 in the hole exposed region 17, so that the injection current can be uniformly dispersed , and further reduce the forward voltage of the light emitting element 2, and make the light field distribution of the light emitting element 2 uniform.

於本申請案之一實施例中，當半導體疊層10不具有一或多個孔部暴露區17，第一導電區60a’仍可藉由接觸環繞暴露區15內的第一半導體層101與其達成電性連接。當一外部電流注入發光元件1時，電流藉由第一導電區60a’傳導至環繞暴露區15內的第一半導體層101，亦即電流的注入區域相當於環繞半導體疊層10，可使發光元件2的光場分佈均勻化，並可降低發光元件2的正向電壓。In one embodiment of the present application, when the semiconductor stack 10 does not have one or more hole exposure regions 17, the first conductive region 60a' can still surround the first semiconductor layer 101 in the exposed region 15 and its achieve an electrical connection. When an external current is injected into the light-emitting element 1, the current is conducted to the first semiconductor layer 101 in the surrounding exposed region 15 through the first conductive region 60a', that is, the injection region of the current is equivalent to surrounding the semiconductor stack 10, which can make light The light field distribution of the element 2 is uniform, and the forward voltage of the light emitting element 2 can be reduced.

接續導電層形成步驟，如第15A圖之上視圖、第15B圖係為沿著第15A圖線段A-A’之剖面圖所示，發光元件2的製造方法包含一電極層30’形成步驟。電極層30’形成步驟與前述發光元件1之製造方法相似，差別在於，如第15A圖所示，電極層30’包含彼此在空間上皆為相互分離一電極墊30a’、一環形電極層30b’以及一連接電極層30c’。環形電極層30b’係沿著環繞暴露區15設置，形成於環繞暴露區15內的第一導電區60a’上，並接觸第一導電區60a’，亦即，由上視觀之，環形電極層30b’與第一導電區60a’同樣呈不連續的環型條狀圖案，包含環繞半導體疊層10三個側邊的U型條狀圖案以及鄰近環繞暴露區15中區域E1的直條狀圖案。環形電極層30b’之線寬小於第一導電區60a’之線寬。電極墊30a’形成於區域S3上，並接觸區域S3的第一半導體層101。電極墊30a’鄰近半導體疊層10之一側具有電極墊突出部303，與第二導電區突出部603之突出方向相對並與其重疊且接觸。於本實施例中，由上視觀之，電極墊30a’設置鄰近於環繞暴露區15中區域E1。多個連接電極層30c’對應形成於各第二導電區60d’上，連接電極層30c’之面積小於第二導電區60d’之面積，且不超出各第二導電區60d’範圍。電極層30’之材料包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、或鉑(Pt)等金屬或上述材料之合金或疊層。Following the step of forming the conductive layer, as shown in the top view of FIG. 15A and the cross-sectional view along the line A-A' of FIG. 15A in FIG. 15B , the manufacturing method of the light-emitting element 2 includes a step of forming an electrode layer 30'. The formation steps of the electrode layer 30' are similar to the manufacturing method of the aforementioned light-emitting element 1. The difference is that, as shown in FIG. 'and a connecting electrode layer 30c'. The ring electrode layer 30b' is arranged along the surrounding exposed area 15, formed on the first conductive area 60a' in the surrounding exposed area 15, and contacts the first conductive area 60a', that is, viewed from above, the ring electrode layer The layer 30b' and the first conductive region 60a' have the same discontinuous ring-shaped strip pattern, including a U-shaped strip pattern surrounding the three sides of the semiconductor stack 10 and a straight strip pattern adjacent to the region E1 surrounding the exposed region 15. pattern. The line width of the ring electrode layer 30b' is smaller than the line width of the first conductive region 60a'. The electrode pad 30a' is formed on the region S3 and contacts the first semiconductor layer 101 of the region S3. The side of the electrode pad 30a' adjacent to the semiconductor stack 10 has an electrode pad protrusion 303, which is opposite to, overlaps and contacts with the protrusion direction of the second conductive region protrusion 603. In this embodiment, viewed from above, the electrode pad 30a' is disposed adjacent to the area E1 in the surrounding exposed area 15. A plurality of connection electrode layers 30c' are correspondingly formed on each second conductive region 60d', and the area of the connection electrode layer 30c' is smaller than that of the second conductive region 60d' and does not exceed the range of each second conductive region 60d'. The material of the electrode layer 30' includes metal materials such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt ) and other metals or alloys or laminates of the above materials.

於本申請案一實施例中，電極層30’可包含一或多個電極墊30a’，一或多個電極墊30a’可設置於基板11之一或多個角落。In an embodiment of the present application, the electrode layer 30' may include one or more electrode pads 30a', and the one or more electrode pads 30a' may be disposed on one or more corners of the substrate 11.

於本申請案一實施例中，電極墊30a’、環形電極層30b’與連接電極層30c’可同時形成，且電極墊30a’、環形電極層30b’與連接電極層30c’具有相同材料。In an embodiment of the present application, the electrode pad 30a', the ring electrode layer 30b' and the connection electrode layer 30c' can be formed simultaneously, and the electrode pad 30a', the ring electrode layer 30b' and the connection electrode layer 30c' have the same material.

於本申請案一實施例中，可先形成電極墊30a’與環形電極層30b’，再形成連接電極層30c’；亦可先形成連接電極層30c’，再形成電極墊30a’與環形電極層30b’，且電極墊30a’、環形電極層30b’與連接電極層30c’可具有不同材料。In one embodiment of the present application, the electrode pad 30a' and the ring electrode layer 30b' can be formed first, and then the connecting electrode layer 30c' can be formed; the connecting electrode layer 30c' can also be formed first, and then the electrode pad 30a' and the ring electrode can be formed The layer 30b', and the electrode pad 30a', the annular electrode layer 30b' and the connecting electrode layer 30c' may have different materials.

接續電極層形成步驟，發光元件2的製造方法包含一第三絕緣層70’形成步驟。在第三絕緣層70’形成步驟完成後，則形成如第16A圖之上視圖、第16B圖係為沿著第16A圖線段A-A’之剖面圖所示之疊層2’，第三絕緣層70’形成步驟與前述發光元件1之製造方法相似，差別在於，如第16A圖所示，第三絕緣層70’包含相互分離的第一群組的第三絕緣層開口701’與第二群組的第三絕緣層開口702。第一群組的第三絕緣層開口701’對應形成於第一導電區60a’上，在本實施例中，由上視觀之，第一群組的第三絕緣層開口701’與第一導電區60a’同樣具有不連續的環型條狀圖案，且第一群組的第三絕緣層開口701’之開口寬度可小於第一導電區60a’之寬度，以裸露出部份第一導電區60a’與環型電極層30b’。於本申請案另一實施例中，第一群組的第三絕緣層開口701’可對應形成於環型電極層30b’上以裸露出環形電極層30b’；於本申請案另一實施例中，第一群組的第三絕緣層開口701’裸露出第一導電區60a’。第二群組的第三絕緣層開口702對應形成於孔部暴露區17上，裸露出部份第三導電區60d’與電極連接層30c’。Following the step of forming the electrode layer, the manufacturing method of the light emitting device 2 includes a step of forming a third insulating layer 70'. After the step of forming the third insulating layer 70' is completed, a stack 2' is formed as shown in the top view of Figure 16A, and Figure 16B is a cross-sectional view along the line AA' of Figure 16A. The formation steps of the insulating layer 70' are similar to the manufacturing method of the aforementioned light-emitting element 1, the difference is that, as shown in FIG. Two groups of openings 702 in the third insulating layer. The third insulating layer openings 701' of the first group are correspondingly formed on the first conductive region 60a'. The conductive region 60a' also has a discontinuous ring-shaped strip pattern, and the opening width of the third insulating layer opening 701' of the first group can be smaller than the width of the first conductive region 60a' to expose part of the first conductive region. Region 60a' and ring electrode layer 30b'. In another embodiment of the present application, the first group of openings 701' of the third insulating layer can be correspondingly formed on the annular electrode layer 30b' to expose the annular electrode layer 30b'; in another embodiment of the present application In the first group of openings 701' of the third insulating layer, the first conductive region 60a' is exposed. The third insulating layer openings 702 of the second group are correspondingly formed on the hole exposure area 17, exposing part of the third conductive area 60d' and the electrode connection layer 30c'.

於本申請案一實施例中，電極層30’可不具有連接電極層30c’。當電極層30’不具有連接電極層30c’時，第二群組的第三絕緣層開口702裸露出各第三導電區60d’。In an embodiment of the present application, the electrode layer 30' may not have the connecting electrode layer 30c'. When the electrode layer 30' does not have the connecting electrode layer 30c', the third insulating layer openings 702 of the second group expose each third conductive region 60d'.

接續第三絕緣層70’形成步驟，發光元件2的製造方法包含接合步驟、移除成長基板11步驟與粗化步驟。上述步驟與接合結構與前述發光元件1之製造方法中所述相同，因此不再贅述。於本申請案之一實施例中導電基板12之尺寸包含晶圓級基板或晶粒級基板。此處所指的晶圓不限於圓形，包含多邊形或不規則形狀。此處所指的晶圓，可於後續製程中分割成複數個晶粒等級的發光元件；亦可以不進行分割直接形成發光元件。當上述步驟完成後，如第17A圖所示，接合結構28’填入第一群組的第三絕緣層開口701’，與環型電極層30b’及/或第一導電區60a’接觸，以及填入第二群組的第三絕緣層開口702，與連接電極層30c’及/或第三導電區60d’接觸。如此一來，導電基板12與第一半導體層101達成電性連接。Following the step of forming the third insulating layer 70', the manufacturing method of the light-emitting device 2 includes a bonding step, a step of removing the growth substrate 11 and a roughening step. The above steps and bonding structure are the same as those described in the aforementioned manufacturing method of the light-emitting element 1 , and thus will not be repeated here. In one embodiment of the present application, the size of the conductive substrate 12 includes a wafer-level substrate or a die-level substrate. The wafers referred to here are not limited to circular shapes, but include polygonal or irregular shapes. The wafer referred to here can be divided into a plurality of light-emitting elements at the grain level in subsequent manufacturing processes; light-emitting elements can also be directly formed without dividing. After the above steps are completed, as shown in FIG. 17A, the bonding structure 28' fills the opening 701' of the third insulating layer of the first group, and contacts the ring electrode layer 30b' and/or the first conductive region 60a', And the third insulating layer opening 702 filled in the second group is in contact with the connecting electrode layer 30c' and/or the third conductive region 60d'. In this way, the conductive substrate 12 is electrically connected to the first semiconductor layer 101 .

其中當形成接合結構28’時，連接電極層30c’可減緩因第三絕緣層70’、導電層60’、第二絕緣層50’以及反射結構16的厚度在第二群組的第三絕緣層開口702所形成的高低落差，以提升接合的良率。於本申請案一實施例中，電極層30’不具有連接電極層30c’，接合結構28’填入第二群組的第三絕緣層開口702，與第三導電區60d’直接接觸。當接合步驟完成後，導電基板12同樣與第一半導體層101達成電性連接。Wherein when forming the bonding structure 28', the connecting electrode layer 30c' can slow down the third insulating layer in the second group due to the thickness of the third insulating layer 70', the conductive layer 60', the second insulating layer 50' and the reflective structure 16. The level difference formed by the layer opening 702 can improve the bonding yield. In an embodiment of the present application, the electrode layer 30' does not have the connecting electrode layer 30c', and the bonding structure 28' fills the opening 702 of the second group of the third insulating layer and directly contacts the third conductive region 60d'. After the bonding step is completed, the conductive substrate 12 is also electrically connected to the first semiconductor layer 101 .

如同前述發光元件1製造方法，於本申請案一實施例中，在發光元件2製造方法中第一金屬層26a之形成步驟，亦可藉由分次在疊層2’上不同區域形成金屬材料來達成。Like the above-mentioned manufacturing method of light-emitting element 1, in an embodiment of the present application, in the step of forming the first metal layer 26a in the manufacturing method of light-emitting element 2, the metal material can also be formed in different regions on the laminated layer 2' in stages to achieve.

如同前述發光元件1製造方法，於本申請案一實施例中，接合方式可倒置疊層2’於導電基板12上對位接合，或者倒置導電基板12於疊層2’上對位接合。Like the above-mentioned manufacturing method of the light-emitting element 1, in an embodiment of the present application, the bonding method can be inverting the laminated layer 2' for alignment bonding on the conductive substrate 12, or inverting the conductive substrate 12 for alignment bonding on the laminated layer 2'.

接續粗化步驟，如第17A圖之剖面圖所示，發光元件2的製造方法包含一打線墊36’形成步驟。首先，如同前述發光單元1製造方法，先形成非封閉式開口38，其形狀由上視觀之，大致上對應於電極墊30a’中電極墊突出部303以外的區域。在非封閉式開口38未形成之前，環繞暴露區15內第一表面S1具有一寛度W1。W1大於非封閉式開口38之一寛度W2，因此環繞暴露區15及非封閉式開口38先後形成後，電極墊30a’連接於第一表面S1，且形成於環繞暴露區15中而與非封閉式開口38對應，電極墊30a’在電極突出部303具有一寬度W3大於W2。電極墊突出部303直接接觸並連接第二導電區突出部603，與第二半導體層102電性連接；電極墊30a’之上表面301’具有一被非封閉式開口38所暴露之暴露區域301b’，與半導體疊層10不重疊。第一半導體層101之厚度可為3~4μm之間，可區分為第一部分101a與第二部分101b。第一部分101a之厚度與非封閉式開口38深度相當，約為1.5~3μm，第二部分101b之厚度對應環繞暴露區15，約為1~1.5μm。電極墊30a’可電性連接於第二半導體層102但並非形成於出光面上，因此不會對發光元件2的光線產生遮光效應。於本申請案一實施例中，電極層30’可包含一或多個電極墊30a’，一或多個電極墊30a’可設置於基板11之一或多個角落。Following the roughening step, as shown in the cross-sectional view of FIG. 17A, the manufacturing method of the light-emitting element 2 includes a step of forming a bonding pad 36'. Firstly, as in the method of manufacturing the aforementioned light-emitting unit 1, the non-closed opening 38 is first formed, and its shape, viewed from above, roughly corresponds to the area of the electrode pad 30a' other than the electrode pad protruding portion 303. Before the non-closed opening 38 is formed, the first surface S1 surrounding the exposed area 15 has a width W1. W1 is greater than the width W2 of the non-enclosed opening 38, so after the surrounding exposed area 15 and the non-enclosed opening 38 are successively formed, the electrode pad 30a' is connected to the first surface S1, and is formed in the surrounding exposed area 15 instead of the non-enclosed opening. Corresponding to the closed opening 38 , the electrode pad 30 a ′ has a width W3 greater than W2 at the electrode protrusion 303 . The electrode pad protrusion 303 directly contacts and connects the second conductive region protrusion 603, and is electrically connected to the second semiconductor layer 102; the upper surface 301' of the electrode pad 30a' has an exposed area 301b exposed by the non-closed opening 38 ', does not overlap with the semiconductor stack 10. The thickness of the first semiconductor layer 101 can be between 3-4 μm, and can be divided into a first part 101a and a second part 101b. The thickness of the first part 101a is equivalent to the depth of the non-closed opening 38, which is about 1.5-3 μm, and the thickness of the second part 101b corresponds to surrounding the exposed area 15, which is about 1-1.5 μm. The electrode pad 30a' can be electrically connected to the second semiconductor layer 102 but is not formed on the light-emitting surface, so it will not have a light-shielding effect on the light of the light-emitting element 2 . In an embodiment of the present application, the electrode layer 30' may include one or more electrode pads 30a', and the one or more electrode pads 30a' may be disposed on one or more corners of the substrate 11.

於本申請案一實施例中，在移除電極墊30a’上方局部的第一半導體層101以形成非封閉式開口38的同時，可進一步蝕刻移除其他部分的第一半導體層101，暴露出部分第三絕緣層70’，做為後續切割步驟之切割道。藉由複數個切割道定義出各發光元件2的位置及尺寸。In one embodiment of the present application, while removing part of the first semiconductor layer 101 above the electrode pad 30a' to form the non-closed opening 38, other parts of the first semiconductor layer 101 can be further etched away to expose Part of the third insulating layer 70' is used as a dicing line for the subsequent dicing step. The position and size of each light-emitting element 2 are defined by a plurality of cutting lines.

接著，如第17B圖所示，在暴露區域301b’上形成一打線墊36，打線墊36之結構、位置、功能與在發光元件1中所述相同，因此不再贅述。Next, as shown in FIG. 17B, a wire bonding pad 36 is formed on the exposed area 301b'. The structure, position, and function of the wire bonding pad 36 are the same as those described in the light-emitting element 1, so details will not be repeated.

接續打線墊36形成步驟，發光元件2製造方法同樣包含保護層80形成步驟，接續保護層80形成步驟，可對晶圓級的導電基板12進行切割，切割步驟包含經由切割道對保護層80、導電基板12與接合結構28’進行切割，以形成複數個發光元件2。切割道是在上述非封閉式開口38形成步驟中，藉由蝕刻移除第一半導體層101而形成。切割方式包含切割刀或雷射切割。此外，亦可在切割步驟之前，選擇性地形成波長轉換層42在保護層80上。Following the step of forming the bonding pad 36, the manufacturing method of the light-emitting element 2 also includes the step of forming the protective layer 80. Following the step of forming the protective layer 80, the conductive substrate 12 at the wafer level can be cut. The cutting step includes cutting the protective layer 80, The conductive substrate 12 and the bonding structure 28 ′ are cut to form a plurality of light emitting elements 2 . The dicing line is formed by removing the first semiconductor layer 101 by etching during the step of forming the non-closed opening 38 . Cutting methods include cutting knife or laser cutting. In addition, the wavelength conversion layer 42 can also be selectively formed on the protection layer 80 before the cutting step.

經本實施例製造方法所形成之發光元件2中，如第17B圖所示，當外部電流由打線墊36及導電基板12注入發光元件2時，電流首先傳遞至電極墊30a’，再經由電極墊突出部303與第二導電區突出部603的接觸，在第二導電區60b’擴散開來，傳導至第二半導體層102。此外，利用環型第一導電區60a’包圍配置在其中的第三導電區60d’，可使得電流同時傳導至環繞暴露區15內與孔部暴露區17內的第一半導體層101。如此一來，電流可在半導體疊層10內均勻散佈，進而使得發光元件2的光場分佈均勻化，並可降低發光元件2的正向電壓。第三絕緣層70’可將電極墊30a’與第二導電區60b’絕緣於第一半導體層102，且電極墊30a’及環型電極層30b’與活性層103位於發光元件2水平方向之不同區域，而由第17B圖觀之，半導體疊層10倒置於導電基板12上，因此活性層103整體位於反射結構16與第二導電區60b’之上方；打線墊36設置於非封閉式開口38中，對應於電極墊30a’的位置，在發光元件2對應活性層103的出光面無設置任何的電極結構；因此活性層103所發出的光線不會被發光元件2之電極結構所遮蔽，提升發光效率。In the light-emitting element 2 formed by the manufacturing method of this embodiment, as shown in FIG. 17B, when an external current is injected into the light-emitting element 2 from the bonding pad 36 and the conductive substrate 12, the current is first transmitted to the electrode pad 30a', and then passed through the electrode pad The contact between the protruding portion 303 and the protruding portion 603 in the second conductive region diffuses in the second conductive region 60 b ′ and conducts to the second semiconductor layer 102 . In addition, the ring-shaped first conductive region 60a' surrounds the third conductive region 60d' disposed therein, so that current can be conducted to the first semiconductor layer 101 in the surrounding exposed region 15 and in the hole exposed region 17 at the same time. In this way, the current can be evenly distributed in the semiconductor stack 10 , thereby making the light field distribution of the light emitting element 2 uniform, and reducing the forward voltage of the light emitting element 2 . The third insulating layer 70' can insulate the electrode pad 30a' and the second conductive region 60b' from the first semiconductor layer 102, and the electrode pad 30a', the ring electrode layer 30b' and the active layer 103 are located in the horizontal direction of the light emitting element 2. Different regions, and as viewed from FIG. 17B, the semiconductor stack 10 is placed upside down on the conductive substrate 12, so the active layer 103 is located above the reflective structure 16 and the second conductive region 60b' as a whole; the bonding pad 36 is arranged in the non-closed opening In 38, corresponding to the position of the electrode pad 30a', no electrode structure is provided on the light emitting surface of the light-emitting element 2 corresponding to the active layer 103; therefore, the light emitted by the active layer 103 will not be blocked by the electrode structure of the light-emitting element 2, Improve luminous efficiency.

惟上述實施例僅為例示性說明本申請案之原理及其功效，而非用於限制本申請案。任何本申請案所屬技術領域中具有通常知識者均可在不違背本申請案之技術原理及精神的情況下，對上述實施例進行修改及變化。因此本申請案之權利保護範圍如後述之申請專利範圍所列。However, the above-mentioned embodiments are only illustrative to illustrate the principles and functions of the present application, and are not intended to limit the present application. Anyone with ordinary knowledge in the technical field to which this application belongs can modify and change the above-mentioned embodiments without violating the technical principle and spirit of this application. Therefore, the scope of protection of the rights of this application is listed in the scope of patent application described later.

1、2:發光元件 1’、2’:疊層 10:半導體疊層 11:成長基板 12:導電基板 101:第一半導體層 102:第二半導體層 103:活性層 10s:半導體疊層之表面 15:環繞暴露區 16:反射結構 17:孔部暴露區 18:電流分散層 20:第一絕緣層 20a、20a’:第一絕緣層環繞區 20b、20b’:第一絕緣層覆蓋區 26a:第一金屬層 261、262、263:金屬材料 26b:第二金屬層 28a:第一接合層 28b:第二接合層 28’:接合結構 30、30’:電極層 30a、30a’:電極墊 30b、30b’:環形電極層 30c、30c’:連接電極層 301、301’:上表面 301a:接觸區域 301b、301b’:暴露區域 303:電極墊突出部 36:打線墊 38:開口 42:波長轉換層 50、50’:第二絕緣層 501:第一群組的第二絕緣層開口 502:第二群組的第二絕緣層開口 503:第二絕緣層突出部 60、60’:導電層 60a、60a’:第一導電區 60b、60b’:第二導電區 60c、60c’:縫隙 60d’:第三導電區 603:第二導電區突出部 70、70’:第三絕緣層 701、701’:第一群組的第三絕緣層開口 702:第二群組的第三絕緣層開口 80:保護層 S1:第一表面 S2:第二表面 S3:區域 E1:環繞暴露區之一區域 TS:粗化結構 1, 2: Light-emitting components 1', 2': Lamination 10: Semiconductor stack 11: Growth substrate 12: Conductive substrate 101: the first semiconductor layer 102: the second semiconductor layer 103: active layer 10s: The surface of the semiconductor stack 15: Surround the exposed area 16: Reflective structure 17: Hole exposed area 18: Current distribution layer 20: The first insulating layer 20a, 20a': first insulating layer surrounding area 20b, 20b': first insulating layer coverage area 26a: first metal layer 261, 262, 263: metal materials 26b: Second metal layer 28a: First bonding layer 28b: Second bonding layer 28':Joint structure 30, 30': electrode layer 30a, 30a': electrode pads 30b, 30b': ring electrode layer 30c, 30c': connect the electrode layer 301, 301': upper surface 301a: Contact area 301b, 301b': exposed area 303: electrode pad protrusion 36: Wire pad 38: opening 42:Wavelength conversion layer 50, 50': second insulating layer 501: openings in the second insulating layer of the first group 502: second insulating layer openings of the second group 503: second insulation layer protrusion 60, 60': conductive layer 60a, 60a': the first conductive region 60b, 60b': the second conductive region 60c, 60c': Gap 60d': the third conductive area 603: second conductive region protrusion 70, 70': the third insulating layer 701, 701': openings in the third insulating layer of the first group 702: openings in the third insulating layer of the second group 80: protective layer S1: first surface S2: second surface S3: area E1: Area surrounding one of the exposed areas TS: coarse structure

［第1A圖至第12圖］係本發明一實施例中所揭示之發光元件1的製造方法。 ［第13圖至第17B圖］係本發明一實施例中所揭示之發光元件2的製造方法。 ［第18圖］係本發明另一實施例中所揭示之發光元件1的製造方法。 [FIG. 1A to FIG. 12] is a manufacturing method of the light-emitting element 1 disclosed in an embodiment of the present invention. [Fig. 13 to Fig. 17B] are the manufacturing method of the light-emitting element 2 disclosed in one embodiment of the present invention. [Fig. 18] is a manufacturing method of the light-emitting element 1 disclosed in another embodiment of the present invention.

1:發光元件 1: Light emitting element

10:半導體疊層 10: Semiconductor stack

12:導電基板 12: Conductive substrate

15:環繞暴露區 15: Surround the exposed area

16:反射結構 16: Reflective structure

17:孔部暴露區 17: Hole exposed area

18:電流分散層 18: Current distribution layer

20’:第一絕緣層 20': first insulating layer

20a’:第一絕緣層環繞區 20a': Surrounding area of the first insulating layer

20b’:第一絕緣層覆蓋區 20b': first insulating layer coverage area

28’:接合結構 28':Joint structure

30:電極層 30: electrode layer

30a:電極墊 30a: electrode pad

30b:環形電極層 30b: ring electrode layer

30c:連接電極層 30c: connect the electrode layer

301b:暴露區域 301b: Exposed areas

36:打線墊 36: Wire pad

50:第二絕緣層 50: Second insulating layer

501:第一群組的第二絕緣層開口 501: openings in the second insulating layer of the first group

502:第二群組的第二絕緣層開口 502: second insulating layer openings of the second group

60:導電層 60: Conductive layer

70:第三絕緣層 70: The third insulating layer

701:第一群組的第三絕緣層開口 701: openings in the third insulating layer of the first group

S1:第一表面 S1: first surface

S2:第二表面 S2: second surface

TS:粗化結構 TS: coarse structure

Claims (10)

一發光元件，包含：一半導體疊層具有一第一半導體層，一第二半導體層，以及一活性層位於該第一半導體層及該第二半導體層之間；一或多個孔部暴露區，位於該半導體疊層內且穿過該第二半導體層及該活性層，暴露出該第一半導體層；一第一絕緣層，位於該半導體疊層上，包含一或多個第一開口對應位於該一或多個孔部暴露區上，及一或多個第二開口位於該第二半導體層上；一或多個第一導電層，位於該一或多個孔部暴露區上並延伸位於該第二半導體層上，且藉由該一或多個第一開口及該一或多個孔部暴露區與該第一半導體層電性連接；一或多個第二導電層，位於該第二半導體層上，藉由該一或多個第二開口與該第二半導體層電性連接；一接合層，位於該一或多個第一導電層及該一或多個第二導電層上；一電極層，位於該一或多個第一導電層及該接合層之間；一第二絕緣層，位於該一或多個第二導電層及該接合層之間；一導電基板，其中該半導體疊層位於該接合層之一側，該導電基板位於該接合層相對於該半導體疊層之另一側；一暴露區域，位於該發光元件之一邊或一角落，與該半導體疊層不重疊；以及一打線墊，位於該暴露區域上，電性連接於該一或多個第一導電層或該一或多個第二導電層。 A light-emitting element, comprising: a semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; one or more hole exposure regions , located in the semiconductor stack and passing through the second semiconductor layer and the active layer, exposing the first semiconductor layer; a first insulating layer, located on the semiconductor stack, including one or more first openings corresponding to Located on the one or more hole exposure areas, and one or more second openings are located on the second semiconductor layer; one or more first conductive layers are located on the one or more hole exposure areas and extend located on the second semiconductor layer, and electrically connected to the first semiconductor layer through the one or more first openings and the one or more hole exposed regions; one or more second conductive layers located on the The second semiconductor layer is electrically connected to the second semiconductor layer through the one or more second openings; a bonding layer is located on the one or more first conductive layers and the one or more second conductive layers On; an electrode layer, located between the one or more first conductive layers and the bonding layer; a second insulating layer, located between the one or more second conductive layers and the bonding layer; a conductive substrate, Wherein the semiconductor stack is located on one side of the junction layer, the conductive substrate is located on the other side of the junction layer relative to the semiconductor stack; an exposed area is located on one side or a corner of the light-emitting element, and the semiconductor stack non-overlapping; and a bonding pad, located on the exposed area, electrically connected to the one or more first conductive layers or the one or more second conductive layers. 如申請專利範圍第1項所述的發光元件，其中該電極層包含一第一連接電極層及一第二連接電極，該第一連接電極層對應形成於該一或多 個第一導電層上且電性連接該一或多個第一導電層，該第二連接電極層對應形成於該一或多個第二導電層上且電性連接該一或多個第二導電層。 The light-emitting element as described in item 1 of the scope of the patent application, wherein the electrode layer includes a first connection electrode layer and a second connection electrode, and the first connection electrode layer is correspondingly formed on the one or more on the first conductive layer and electrically connected to the one or more first conductive layers, the second connection electrode layer is formed on the one or more second conductive layers and electrically connected to the one or more second conductive layers conductive layer. 如申請專利範圍第2項所述的發光元件，其中該第一連接電極層或該第二連接電極層電性連接該接合層。 The light-emitting device as described in claim 2, wherein the first connecting electrode layer or the second connecting electrode layer is electrically connected to the bonding layer. 如申請專利範圍第2項所述的發光元件，其中該第一連接電極層之面積小於該一或多個第一導電層之面積。 The light-emitting device as described in claim 2, wherein the area of the first connection electrode layer is smaller than the area of the one or more first conductive layers. 如申請專利範圍第1項所述的發光元件，更包含一反射結構及/或電流分散層位於該第二半導體層上。 The light-emitting device described in item 1 of the patent claims further includes a reflective structure and/or a current spreading layer located on the second semiconductor layer. 如申請專利範圍第1項所述的發光元件，更包含一環形電極層鄰近該發光元件的一周圍。 The light-emitting element described in item 1 of the scope of the patent application further includes a ring-shaped electrode layer adjacent to a periphery of the light-emitting element. 如申請專利範圍第1項所述的發光元件，其中該一或多個第二導電層包含一第二導電層突出部超出該第二半導體層之邊緣，該打線墊藉由該第二導電層突出部與該第二半導體層電性連接。 The light-emitting device as described in item 1 of the scope of the patent application, wherein the one or more second conductive layers include a second conductive layer protruding beyond the edge of the second semiconductor layer, and the bonding pad is passed through the second conductive layer The protruding part is electrically connected with the second semiconductor layer. 如申請專利範圍第1項所述的發光元件，其中該一或多個第二導電層與該一或多個第一導電層在空間上相互分離。 The light-emitting device as described in claim 1, wherein the one or more second conductive layers and the one or more first conductive layers are spatially separated from each other. 如申請專利範圍第1項所述的發光元件，更包含一保護層覆蓋該半導體疊層相對於該導電基板之一表面，其中該保護層包含一保護層開口裸露出該打線墊。 The light-emitting device as described in item 1 of the scope of the patent application further includes a protective layer covering a surface of the semiconductor laminate opposite to the conductive substrate, wherein the protective layer includes an opening in the protective layer exposing the wiring pad. 如申請專利範圍第9項所述的發光元件，其中該保護層覆蓋該打線墊與該半導體疊層之一間隙。 The light-emitting device as described in claim 9 of the patent application, wherein the protection layer covers a gap between the wiring pad and the semiconductor stack.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150263230A1 (en) * 2011-05-16 2015-09-17 Kabushiki Kaisha Toshiba Semiconductor light emitting device
US20160211419A1 (en) * 2015-01-16 2016-07-21 Kabushiki Kaisha Toshiba Semiconductor light emitting element and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150263230A1 (en) * 2011-05-16 2015-09-17 Kabushiki Kaisha Toshiba Semiconductor light emitting device
US20160211419A1 (en) * 2015-01-16 2016-07-21 Kabushiki Kaisha Toshiba Semiconductor light emitting element and method of manufacturing the same

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