TWI898164B - Electronic device - Google Patents

Abstract

The present disclosure provides an electronic device, comprising: a substrate structure with a conductive via pattern and a dummy via pattern therein; a control unit electrically connected to the conductive via pattern; a first circuit structure electrically connected to the conductive via pattern; and an electronic unit electrically connected to the control unit through the first circuit structure, wherein the dummy via pattern is electrically insulated from the first circuit structure.

Description

electronic devices

The present invention relates to an electronic device, and more particularly to an electronic device including a dummy through-hole pattern.

As electronic device applications continue to advance, display technology is also evolving rapidly. However, facing varying manufacturing technology conditions, the requirements for the structure and quality of electronic devices are becoming increasingly stringent, posing unique challenges to the manufacturing of electronic devices.

In electronic component packaging technologies, fan-out wafer level packages (FOWLP) and fan-out panel level packages (FOPLP) form electronic components and a redistribution layer on a wafer-level or panel-level substrate, followed by packaging and dicing to create a large number of packaged components simultaneously. However, in these packages, the varying thickness of the film layers on both sides of the substrate can easily cause the substrate to warp due to uneven stress, impacting the yield of the electronic components.

In summary, while existing packaging structures generally meet their intended uses, they still don't fully meet all requirements. For example, how to create a packaging structure that meets electrical requirements while preventing uneven stress remains a research topic within the industry. Therefore, the development of electronic devices requires continuous updates and adjustments to address the various challenges facing their manufacturing.

An electronic device is characterized by comprising: a substrate structure having a conductive via pattern and a dummy via pattern; a control unit electrically connected to the conductive via pattern; a first circuit structure electrically connected to the conductive via pattern; and an electronic unit electrically connected to the control unit via the first circuit structure, wherein the dummy via pattern is electrically insulated from the first circuit structure.

A method for forming an electronic device comprises: forming a substrate structure having a conductive via pattern and a dummy via pattern; forming a control unit electrically connected to the conductive via pattern; forming a first circuit structure electrically connected to the conductive via pattern; and disposing an electronic unit on the first circuit structure, wherein the electronic unit is electrically connected to the control unit via the first circuit structure, wherein the dummy via pattern is electrically insulated from the first circuit structure.

The following disclosure provides many different embodiments or examples to illustrate different components of the embodiments of the present invention. Specific examples of the components of this specification and their arrangement will be disclosed below to simplify the description of this disclosure. Of course, these specific examples are not intended to limit the present disclosure. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which additional components can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in this disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, to facilitate describing the relationship of one element or component to another element or component in the drawings, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and similar terms may be used. Spatially relative terms encompass different orientations of the device during use or operation, in addition to those depicted in the drawings. When the device is oriented differently (for example, rotated 90 degrees or in other orientations), spatially relative adjectives are interpreted based on that orientation.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure.

Herein, the terms "about," "approximately," and "substantially" generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about," "approximately," or "substantially," the meaning of "about," "approximately," or "substantially" may still be implied.

It should be understood that the following embodiments may be implemented by replacing, combining, or reorganizing features from various embodiments without departing from the spirit of the present disclosure. Features from various embodiments may be arbitrarily combined and used together as long as they do not violate or conflict with the spirit of the invention.

The following describes some embodiments of the present invention. Additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages described may be replaced or eliminated in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described may be replaced or eliminated in different embodiments. Although some embodiments are discussed as performing the steps in a specific order, these steps may also be performed in another logical order.

As used herein, the term "substantially" means that a given amount of a value may vary based on a particular technology node associated with the target semiconductor device. In some embodiments, the term "substantially" may mean that a given amount of a value is within a range of, for example, ±10% of a target (or desired) value based on a particular technology node.

It should be understood that the electronic devices disclosed herein may include, but are not limited to, semiconductor devices, semiconductor package devices, display devices, sensor devices, antenna devices, radar devices, lidar devices, touch displays, curved displays, or free-form displays. The electronic devices may be bendable or flexible. The electronic devices may include, for example, but are not limited to, light-emitting diodes, liquid crystals, fluorescence, phosphors, other suitable display media, or combinations thereof. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a submillimeter light-emitting diode (mini LED), a micro-light-emitting diode (micro-LED), a quantum dot (QDs) light-emitting diode (such as a QLED or QDLED), other suitable materials, or any combination thereof, but is not limited thereto. The display device may include, for example, a tiled display device, but is not limited thereto. The concepts and principles disclosed herein may also be applied to non-luminescent liquid crystal displays (LCDs), but are not limited thereto.

The antenna device may be, for example, a 5G antenna, a Beyond-5G antenna, a 6G antenna, a liquid crystal antenna, a phased array antenna, a low-orbit satellite antenna, or other types of antennas, but is not limited thereto. The antenna device may, for example, include a spliced antenna device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but is not limited thereto. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device, or a spliced device. The electronic device disclosed herein may be, for example, a display device, but is not limited thereto.

The present disclosure provides an electronic device and a method for forming the same. By forming a virtual through-hole pattern in a substrate structure, the substrate structure can be prevented from warping due to uneven stress. Compared to the packaging structure of conventional electronic devices, the electronic device disclosed herein can maintain the stability of the substrate structure without affecting electrical requirements. The packaging structure formed by such an electronic device can enhance the functionality of the electronic unit through the through-hole structure and the control unit. In addition, the formation of a virtual through-hole structure that is electrically isolated from the circuit structure can be integrated into the manufacturing process of the conductive through-hole pattern. Therefore, the formation method disclosed herein can produce electronic devices with better electrical and structural performance, or eliminate the need for complex manufacturing steps, thereby saving manufacturing costs.

FIG1 is a schematic cross-sectional view of an electronic device 10 according to some embodiments of the present disclosure. The electronic device 10 includes a substrate structure 100, a control unit 110, a first circuit structure 120, and an electronic unit 130. The substrate structure 100 has a conductive via pattern 101 and a dummy via pattern 102. The control unit 110 is electrically connected to the conductive via pattern 101, the first circuit structure 120 is electrically connected to the conductive via pattern 101, and the electronic unit is electrically connected to the control unit 110 through the first circuit structure 120. The dummy via pattern 102 is electrically insulated from the first circuit structure 120. According to some embodiments, the electronic device 10 may include at least one control unit 110 and at least one electronic unit 130, and the number is not limited thereto.

As shown in FIG. 1 , substrate structure 100 may include substrate material 100M and conductive via pattern 101 and dummy via pattern 102 disposed within substrate material 100M. Substrate material 100M may include, but is not limited to, a hard or soft material such as glass, ceramic, polyimide (PI), polyethylene terephthalate (PET), steel, a silicon base, other suitable materials, or combinations thereof.

The substrate structure 100 may comprise a transparent or translucent material. For example, in some embodiments, the substrate structure 100 comprises a through-glass via (TGV) structure, which includes a substrate material 100M comprising an inorganic, amorphous glass material, with a conductive through-hole material disposed within the substrate material 100M. For example, a substrate structure 100 comprising a transparent or translucent material can be used for processing from the other side of a component to be processed, such as laser processing, and facilitates alignment of circuit structures and components on both sides, but is not limited to this. According to some embodiments, the substrate structure 100 may comprise an opaque substrate, enabling processing from the other side by providing alignment marks.

In some embodiments, conductive via pattern 101 includes a first conductive via 101A and a second conductive via 101B. As shown in FIG1 , first conductive via 101A can be electrically connected to control unit 110 through first circuit structure 120, and second conductive via 101B can be electrically connected to electronic unit 130 through a portion of first circuit structure 120 separated from control unit 110. However, the present disclosure is not limited to this. In other embodiments, control unit 110 and electronic unit 130 can be electrically connected to a common conductive via through first circuit structure 120.

By providing a dummy via pattern 102 in substrate structure 100, warping of substrate structure 100 due to uneven stress can be prevented. Compared to conventional electronic device packaging structures, electronic device 10 including dummy via pattern 102 can maintain the stability of substrate structure 100 without compromising the electrical performance of conductive via pattern 101. Although FIG. 1 depicts dummy via pattern 102 penetrating substrate material M, the present disclosure is not limited thereto. In some embodiments, dummy via pattern 102 is embedded within substrate material M, with the top or bottom surface of dummy via pattern 102 covered by substrate material M. It should be understood that the present disclosure does not specifically limit the number, cross-sectional shape, or horizontal position of the vias included in the dummy via pattern 102. For example, the conductive vias 101 may be I/Os (input/output points) of an electronic device. An uneven number of I/Os on a substrate can lead to uneven stress on the substrate, which in turn can cause warping. Therefore, elastically configuring the dummy via pattern 102 can be used to balance stress, but this is not a limitation.

The conductive via pattern 101 may be made of, for example, copper (Cu), tin (Sn), nickel (Ni), silver (Ag), gold (Au), titanium (Ti), molybdenum (Mo), tungsten (W), aluminum (Al), other suitable conductive materials, or combinations thereof, but is not limited thereto. The dummy via pattern 102 may be made of the same or similar material as the conductive via pattern 101, but the present disclosure is not limited thereto. In some embodiments, at least a portion of the dummy via pattern 102 comprises an insulating material. For example, this can reduce parasitic capacitance or electrical interference with nearby conductive via pattern 101 or circuit structures, but is not limited thereto.

The control unit 110 can be an element for controlling the electronic unit 130, such as a control element including a transistor. In some embodiments, the control unit 110 can be a thin film transistor (TFT) element. The control element 110 can include a semiconductor layer 112, a gate 114, and a source/drain 116. It should be noted that the present disclosure does not limit the form of the control unit 110. For example, the control unit 110 can have a top-gated gate, a bottom-gated gate, or other suitable forms, but is not limited thereto. In some embodiments, as shown in FIG. 1 , the control element 110 can be located above the substrate structure 100, and the control unit can be located between the substrate structure 100 and the first circuit structure 120. Furthermore, the semiconductor layer 112, the gate 114, and the source/drain 116 may be fully or partially embedded in the first insulating layer 106 and the second insulating layer 108. In some embodiments, as shown in FIG. 1 , the top surface of the source/drain 116 is exposed above the second insulating layer 108.

The material of the semiconductor layer 112 may include, but is not limited to, amorphous silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), other suitable semiconductor materials, or combinations thereof. The material of the gate 114 may include, but is not limited to, Al, Ti, Mo, W, other suitable conductive materials, or combinations thereof. The material of the source/drain 116 may include, but is not limited to, Al, Ti, Mo, W, other suitable conductive materials, or combinations thereof. In some embodiments, the first insulating layer 106 and the second insulating layer 108 may include the same or similar materials. The materials of the first insulating layer 106 and the second insulating layer 108 may include, but are not limited to, silicon nitride ( _SiNx ), silicon oxide ( _SiOx ), silicon oxynitride ( _SiOxNy ), aluminum oxide ( _AlxOy ), other suitable insulating materials, or combinations thereof. _In some embodiments, the thickness of the first insulating layer 106 and the second insulating layer 108 is greater than or equal to 500 nanometers (nm) and less than or equal to ₅₀₀₀ nanometers.

In some embodiments, electronic device 10 further includes a buffer layer 104 disposed between substrate structure 100 and control element 110. As shown in FIG1 , buffer layer 104 may cover the top surface of dummy via pattern 102. Because materials (e.g., copper) within conductive via pattern 101 may diffuse into control element 110 at high temperatures, buffer layer 104 can substantially block diffusion of such materials during high-temperature manufacturing processes, thereby preventing contamination of control element 110. In some embodiments, buffer layer 104 has a thickness between approximately 400 nanometers (nm) and approximately 1500 nanometers (nm) to achieve this purpose. In some embodiments, as shown in FIG1 , the first circuit structure 120 penetrates the buffer layer 104 to be electrically connected to the conductive via pattern 101. The material of the buffer layer 104 may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable insulating materials, or a combination thereof, but is not limited thereto.

In some embodiments, the electronic device 10 further includes a stress-adjusting layer 105 disposed on the substrate structure 100 and located on a side of the substrate structure 100 opposite the control unit 110. As shown in FIG1 , the stress-adjusting layer 105 may cover the bottom surface of the dummy via pattern 102. By disposing the stress-adjusting layer 105 on the substrate structure 100, stress balance can be maintained on the substrate structure 100 during deposition of components on the other side of the substrate structure 100 (e.g., the control unit 110, the first circuit structure 120, and the electronic unit 130), thereby preventing warping of the substrate structure 100. In some embodiments, the thermal expansion coefficient of the stress-adjusting layer 105 is similar to that of the insulating layers on the other side of the substrate structure 100, such as the buffer layer 104, the first insulating layer 106, and the second insulating layer 108. The stress-adjusting layer 105 may be made of, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable insulating materials, or combinations thereof. The thickness of the stress-adjusting layer 105 may be between 800 nanometers and approximately 3000 nanometers.

Referring to FIG. 1 , first circuit structure 120 is surrounded by a first dielectric layer 122. First circuit structure 120 may be made of materials similar to those of conductive via pattern 101, such as, but not limited to, Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or combinations thereof. First dielectric layer 122 may be made of, but not limited to, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto Build-up Film (ABF), epoxy resin, other suitable dielectric materials, or combinations thereof.

In some embodiments, the electronic device 10 further includes an alignment component 124 disposed on the first circuit structure 120 and electrically connected to the electronic unit 130. As shown in FIG1 , the alignment component 124 may have a groove facing the electronic unit 130. The alignment component 124 can be used to align the electronic unit 130 to a specified position above the first circuit structure 120. In addition, by increasing the side stress that the electronic unit 130 can withstand, the groove of the alignment component 124 can be used to strengthen the bonding strength between the first circuit structure 120 and the electronic unit 130. The alignment component 124 may include a material similar to that of the first circuit structure 120, but is not limited thereto. According to some embodiments, the alignment component 124 may be, for example, a conductive bump (under bump metallization, UBM), but is not limited thereto.

The electronic unit 130 and the first circuit structure 120 can be electrically connected via a bonding material 134. In some embodiments, as shown in FIG. 1 , the bonding material 134 is disposed on the alignment feature 124 on the first circuit structure 120, and the electronic unit 130 having the electrical connection portion 132 is disposed on the bonding material 134. In some embodiments, a diffusion region 136 is defined between the electrical connection portion 132 and the bonding material 134, and the diffusion region 136 includes elements from both the electrical connection portion 132 and the bonding material 134.

The bonding material 134 may include, but is not limited to, Au, Sn, Al, Cu, Ti, Ag, Ga, other suitable metals, or combinations thereof. In some embodiments, the bonding material 134 comprises a mixture of particles of the aforementioned metals and an organic material. The electrical connection portion 132 may include, but is not limited to, Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or combinations thereof.

Depending on the application of the electronic device 10, the electronic unit 130 can be a variety of components. For example, the electronic unit 130 can be a chip, a die, an integrated circuit, a diode, a capacitor, a resistor, an inductor, a sensor, other suitable components, or a combination thereof, but is not limited thereto. The electronic device 10 further includes a protective layer 140 surrounding the electronic unit 130. For example, the protective layer 140 can prevent moisture from affecting the electronic unit 130 or the circuit structure. According to some embodiments, the protective layer 140 can contact at least two sides of the electronic unit 130. According to some embodiments, at least one surface of the electronic unit 130 can be exposed and not contacted by the protective layer. The material of the protective layer 140 may include silicone, epoxy, acrylic, other suitable materials, or a combination thereof, but is not limited thereto.

According to some embodiments, the protective layer 140 may contact a side surface 122SS of the insulating layer 122. The protective layer 140 may also contact a top surface 108TS of the insulating layer 108. The above configuration can enhance the bonding capability between different film layers, thereby improving the reliability of the electronic device, but is not limited thereto.

In some embodiments, the electronic device 10 further includes a second circuit structure 150 disposed on the substrate structure 100 and opposite the first circuit structure 120. In some embodiments, the dummy via pattern 102 is electrically isolated from the second circuit structure 150. As shown in FIG. 1 , for example, the dummy via pattern 102 and the second circuit structure 150 may be separated by a stress-adjusting layer 105. In some embodiments, the second circuit structure 150 penetrates the stress-adjusting layer 105 to electrically connect to the conductive via pattern 101. In some embodiments, the first circuit structure 120 and the second circuit structure 150 are electrically connected through the conductive via pattern 101. In some embodiments, the second circuit structure 150 is surrounded by a second dielectric layer 152. The second dielectric layer 152 may include a material similar to that of the first dielectric layer 122, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, ABF, other suitable dielectric materials, or combinations thereof, but is not limited thereto.

In some embodiments, the electronic device 10 further includes an alignment member 154 disposed on the second circuit structure 150. As shown in FIG1 , the alignment member 154 may have a groove facing away from the substrate structure 100. The alignment member 154 can be used to align the electronic device 10 to a specified position of an external circuit. In addition, the groove of the alignment member 154 can be used to strengthen the bonding strength between the electronic device 10 and the external circuit. The alignment member 154 may include a material similar to the alignment member 124 or the second circuit structure 150, but is not limited thereto. In some embodiments, as shown in FIG1 , a bonding material 156 is provided on the alignment member 154 on the second circuit structure 150, and the bonding material 156 can be used to bond the electronic device 10 to the external circuit. The external circuits may include printed circuit boards (PCBs) or flexible printed circuits (FPCs). For example, the first circuit structure 120 and the second circuit structure 150 may be redistribution layers (RDLs). By designing the RDLs, I/O can be flexibly designed or the fan-out range of the circuit structure can be increased. According to some embodiments, the alignment component 124 or the alignment component 154 may have a convex, flat, concave, or curved surface, but is not limited thereto. According to some embodiments, the surface of the alignment component 124 may be coplanar with or different from the surface of the dielectric layer 122. Specifically, the surface of the alignment component 124 may be higher than the surface of the dielectric layer 122, or the surface of the alignment component 124 may be lower than the surface of the dielectric layer 122. According to some embodiments, the surface of the alignment member 154 may be coplanar with or different from the surface of the dielectric layer 152. Specifically, the surface of the alignment member 154 may be higher than the surface of the dielectric layer 152 or lower than the surface of the dielectric layer 152.

FIG2 is a cross-sectional view of an electronic device array 20′ according to some embodiments of the present disclosure. FIG2 shows an electronic device array 20′ including two electronic devices 20, each of which includes an electronic unit 130 and its corresponding first circuit structure 120, a control unit 110, and a second circuit structure 150. In practice, the present disclosure does not limit the number of electronic devices 20 included in the electronic device array 20′ or the configuration of each electronic device 20. For example, the electronic devices 20 may have a configuration similar to the electronic device 10 described with reference to FIG1, or may have a configuration in which the control unit 110 and the electronic unit 130 are located on opposite sides of the substrate structure 100 (as shown in FIG3). Furthermore, depending on the design requirements of electronic device array 20', each electronic unit 130 can be the same, similar, or different types of components, which is not limited by the present disclosure. In some embodiments, the circuit structures of adjacent electronic devices 20 are connected by conductive lines. Similar components shown in Figures 1 and 2 are represented by the same or similar reference numerals and may be formed of the same or similar materials and configurations. For the sake of simplicity, their detailed description is omitted here.

FIG3 illustrates a cross-sectional view of an electronic device 30 according to some other embodiments of the present disclosure. Unlike the electronic device 10 shown in FIG1 , the control unit 110 and the electronic unit 130 of the electronic device 30 are located on opposite sides of the substrate structure 100. Specifically, as shown in FIG3 , the control unit 110 is located below the substrate structure 100, and the substrate structure 100 is located between the control unit 110 and the first circuit structure 120. For example, this arrangement can prevent the control unit 110 from interfering with the electronic unit 130 during operation, but is not limited thereto.

Furthermore, in the embodiment shown in FIG3 , since the buffer layer 104 is disposed between the substrate structure 100 and the control unit 110, the buffer layer is also located below the substrate structure 100. The stress adjustment layer 105 can be disposed on the side of the substrate structure 100 opposite the control unit 110, such that the stress adjustment layer 105 is located between the substrate structure 100 and the electronic unit 130. Similar components shown in FIG1 and FIG3 are denoted by the same or similar reference numerals and may be formed using the same or similar materials and configurations. For the sake of simplicity, their detailed description is omitted here.

FIG4 is a cross-sectional view of an electronic device 40 according to some other embodiments of the present disclosure. The difference from the electronic device 10 shown in FIG1 is that a conductive material 160 is disposed between the substrate structure 100 and the first circuit structure 120 of the electronic device 40. The substrate structure 100 and the first circuit structure 120 of the electronic device 40 are electrically connected via the conductive material 160. The conductive material 160 may include a material similar to that of the first circuit structure 120 and the second circuit structure 150, but is not limited thereto. Furthermore, similar components shown in FIG1 and FIG4 are denoted by the same or similar reference numerals and may be formed using the same or similar materials and configurations, and their detailed description is omitted for simplicity. By forming such an electronic device 40 , the complexity of the manufacturing process, which originally required forming the first circuit structure 120 and the second circuit structure 150 on the upper and lower sides of the substrate structure 100 , respectively, can be reduced.

5A to 5F are cross-sectional views illustrating various stages in the manufacturing process of an electronic device according to some embodiments of the present disclosure.

5A , a substrate structure 100 is first formed having a conductive via pattern 101 and a dummy via pattern 102. In some embodiments, a removal process is used to form a plurality of through holes in the substrate material 100M, and then materials for the conductive via pattern 101 and the dummy via pattern 102 are deposited in the through holes.

The removal process may include, but is not limited to, laser processing, a suitable etching process, or a combination thereof. In embodiments where the substrate material 100M is thicker, laser processing may be performed on both sides of the substrate material 100M to form through-holes with larger diameters at the top and bottom and a smaller diameter in the middle. In this case, the resulting conductive via pattern 101 and dummy via pattern 102 have larger diameters at the top and bottom and a smaller diameter in the middle, as shown in FIG. 5A .

The process for depositing the conductive via pattern 101 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof, but is not limited thereto. In some embodiments, the formation of the conductive via pattern 101 includes first depositing a seed layer in the through hole, and then depositing a conductive material on the seed layer. The material of the seed layer includes, but is not limited to, titanium (Ti), copper (Cu), other suitable conductive materials, or combinations thereof. The conductive material includes, for example, Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or combinations thereof, but is not limited thereto.

The process used to deposit dummy via pattern 102 may include, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof. In some embodiments, conductive via pattern 101 and dummy via pattern 102 are formed simultaneously in a single deposition process. Alternatively, dummy via pattern 102 may be formed in a different deposition process than conductive via pattern 101, and may comprise a different material than conductive via pattern 101.

Next, as shown in FIG. 5A , a buffer layer 104 can be formed on substrate structure 100 to cover the top surface of dummy via pattern 102 before forming the control unit. This prevents diffusion of material from conductive via pattern 101 into control element 110 during subsequent high-temperature processes. Furthermore, a stress adjustment layer 105 can be formed on substrate structure 100 on a side opposite to buffer layer 104. Stress adjustment layer 105 is thicker than buffer layer 104.

The process used to deposit the buffer layer 104 may include, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. The process used to deposit the stress adjustment layer 105 may be similar to that used to deposit the buffer layer 104, including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof.

Then, a control unit 110 is formed that is electrically connected to the conductive via pattern 101. Referring to Figures 5A and 5B, a semiconductor layer 112 of the control unit 110 can first be formed above the substrate structure 100, for example, on the buffer layer 104. In an embodiment where the control unit 110 is a transistor, the semiconductor layer 112 may include a channel layer. The formation of the semiconductor layer 112 may include a deposition process and a patterning process. The deposition process may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto. The patterning process includes a suitable lithography and/or etching process. The lithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying) and/or hard baking, other suitable lithography techniques, or combinations thereof. The etching process may include, but is not limited to, dry etching (e.g., RIE etching), wet etching, other etching methods, or combinations thereof.

Next, a first insulating layer 106 may be formed on the semiconductor layer 112. The process used to form the first insulating layer 106 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto. Next, a gate 114 and a source/drain 116 may be formed on the first insulating layer 106. The process used to form the gate 114 and the source/drain 116 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or a combination thereof, but is not limited thereto. Between the formation of the gate 114 and the source/drain 116, a second insulating layer 108 may be formed on the first insulating layer 106 and the gate 114. In some embodiments, a portion of the first insulating layer 106 and the second insulating layer 108 are removed by an etching process to expose the semiconductor layer 112. A conductive material for the source/drain 116 is then deposited in the openings left by the removal of the first insulating layer 106 and the second insulating layer 108. The second insulating layer 108 may be formed using a deposition process similar to that of the first insulating layer 106, which is not described in detail here for simplicity.

It should be understood that the present disclosure does not limit the order in which the various components of the control element 110 (e.g., the semiconductor layer 112, the gate 114, and the source/drain 116) and the various insulating layers (e.g., the first insulating layer 106 and the second insulating layer 108) are formed. A person skilled in the art can adjust the order in which these layers are formed based on process requirements. Furthermore, it should be understood that the present disclosure does not limit when the stress-adjusting layer 105 is formed. A person skilled in the art can form the stress-adjusting layer 105 before, during, or after the formation of the control unit 110, based on process requirements.

Next, referring to FIG. 5C , a first circuit structure 120 electrically connected to the conductive via pattern 101 can be formed, while the dummy via pattern 102 is electrically isolated from the first circuit structure 120. Before, during, or after the formation of the first circuit structure 120, a dielectric material can be deposited to form a first dielectric layer 122 surrounding the first circuit structure 120. The process used to deposit the first circuit structure 120 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof, but is not limited thereto. The process for forming the first dielectric layer 122 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto.

As shown in FIG. 5C , to dispose electronic component 130 on first circuit structure 120, an alignment feature 124 having a recess facing away from first circuit structure 120 may be formed on first circuit structure 120. Alignment feature 124 may be formed by forming an opening in first dielectric layer 122 to expose first circuit structure 120 and forming a conductive material in the opening. Formation of alignment feature 124 may include a deposition process and a patterning process.

The deposition process for the alignment feature 124 may include, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. The patterning process for the alignment feature 124 may include suitable lithography and/or etching processes. The lithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying) and/or hard baking, other suitable lithography techniques, or combinations thereof. The etching process may include, but is not limited to, dry etching (e.g., RIE etching), wet etching, other etching methods, or combinations thereof. In some embodiments, the formed alignment feature 124 may have a top portion higher than the top surface of the first dielectric layer 122.

Next, referring to FIG. 5D , electronic unit 130 is disposed on first circuit structure 120, and electronic unit 130 is electrically connected to control unit 110 via first circuit structure 120. Disposing electronic unit 130 may include aligning any portion of electronic unit 130 with alignment member 124. For example, in some embodiments, alignment member 124 is aligned with electrical connection portion 132 of electronic unit 130. A heating step may then be performed to bond alignment member 124 and electrical connection portion 132 via bonding material 134. After disposing electronic unit 130, protective layer 140 may be formed around electronic unit 130. The process for forming the protective layer 140 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto.

In some embodiments, the control unit 110 is formed after the electronic unit 130 and the protective layer 140 are formed. More specifically, the protective layer 140 surrounding the electronic unit 130 can be formed in an electronic device before the control unit 110 is formed. The entire electronic device is then flipped over and the control unit 110 is formed on the other side of the substrate structure 100. In this way, an electronic device 30 similar to that shown in FIG. 3 can be formed, in which the substrate structure 100 is located between the electronic unit 130 and the control unit 110. This design can prevent the control unit 110 from interfering with the electronic unit 130 during operation, but is not limited to this.

In some embodiments, before forming the control element 110, the first circuit structure 120, and the electronic unit 130, a conductive material 160 electrically connected to the conductive via pattern 101 is formed on the substrate structure 100. In this case, a protective layer 140 surrounding the electronic unit 130 can be formed first, and then the first circuit structure 120 is bonded to the conductive via pattern 101 of the substrate structure 100 using the conductive material 160. In this way, an electronic device 40 including the conductive material 160, similar to that shown in FIG. 4, can be formed. Through the above design, the complexity of the process of forming the first circuit structure 120 and the second circuit structure 150 on the upper and lower sides of the substrate structure 100, respectively, can be reduced, but the present invention is not limited to this.

5E , the formation of the electronic device may further include forming a second circuit structure 150 on the substrate structure 100, opposite the first circuit structure 120, with the dummy via pattern 102 electrically isolated from the second circuit structure 150. Before, during, or after the formation of the second circuit structure 150, a dielectric material may be deposited to form a second dielectric layer 152 surrounding the second circuit structure 150. The process for depositing the second circuit structure 150 may be similar to that for the first circuit structure 120 and is not further described herein for simplicity. The process for depositing the second dielectric layer 152 may be similar to that for the first dielectric layer 122 and is not further described herein for simplicity.

As shown in FIG. 5E , an alignment feature 154 having a recess facing away from the second circuit structure 150 can be formed on the second circuit structure 150. The alignment feature 154 can be formed by forming an opening in the second dielectric layer 152 to expose the second circuit structure 150 and depositing a conductive material in the opening. The process for depositing the conductive material for the alignment feature 154 can be similar to that for the alignment feature 124 and is not further described here for simplicity.

Next, referring to FIG. 5F , a bonding material 156 can be formed on the alignment member 154 . By forming the bonding material 156 , the formed electronic device can be bonded to external circuitry through heating. In some embodiments, after forming an electronic device array including a plurality of electronic units 130 , the electronic device array is cut along, for example, cutting lines L shown in FIG. 5F , to form a plurality of electronic devices. Depending on the design requirements of each electronic device after cutting, each electronic unit 130 can be the same, similar, or different types of components, which is not limited by the present disclosure.

It should be understood that the features of the various embodiments of the present disclosure can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

In summary, the present disclosure provides an electronic device and a method for forming the same. By forming a dummy via pattern in a substrate structure, the substrate structure can be prevented from warping due to uneven stress. Compared to conventional electronic device packaging structures, the electronic device disclosed herein can maintain the stability of the substrate structure without compromising electrical performance. The resulting package structure can enhance the functionality of the electronic unit through the via structure and control unit. Furthermore, the formation of the dummy via structure, which is electrically isolated from the circuit structure, can be integrated into the manufacturing process of the conductive via pattern. Therefore, the formation method disclosed herein can manufacture electronic devices with better electrical and structural properties, or eliminate the need for complex manufacturing steps, thereby saving manufacturing costs.

The above summarizes the features of several embodiments to facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present embodiments can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and/or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and replacements may be made without departing from the spirit and scope of the present invention.

10, 20, 30, 40: Electronic devices 20': Electronic device array 100: Substrate structure 100M: Substrate material 101: Conductive via pattern 101A: First conductive via 101B: Second conductive via 102: Dummy via pattern 104: Buffer layer 105: Stress management layer 106: First insulating layer 108: Second insulating layer 108TS: Top surface 110: Control element 112: Semiconductor layer 114: Gate 116: Source/drain 120: First circuit structure 122: First dielectric layer 122SS: Side surface 124, 154: Alignment element 130: Electronic unit 132: Electrical connection 134, 156: Bonding material 136: Diffusion region 140: Protective layer 150: Second circuit structure 152: Second dielectric layer 160: Conductive material L: Cutting line

The following describes embodiments of the present invention in detail with reference to the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are provided for illustrative purposes only. In fact, the dimensions of components may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present invention. Figure 1 is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view of an array of electronic devices according to some embodiments of the present disclosure. Figure 3 is a cross-sectional view of an electronic device according to some other embodiments of the present disclosure. Figure 4 is a cross-sectional view of an electronic device according to some other embodiments of the present disclosure. Figures 5A-5F are cross-sectional views illustrating various stages of the electronic device manufacturing process according to some embodiments of the present disclosure.

10: Electronic devices

100:Substrate structure

100M:Substrate material

101: Conductive via pattern

101A: First conductive via

101B: Second conductive via

102: Virtual through-hole pattern

104: Buffer layer

105: Stress adjustment layer

106: First Insulation Layer

108: Second insulation layer

108TS: Top surface

110: Control element

112: Semiconductor layer

114: Gate

116: Source/Drain

120: First circuit structure

122: First dielectric layer

122SS: Side

124,154: Alignment components

130: Electronic unit

132: Electrical connection part

134,156: Bonding materials

136: Diffusion Zone

140: Protective layer

150: Second circuit structure

152: Second dielectric layer

Claims (9)

An electronic device characterized by comprising: a substrate structure having a conductive via pattern and a dummy via pattern; a control unit electrically connected to the conductive via pattern; a first circuit structure electrically connected to the conductive via pattern; and an electronic unit electrically connected to the control unit via the first circuit structure, wherein the dummy via pattern is electrically insulated from the first circuit structure, wherein the conductive via pattern includes a first conductive via electrically connected to the control unit via the first circuit structure, and a second conductive via electrically connected to the electronic unit via a portion of the first circuit structure separated from the control unit. The electronic device of claim 1, further comprising: A second circuit structure disposed on the substrate structure and opposite the first circuit structure, wherein the dummy via pattern is electrically isolated from the second circuit structure. The electronic device of claim 2 is characterized in that the first circuit structure and the second circuit structure are electrically connected through the conductive via pattern. The electronic device of claim 1 is characterized by further comprising: A stress adjustment layer disposed on the substrate structure and located on a side of the substrate structure opposite to the control unit, wherein the stress adjustment layer covers a bottom surface of the dummy through-hole pattern. The electronic device of claim 1 is characterized in that the control unit is located above the substrate structure and between the substrate structure and the first circuit structure. The electronic device of claim 1 is characterized in that the control unit is located below the substrate structure, and the substrate structure is located between the control unit and the first circuit structure. The electronic device of claim 1 is characterized in that it further includes a protective layer surrounding the electronic unit. The electronic device of claim 1 is characterized in that the substrate structure comprises a transparent material. The electronic device of claim 1, wherein the conductive via pattern and the dummy via pattern comprise the same material.