TWI911535B - Electronic device - Google Patents

Abstract

An electronic device includes a chip and a circuit structure layer overlapping the chip. The circuit structure layer includes a redistribution structure layer and an element structure layer, and the redistribution structure layer and the element structure layer are electrically connected to the chip. At least one of the redistribution structure layer and the element structure layer includes at least one opening, and the at least one opening overlaps a side of the chip in a normal direction of the electronic device.

Description

Electronic devices

This disclosure relates to an electronic device, and more particularly to an electronic device including a package structure.

Electronic devices may include chips and redistribution layers for electrically connecting the chips to other electronic components. However, the film layers in the redistribution layers can be susceptible to damage due to stress. Therefore, how to reduce stress in the package structure remains an important issue in this field.

In some embodiments, this disclosure provides an electronic device including a chip and a circuit structure layer overlapping the chip. The circuit structure layer includes a redecosystem layer and a component structure layer, wherein the redecosystem layer and the component structure layer are electrically connected to the chip. At least one of the redecosystem layer and the component structure layer includes at least one opening that overlaps one side of the chip in a normal direction of the electronic device.

This disclosure can be understood by referring to the following detailed description and accompanying drawings. It should be noted that, for ease of understanding and for the sake of simplicity, many of the accompanying drawings only show a portion of the device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

Throughout this disclosure and the attached patent claims, certain terms will be used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that have the same function but different names.

In the following description and scope of the patent application, the words "containing" and "including" are open-ended terms, and therefore should be interpreted as "containing but not limited to...".

It should be understood that when a component or film is said to be "placed" on or "connected" to another component or film, it can be directly on or directly connected to the other component or film, or there may be an inserted component or film between them (indirect cases). Conversely, when a component is said to be "directly" on or "directly connected" to another component or film, there may be no inserted component or film between them. When a component or film is said to be "electrically connected" to another component or film, it can be interpreted as a direct electrical connection or a non-direct electrical connection. The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the terminals of the components on the two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, the terminals of the components on the two circuits are connected by a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components, but are not limited thereto.

Although the terms "first," "second," "third," etc., can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but rather replaced with "first," "second," "third," etc., according to the order of the components declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

In this disclosure, the thickness, length and width can be measured by optical microscope, and the thickness or width can be measured by cross-sectional images in electron microscope, but are not limited thereto.

Furthermore, any two values or directions used for comparison may have a certain degree of error. The terms "approximately," "equal to," "equivalent to," "identical," "substantially," or "roughly" are generally interpreted as being within ±20% of the given value, or within ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of the given value.

Furthermore, the terms "the given range is from the first value to the second value" and "the given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values in between.

If the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 and 10 degrees.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted in a manner consistent with the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

It should be understood that, without departing from the spirit of this disclosure, the technical features in several different embodiments can be replaced, recombined, or mixed to complete other embodiments.

The electronic devices disclosed herein may include, but are not limited to, semiconductor devices, packaging devices, display devices, sensing devices, backlight devices, antenna devices, splicing devices, or other suitable electronic devices. The electronic devices disclosed herein may include any suitable device applied to the aforementioned devices. The electronic devices may be bendable, flexible, or stretchable. Display devices may be used, for example, in laptops, public displays, splicing displays, automotive displays, touch displays, televisions, surveillance cameras, smartphones, tablets, light source modules, lighting equipment, or, for example, electronic devices applied to the aforementioned products, but are not limited to these. Sensing devices may include biosensors, touch sensors, fingerprint sensors, other suitable sensors, or combinations of sensors of the aforementioned types. Antenna devices can be liquid crystal type antenna devices or non-liquid crystal type antenna devices, including, but not limited to, liquid crystal antenna devices. Splicing devices can include, for example, display splicing devices or antenna splicing devices, but are not limited to, these. The shape of the electronic device can be rectangular, circular, polygonal, with curved edges, or other suitable shapes. The electronic device can include electronic units, which can include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. Diodes can include light-emitting diodes or photodiodes. The light-emitting diode (LED) may include, for example, an organic light-emitting diode (OLED) or an inorganic light-emitting diode (in-organic LED). Inorganic LEDs may include, for example, mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. It should be noted that the electronic device disclosed herein can be any combination of the above-mentioned devices, but is not limited thereto. It should also be noted that the electronic device can be any arrangement or combination of the foregoing, but this disclosure is not limited thereto. Electronic devices may have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices (such as augmented reality or virtual reality), in-vehicle devices (such as car windshields), or splicing devices.

Please refer to Figure 1, which is a cross-sectional schematic diagram of the electronic device according to the first embodiment of this disclosure. Specifically, Figure 1 shows the cross-sectional structure of the structure shown in Figure 2 along the tangent A-A'. According to this embodiment, as shown in Figure 1, the electronic device ED may include a chip CP and a circuit structure layer CS, wherein the circuit structure layer CS may overlap the chip CP in the normal direction of the electronic device ED (i.e., parallel to direction Z, which will not be elaborated further below). The circuit structure layer CS may include a redistribution layer RDL and a component structure layer ES, wherein the component structure layer ES may be located on the side of the redistribution layer RDL opposite to the chip CP, that is, the redistribution layer RDL is located between the chip CP and the component structure layer ES, but is not limited thereto. The electronic device ED may also include a buffer layer INL disposed on the side of the component structure layer ES opposite to the redistribution structure layer RDL, i.e., the component structure layer ES is disposed between the buffer layer INL and the redistribution structure layer RDL. The electronic device ED may also include a package layer EN, wherein the package layer EN may surround the chip CP. The phrase "package layer EN surrounds the chip CP" may refer to, in a cross-sectional view of the electronic device ED (e.g., Figure 1), at least a portion of the chip CP is disposed within the package layer EN, and the package layer EN may contact the side surface of the chip CP. The package layer EN may be used to package the chip CP, the circuit structure layer CS, or other components and/or film layers of the electronic device ED. The encapsulation layer EN can include any suitable encapsulation material. For example, the encapsulation layer EN can include organic materials, inorganic materials, or combinations thereof. The encapsulation layer EN can include transparent or opaque encapsulation materials. It should be noted that although Figure 1 illustrates the structure of an encapsulation layer EN encapsulating a single chip CP, this disclosure is not limited thereto. In some embodiments, the encapsulation layer EN can be used to encapsulate multiple chip CPs, i.e., the electronic device ED can include a multi-chip encapsulation structure. The encapsulation layer EN can reduce the influence of external moisture on the components and/or film layers in the electronic device ED. In this embodiment, the method of forming the electronic device ED can include forming the circuit structure layer CS first and then forming the chip CP, which can be regarded as a circuit redistribution-first (RDL-first) process. Specifically, a circuit structure layer CS can be formed first on a buffer layer INL, and then a chip CP can be placed on the circuit structure layer CS. Next, a package layer EN can be placed and cover the chip CP and the circuit structure layer CS to form an electronic device ED. It should be noted that the method for forming the electronic device ED disclosed herein is not limited to the above.

The structure of each component of the electronic device ED of this embodiment will be described in detail below.

The chip CP disclosed herein may include an integrated circuit (IC) chip, a diode chip, other suitable chips, or a combination of the above chips, depending on the type or purpose of the electronic device ED. For example, when the electronic device ED includes a display device, the chip CP may include a light-emitting diode chip, but is not limited thereto. The chip CP may be electrically connected to a circuit structure layer CS. Specifically, the redistribution layer RDL and the component structure layer ES in the circuit structure layer CS may be electrically connected to the chip CP. For example, as shown in Figure 1, the chip CP may include an insulating layer INL2 disposed on the side of the chip CP facing the circuit structure layer CS. A conductive layer CL1 may be disposed in the insulating layer INL2, and the chip CP can be electrically connected to the underbump metalization layer UM1 via the conductive layer CL1 and the bonding pad SD1. The underbump metalization layer UM1 may be disposed in one of the insulating layers of the redistribution structure layer RDL closest to the chip CP (e.g., insulating layer IL3), but is not limited thereto. The underbump metalization layer UM1 may be electrically connected to the redistribution structure layer RDL and the component structure layer ES in the circuit structure layer CS, thereby electrically connecting the chip CP to the redistribution structure layer RDL and the component structure layer ES. The bottom metal layer UM1 and the conductive layer CL1 may comprise any suitable conductive material, such as molybdenum (Mo), tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co), zirconium (Zr), tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), other suitable metals, or alloys or combinations thereof. In some embodiments, the bottom metal layer UM1 and the conductive layer CL1 may be, for example, a single metal layer or a laminated structure formed by stacking multiple sub-metal layers, but are not limited thereto. The bonding pad SD1 may include tin, nickel, gold, silver, tin-containing alloys, or other suitable conductive materials. It should be noted that the structures of the insulating layer INL2 and conductive layer CL1 shown in Figure 1 are merely exemplary. In some embodiments, the insulating layer INL2 may include a structure formed by stacking multiple insulating layers. The insulating layer INL2 may contain organic or inorganic materials. The thickness of the insulating layer INL2 may be greater than or equal to 0.5 micrometers (μm) and less than or equal to 20 μm. The wafer CP may be formed by dicing a wafer or semiconductor substrate, and when the wafer or semiconductor substrate includes hard and brittle materials, it is prone to cracking or chipping after the dicing process. According to this embodiment, the thickness design of the insulating layer INL2 can reduce the occurrence of wafer or semiconductor substrate breakage or chipping. For example, the thickness of the insulating layer INL2 can be designed to be greater than or equal to 7 μm and less than or equal to 20 μm, more preferably greater than or equal to 10 μm and less than or equal to 20 μm, but is not limited thereto.

The redistribution layer (RDL) includes any suitable film layer that allows adjustment of the positions of signal inputs and outputs, or adjustment of the routing layout. In this disclosure, the RDL may comprise a stacked structure formed by stacking at least one insulating layer and at least one conductive layer, wherein the stacking direction of the insulating and conductive layers may, for example, be parallel to the normal direction of the electronic device (ED). For example, as shown in Figure 1, the redistribution layer RDL of this embodiment may include an insulating layer IL1, an insulating layer IL2 disposed on the insulating layer IL1, a conductive layer CL2 disposed on the insulating layer IL2, and an insulating layer IL3 disposed on the insulating layer IL2 and covering the conductive layer CL2, but is not limited thereto. Insulating layers IL1, IL2, and IL3 may include any suitable organic material, such as photosensitive polyimide (PSPI), ABF (Ajinomoto build-up film) material, combinations of the above materials, or other build-up materials, but is not limited thereto. The conductive layer CL2 may comprise any suitable conductive material, and the conductive layer CL2 may be made of the same or different material as the conductive layer CL1. It should be noted that the number and relative placement of the insulating and conductive layers in the redistribution structure layer RDL shown in Figure 1 are merely exemplary and are not intended to limit this disclosure.

The component structure layer ES may include electronic components EL for receiving signals from or transmitting signals to the chip CP, but is not limited thereto. Electronic components EL may include, for example, at least one switching element, at least one driving element, at least one protection element, or other suitable active or passive elements, depending on the design of the electronic device ED. Specifically, the electronic components EL in the electronic device ED and the film layer used to mount the electronic components EL can be considered as part of the component structure layer ES. In this embodiment, the electronic components EL may include driving elements DU, but is not limited thereto. The driving elements DU may include thin-film transistors, therefore the component structure layer ES may include thin-film transistors and film layers used to mount the thin-film transistors. Specifically, as shown in Figure 1, the component structure layer ES may include an insulating layer IL4, a semiconductor layer SM disposed on the insulating layer IL4, an insulating layer IL5 disposed on the insulating layer IL4 and covering the semiconductor layer SM, a conductive layer CL3 disposed on the insulating layer IL5, an insulating layer IL6 disposed on the insulating layer IL5 and covering the conductive layer CL3, and a conductive layer CL4 disposed on the insulating layer IL6, but is not limited thereto. Insulating layers IL4, IL5, and IL6 may comprise, but are not limited to, any suitable insulating material, such as organic or inorganic insulating materials. Organic insulating materials include, for example, photosensitive polyimide or ABF materials, while inorganic insulating materials include, for example, silicon oxide, silicon nitride, or silicon oxynitride, but are not limited to. The semiconductor layer SM may form the channel region CR, source region SR, and drain region DR of the driver element DU. The material of the semiconductor layer SM includes, for example, low-temperature polysilicon (LTPS), low-temperature polysilicon oxide (LTPO), or amorphous silicon (a-Si), but is not limited to. The conductive layer CL3 can form the gate electrode GE of the driver element DU. In the normal direction of the electronic device ED, the channel region CR can be defined as the portion where the semiconductor layer SM overlaps with the gate electrode GE. The conductive layer CL4 can form the source electrode SE and drain electrode DE, which are electrically connected to the source region SR and drain region DR, respectively. The source electrode SE and drain electrode DE can be filled with vias passing through the insulation layers IL5 and IL6, respectively, and electrically connected to the source region SR and drain region DR. It should be noted that in some embodiments, the source region SR and source electrode SE can be the drain region and drain electrode, respectively, while the drain region DR and drain electrode DE can be the source region and source electrode, respectively. That is, the positions or functions of the source region SR/source electrode SE and the drain region DR/drain electrode DE can be interchanged. Conductive layers CL3 and CL4 can include any suitable conductive material, such as metal, but are not limited thereto. Although not shown in Figure 1, the component structure layer ES can include other suitable electronic components EL in addition to the driver element DU. It should be noted that the structure of the component structure layer ES disclosed herein is not limited to that shown in Figure 1. Furthermore, although the electronic device EL of this embodiment includes top-gate thin-film transistors, this disclosure is not limited thereto. In some embodiments, the electronic device EL may include bottom-gate thin-film transistors, dual-gate thin-film transistors, or other suitable types of thin-film transistors.

According to some embodiments, in the normal direction of the electronic device ED, the thickness of the insulation layer in the component structure layer ES is less than the thickness of the insulation layer in the redistribution structure layer RDL. This can reduce the impact of noise generated by electronic components in the component structure layer ES on electrical quality, but is not limited thereto. For example, the insulation layers in the component structure layer ES (e.g., insulation layers IL4, IL5, and IL6) have a thickness greater than or equal to 0.1 μm and less than or equal to 5 μm, while the insulation layers in the redistribution structure layer RDL (e.g., insulation layers IL1, IL2, and IL3) have a thickness greater than or equal to 6 μm and less than or equal to 15 μm. According to some embodiments, the thermal expansion coefficient of the insulation layers in the component structure layer ES is less than the thermal expansion coefficient of the insulation layers in the redistribution structure layer RDL. For example, the thermal expansion coefficient of the insulation layer in the component structure layer ES is greater than or equal to 0.1 ppm/°C and less than or equal to 10 ppm/°C, while the thermal expansion coefficient of the insulation layer in the redistribution structure layer RDL is greater than or equal to 12 ppm/°C and less than or equal to 30 ppm/°C. In some embodiments, the warping trend of the insulation layer in the component structure layer ES is opposite to that of the insulation layer in the redistribution structure layer RDL. This mitigates stress in the electronic device ED, reduces the risk of cracking, and thus improves the reliability of the electronic device ED.

According to this disclosure, a buffer layer INL can be used to prevent the diffusion of metal ions (e.g., external metal ions) into the electronic component EL in the component structure layer ES. This reduces the likelihood of damage to the electronic component EL due to the influence of metal ions. The buffer layer INL can also be used to provide a planar surface to facilitate the placement of a circuit structure layer CS thereon. Specifically, the buffer layer INL can serve as a planarization layer to facilitate deposition processes on its surface to form electronic components EL, such as driver components DU. Although the buffer layer INL shown in FIG. 1 is a single-layer structure, this disclosure is not limited thereto. In some embodiments, the buffer layer INL may comprise a multi-layer structure. In addition, in some embodiments, the buffer layer INL may comprise a structure formed by stacking insulating and conductive layers and may serve as another redistribution layer.

According to this disclosure, the insulating layers in the component structure layer ES disposed on the buffer layer INL may protrude beyond the buffer layer or be flush with the side surface S1 of the buffer layer INL, depending on the manufacturing process (e.g., dicing process) of the electronic device ED. For example, in this embodiment, as shown in FIG1, the insulating layers IL4, IL5, and IL6 in the component structure layer ES may protrude beyond the side surface S1 of the buffer layer INL and extend to the bottom of the side surface S1, but are not limited thereto. In some embodiments, insulating layers IL4, IL5, and IL6 may be flush with the side surface S1 of the buffer layer INL, or the side surfaces of insulating layers IL4, IL5, and IL6 may be coplanar with the side surface S1 of the buffer layer INL without covering the side surface S1, as shown in Figure 3.

According to this embodiment, the chip CP can be electrically connected to the redistribution layer RDL (e.g., electrically connected to the conductive layer CL2 in the redistribution layer RDL), and electrically connected to the electronic component EL of the component structure layer ES through the redistribution layer RDL. For example, as shown in FIG1, a portion of the conductive layer CL2 in the redistribution layer RDL can be electrically connected to the chip CP, and this portion of the conductive layer CL2 can be filled with a via V1 that passes through the insulating layers IL1 and IL2 and contacts one of the source electrode SE and drain electrode DE of the driver component DU of the component structure layer ES (e.g., the drain electrode DE shown in FIG1, but not limited thereto), thereby electrically connecting the chip CP to the electronic component EL. Thus, the operation of the chip CP can be controlled by the driver element DU, or the chip CP can transmit signals to the electronic component EL. Furthermore, another portion of the conductive layer CL2 can be electrically connected to the drain electrode DE and the other source electrode SE of the driver element DU (e.g., the source electrode SE shown in Figure 1, but not limited thereto) and the bottom metal layer UM2, and electrically connected to an external electronic component (not shown) via the bottom metal layer UM2 and the bonding pad SD2. External electronic components include, for example, printed circuit boards (PCBs), but are not limited thereto. Specifically, a portion of the conductive layer CL2 can be filled with a via V2 that passes through insulating layers IL1, IL2, IL4, IL5, IL6, and the buffer layer INL and contacts the bottom metal layer UM2. The bottom metal layer UM2 can be located within the buffer layer INL, but is not limited to this. In this way, the chip CP can be electrically connected to external electronic components through the circuit structure layer CS. As shown in Figure 1, by setting a redistribution layer RDL, the positions of the signal input terminals (e.g., corresponding to the positions on the conductive layer CL1) and the signal output terminals (e.g., corresponding to the positions on the bottom metal layer UM2) located on both sides of the redistribution layer RDL do not necessarily correspond to each other. In other words, the signal input/output terminals of the chip CP and the signal input/output terminals of the electronic device ED can be misaligned in the top view direction of the electronic device ED, or in other words, they do not overlap in the normal direction. It should be noted that the above-described electrical connection method between the chip CP, the circuit structure layer CS, and the external electronic components is merely exemplary, and this embodiment is not limited thereto. Furthermore, in some embodiments, the circuit structure layer CS may include a redistribution structure layer RDL but not a component structure layer ES, and the chip CP may be electrically connected to external electronic components through the redistribution structure layer RDL.

The bottom metal layer in the disclosed electronic device ED may have a suitable structure. In some embodiments, the bottom metal layer may protrude from the surface of the insulating layer on which it is disposed, and its surface may have a recessed structure. For example, as shown in FIG1, the surface of the bottom metal layer UM1 that contacts the bonding pad SD1 (i.e., surface S2) may protrude from the surface of the insulating layer IL3, and the surface S2 of the bottom metal layer UM1 may have a recessed structure, or in other words, the bottom metal layer UM1 may have a recessed surface S2. In some embodiments, the bottom metal layer may be flush with the surface of the insulating layer on which it is disposed, and its surface may have a recessed structure. For example, as shown in Figure 1, the surface (i.e., surface S3) in contact with the bottom metal layer UM2 and the bonding pad SD2 may be flush with or not protrude from the surface of the buffer layer INL, and the surface S3 of the bottom metal layer UM2 may have a recessed structure. By including a recessed structure on the surface in contact with the bonding pad, the electrical connection between the bottom metal layer and the bonding pad can be improved, thereby enhancing the reliability of the electronic device ED. The bottom metal layer disclosed herein may also include other suitable structures, and is not limited to the structures described above.

Please refer to Figures 1 and 2. Figure 2 is a top view schematic diagram of the component configuration of the electronic device according to the first embodiment of this disclosure, showing the main components of the electronic device but not all of them. Specifically, as shown in Figure 2, the input/output point (hereinafter referred to as I/O point) IO1 of the chip CP can be electrically connected to the electronic component EL of the component structure layer ES via trace WL1, and the electronic component EL can be electrically connected to the I/O point IO2 via trace WL2. The I/O point IO1 can correspond to the location of the conductive layer CL1. Trace WL1 can refer to any suitable conductive element used to electrically connect the chip CP to the electronic component EL. For example, trace WL1 can include a conductive layer (e.g., conductive layer CL2) in the redistribution structure layer RDL. Trace WL2 can refer to any suitable conductive element that electrically connects the electronic component EL to the bottom metal layer UM2. For example, trace WL2 may include a portion of the conductive layer CL2 shown on the left side of Figure 1. I/O point IO2 may correspond to the location of the bottom metal layer UM2 and may be electrically connected to external electronic components. It should be noted that Figure 2 only illustrates the electrical connections of the components exemplarily and does not show the detailed structure or location of each component. Furthermore, the number of electronic components EL and I/O points shown in Figure 2 is merely exemplary.

According to this embodiment, at least one of the redistribution line structure layer RDL and the device structure layer ES may include at least one opening, wherein the at least one opening may overlap the side of the wafer CP in the normal direction of the electronic device ED. Specifically, the opening may overlap at least a portion of the side of the wafer CP. Here, "opening" may refer to a structure that disconnects at least one layer of the film structure. In other words, when a film structure includes an opening, in a cross-sectional view of the film structure, at least one layer of the film structure may be separated by the opening, or the portions of the at least one layer located on either side of the opening are not connected to each other through the material of the at least one layer. Therefore, the aforementioned "opening" can also be considered as a through hole penetrating the at least one layer. As shown in Figure 1, the component structure layer ES of this embodiment may include at least one first opening ST1, wherein the first opening ST1 overlaps with the side SS of the chip CP in the normal direction of the electronic device ED. In this embodiment, the first opening ST1 may be formed by removing portions of the insulating layers IL4, IL5, and IL6, but this disclosure is not limited thereto. In other words, the first opening ST1 may serve as a through-hole penetrating the insulating layers IL4, IL5, and IL6. In this case, the first opening ST1 disconnects the insulating layers IL4, IL5, and IL6 on both sides. In some embodiments, the first opening ST1 may be formed by removing a portion of the insulation layer IL4, exposing the upper surface of the insulation layer IL5. In this case, the first opening ST1 disconnects the insulation layer IL4. In some embodiments, the first opening ST1 may be formed by removing portions of both insulation layers IL4 and IL5, exposing the upper surface of the insulation layer IL6. In this case, the first opening ST1 disconnects both insulation layers IL4 and IL5. Furthermore, the redistribution line structure layer RDL of this embodiment may include at least one second opening ST2, wherein the second opening ST2 overlaps with the side SS of the chip CP in the normal direction of the electronic device ED. Therefore, in the normal direction of the electronic device ED, the first opening ST1 may overlap with or at least partially overlap with the second opening ST2. In this embodiment, the second opening ST2 may be formed by removing a portion of the insulating layer IL2, but this disclosure is not limited thereto. In other words, the second opening ST2 may serve as a through-hole penetrating the insulating layer IL2 and breaking the insulating layer IL2. In some embodiments, the electronic device ED may include the first opening ST1 but not the second opening ST2. In this case, the conductive layer CL2 may extend on the flat insulating layer IL2. In some embodiments, the electronic device ED may include the second opening ST2 but not the first opening ST1.

Specifically, as shown in Figures 1 and 2, the electronic device ED may have a first region R1, a second region R2, and a third region R3. The first region R1 may be a region in the electronic device ED that generally corresponds to the side SS of the chip CP. The second region R2 may be a region in the electronic device ED that generally corresponds to the chip CP. In a top view of the electronic device ED (e.g., Figure 2), the second region R2 is surrounded by the first region R1, but is not limited thereto. The third region R3 may be any region in the electronic device ED other than the first region R1 and the second region R2. According to this embodiment, a first opening ST1 of the component structure layer ES and/or a second opening ST2 of the redistribution line structure layer RDL are disposed in the first region R1 of the electronic device ED, such that the first opening ST1 and/or the second opening ST2 overlap the side SS of the chip CP. In this embodiment, as shown in FIG2, the chip CP may, for example, have a rectangular shape with four sides SS, and the component structure layer ES (and/or redistribution structure layer RDL) may include a first opening ST1 (and/or a second opening ST2), wherein the first opening ST1 and/or the second opening ST2 may be disposed along the four sides SS of the chip CP (the extent of the first opening ST1 and/or the second opening ST2 is indicated by diagonal lines in FIG2), that is, the first opening ST1 and/or the second opening ST2 will surround the chip CP (or surround the second region R2) in the top view of the electronic device ED, but this disclosure is not limited thereto. In some embodiments, the first opening ST1 and/or the second opening ST2 may not completely surround the chip CP in the top view of the electronic device ED. In some embodiments, the component structure layer ES (and/or redistribution structure layer RDL) may include multiple first openings ST1 (and/or multiple second openings ST2) disposed along a portion of the side edge SS of the chip CP. The electronic device ED may also include other openings, and this disclosure is not limited thereto.

In existing wafer packaging structures, the film layers on the sides of the wafer are more susceptible to stress, which can lead to breakage or damage, thereby reducing the reliability of the device. For example, during wafer mounting, the film layers on the sides of the wafer may be subjected to greater stress. According to the first embodiment provided in this disclosure, since the redistribution line structure layer RDL and/or the device structure layer ES include a first opening ST1 and/or a second opening ST2 corresponding to the side edge SS of the wafer CP, the stress borne by the insulation layer of the redistribution line structure layer RDL and the device structure layer ES corresponding to the wafer CP can be reduced, thereby reducing the possibility of the insulation layer in the redistribution line structure layer RDL and the device structure layer ES breaking. Furthermore, as shown in FIG. 1, the bottom of the first opening ST1 and the second opening ST2 can be arc-shaped or other suitable non-pointed shapes, but are not limited thereto. Thus, the stress borne by the portion of the side edge SS of the redistribution line structure layer RDL and the device structure layer ES corresponding to the wafer CP can be further reduced.

According to this embodiment, the electronic device ED may also include a support element disposed in the opening. Specifically, the portion of the element and/or film layer of the electronic device ED that fills the opening can be defined as a support element. For example, as shown in FIG1, the element structure layer ES may include a first opening ST1, and a portion of the insulation layer IL1 in the redistribution line structure layer RDL may extend into, or fill into, the first opening ST1. In this case, the portion of the insulation layer IL1 filling the first opening ST1 can be defined as a support element SP1. The material of the support element SP1 may be determined based on the material of the film layer and/or element filling the first opening ST1. In this embodiment, since a portion of the insulating layer IL1 is filled into the first opening ST1, the material of the supporting element SP1 can be the same as the material of the insulating layer IL1. In other embodiments, a portion of the conductive layer (e.g., conductive layer CL2) in the redistribution layer RDL can be filled into the first opening ST1, and the material of the supporting element SP1 can be the same as the material of the conductive layer CL2. In still other embodiments, a portion of both the insulating layer IL1 and the conductive layer CL2 in the redistribution layer RDL can be filled into the first opening ST1, and the material of the supporting element SP1 can include the same as the materials of the insulating layer IL1 and the conductive layer CL2. In other words, the supporting element SP1 can include insulating material, metallic material, or a combination of the above materials. As described above, the insulating layer IL1 may include an organic insulating material. Therefore, by providing a support element SP1 in the first opening ST1, wherein the support element SP1 may include an organic insulating material or a metallic material, the stress experienced by the portion of the electronic device ED corresponding to the side SS of the chip CP can be reduced, thereby improving the reliability of the electronic device ED. Similarly, as shown in FIG1, the redistribution line structure layer RDL may include a second opening ST2, and a portion of the conductive layer CL2 and the insulating layer IL3 in the redistribution line structure layer RDL may extend into the second opening ST2. Therefore, the electronic device ED may include a support element SP2 disposed in the second opening ST2, wherein the support element SP2 includes a portion of the conductive layer CL2 and the insulating layer IL3, but is not limited thereto. According to different embodiments of this disclosure, the support element SP2 may include one or more of an insulating material and a conductive material.

In some embodiments, the surface of the redistribution line structure layer RDL of the electronic device ED may selectively have at least one groove, wherein the groove may overlap with the side edge SS of the wafer CP in the normal direction of the electronic device ED. Specifically, as shown in FIG. 1, the surface S4 of the redistribution line structure layer RDL facing the wafer CP may have a groove RS, wherein the groove RS may correspond to the side edge SS of the wafer CP. The groove RS may be formed by removing at least a portion of the surface of the redistribution line structure layer RDL, for example by removing a portion of the insulating layer IL3, but is not limited thereto. In some embodiments, the groove RS may extend along the side edge SS of the wafer CP and form a closed structure. In some embodiments, the groove RS may extend only along a portion of the side edge SS of the wafer CP. In some embodiments, the surface S4 of the redistribution line structure layer RDL may have multiple grooves RS, each extending along a portion of the side edge SS of the wafer CP. In the normal direction of the electronic device ED, since the grooves RS may overlap the side edge SS of the wafer CP, the grooves RS may overlap with, or at least partially overlap with, the first opening ST1 and/or the second opening ST2, but are not limited thereto. The bottom of the grooves RS may be arc-shaped or other suitable non-pointed shapes, but is not limited thereto. By forming grooves RS on the surface S4 of the redistribution line structure layer RDL, the stress experienced by the electronic device ED corresponding to a portion of the side edge SS of the wafer CP can be reduced. In some embodiments, the surface S4 of the redistribution line structure layer RDL may not have grooves RS. Specifically, in the normal direction of the electronic device ED, the height of the groove RS is less than the insulation layer thickness of the redistribution layer RDL. In particular, the height of the groove RS is less than half the insulation layer thickness of the redistribution layer RDL.

In some embodiments, the electronic components EL in the component structure layer ES do not overlap with the side edge SS of the wafer CP in the normal direction of the electronic device ED. In other words, the electronic components EL may not correspond to the side edge SS of the wafer CP. Specifically, the electronic components EL in this embodiment may include thin-film transistors, wherein the thin-film transistors may not overlap with the side edge SS of the wafer CP in the normal direction of the electronic device ED. The meaning of "thin-film transistors do not overlap with the side edge SS of the wafer CP" may include at least the case where the semiconductor layer SM of the thin-film transistors does not overlap with the side edge SS of the wafer CP, but is not limited thereto. In this case, the electronic components EL are not disposed in the first region R1 of the electronic device ED. In some embodiments, as shown in FIG1, the electronic components EL may be disposed in the third region R3. In some embodiments, although not shown in the figures, electronic component EL may be disposed in the second region R2, meaning that electronic component EL may overlap a portion of the wafer CP in the normal direction of the electronic device ED, but not overlap the side SS of the wafer CP. By ensuring that the placement of electronic component EL does not overlap with the side SS of the wafer CP, the effect of stress on electronic component EL can be reduced. Furthermore, in some embodiments, electronic component EL may also not overlap with bonding pads SD1 and/or SD2 in the normal direction of the electronic device ED. In other words, the placement of electronic component EL may not correspond to the positions of the side SS of the wafer CP, bonding pads SD1 and/or SD2. In this case, electronic component EL may be disposed in the second region R2 or the third region R3 without corresponding to the bonding pad positions.

Further embodiments of this disclosure will be described below. For the sake of simplicity, the same film or element in the following embodiments will be labeled with the same designation, and its features will not be repeated. The differences between the embodiments will be described in detail below.

Please refer to Figure 3, which is a cross-sectional schematic diagram of the electronic device according to the second embodiment of this disclosure. According to this embodiment, the component structure layer ES may have a first opening ST1, and the conductive layer CL2 in the redistribution line structure layer RDL may extend into the first opening ST1. In other words, the conductive layer CL2 may fill the first opening ST1. Specifically, as shown in Figure 3, the portions of the insulating layers IL1 and IL2 of the redistribution line structure layer RDL and the insulating layers IL4, IL5, and IL6 of the component structure layer ES corresponding to the side SS of the wafer CP can be removed to form the first opening ST1 of the component structure layer ES and the second opening ST2 of the redistribution line structure layer RDL. The conductive layer CL2 disposed on the insulating layer IL2 can extend downward and fill the first opening ST1 and the second opening ST2. In this case, the support element SP1 disposed in the first opening ST1 and the support element SP2 disposed in the second opening ST2 may include the material of the conductive layer CL2, such as a metal material. Furthermore, support element SP1 may, for example, contact support element SP2. Moreover, in the normal direction of electronic device ED, first opening ST1 may overlap with or at least partially overlap with second opening ST2.

Furthermore, in this embodiment, as shown in FIG3, the surface S4 of the redistribution line structure layer RDL may have multiple grooves RS, wherein these grooves RS may be disposed in the first region R1 of the electronic device ED, or corresponding to/adjacent to the side SS of the wafer CP. In some embodiments, these grooves RS may extend along the side SS of the wafer CP and form a closed structure. In some embodiments, these grooves RS may extend along a portion of the side SS of the wafer CP. It should be noted that the number and shape of the grooves RS shown in FIG3 are merely exemplary and this disclosure is not limited thereto.

Furthermore, compared to the structure shown in FIG1, the bottom metal layer of this embodiment may have a different structure. In some embodiments, the bottom metal layer may be flush with the surface of the insulating layer on which it is disposed. For example, as shown in FIG3, the surface S2 of the bottom metal layer UM1 that contacts the bonding pad SD1 may be flush with the surface of the insulating layer IL3, and the surface S2 of the bottom metal layer UM1 may be substantially flat. In some embodiments, the bottom metal layer may protrude from the surface of the insulating layer on which it is disposed, and its surface may be flat. For example, as shown in FIG3, the surface S3 of the bottom metal layer UM2 that contacts the bonding pad SD2 may protrude from the surface of the buffer layer INL, and the surface S3 of the bottom metal layer UM2 may be substantially flat. The structural features of the bottom metal layer in this embodiment and the bottom metal layer in the above embodiments can be applied to all embodiments disclosed herein.

The structural features of other components and/or films of the electronic device ED shown in Figure 3 can be found above, and therefore will not be repeated here.

Please refer to Figures 4 and 5. Figure 4 is a top view of the component configuration of the electronic device according to the third embodiment of this disclosure, and Figure 5 is an equivalent circuit diagram of the electronic components according to the third embodiment of this disclosure. According to this embodiment, the first opening ST1 of the component structure layer ES and/or the second opening ST2 of the redistribution structure layer RDL may not completely surround the chip CP in the top view of the electronic device ED. Specifically, as shown in Figure 4, the component structure layer ES (and/or the redistribution structure layer RDL) of this embodiment may include multiple first openings ST1 (and/or second openings ST2), and these first openings ST1 (and/or second openings ST2) may be respectively disposed along a portion of the side SS of the chip CP. In this embodiment, the first opening ST1 and/or the second opening ST2 may correspond to the I/O point of the electrical connection chip CP and the trace WL1 of the electronic component EL. That is, the first opening ST1 and/or the second opening ST2 may overlap with the trace WL1 in the normal direction of the electronic device ED, but this is not a limitation. In other words, the first opening ST1 and/or the second opening ST2 may be disposed in the first region R1 corresponding to a portion of the trace WL1. As mentioned above, the trace WL1 may include the conductive layer CL2 of the redistributed line structure layer RDL. Therefore, in this embodiment, the first opening ST1 and/or the second opening ST2 may overlap with the conductive layer CL2 of the redistributed line structure layer RDL, but this is not a limitation.

Furthermore, in this embodiment, the electronic component EL may, for example, include a demultiplexer (DeMUX) DMX, wherein the demultiplexer DMX may include at least one thin-film transistor element, but is not limited thereto. For example, as shown in FIG5, the demultiplexer DMX may include thin-film transistors T1, T2, and T3, wherein the gates of these thin-film transistors are respectively electrically connected to one of the I/O points IO2, the sources of these thin-film transistors may be electrically connected to a signal input terminal IN, and the drains of these thin-film transistors may be respectively electrically connected to a signal output terminal, wherein the signal output terminal may be electrically connected to I/O point IO1. It should be noted that the circuit of the demultiplexer DMX shown in FIG5 is merely exemplary, and this disclosure is not limited thereto. By including a demultiplexer DMX in the electronic components EL of the electronic device ED, the number of I/O points IO2 can be reduced, thereby simplifying the routing layout of the electronic device ED. In this embodiment, the demultiplexer DMX may not overlap with the side SS of the chip CP in the normal direction of the electronic device ED, or in other words, it may not be positioned corresponding to the side SS of the chip CP. Furthermore, in some embodiments, the demultiplexer DMX may also not overlap with the bonding pads SD1 and/or SD2 in the normal direction of the electronic device ED. In this case, the demultiplexer DMX can be positioned in the second region R2 or the third region R3 at a location that does not correspond to a bonding pad.

Please refer to Figures 6 and 7. Figure 6 is a cross-sectional schematic diagram of the electronic device according to the fourth embodiment of this disclosure, and Figure 7 is a top schematic diagram of the component configuration of the electronic device according to the fourth embodiment of this disclosure. According to this embodiment, the electronic components EL of the component structure layer ES of the electronic device ED may include an electrostatic discharge (ESD) protection element. The ESD protection element may be electrically connected between I/O points IO1 and IO2 and can be used to eliminate static electricity. Specifically, as shown in Figure 7, the ESD protection element may be electrically connected to the electrical connection path between I/O points IO1 and IO2, and may be electrically connected to the ground point GP. Figure 6 exemplarily illustrates the structure of the ESD protection element of this embodiment. The structure and electrical connection method of the ESD protection element of this embodiment are described below. It should be noted that the electrostatic discharge (ESD) protection element of this embodiment may include any suitable structure or be electrically connected to I/O points IO1 and IO2 in any suitable manner, and is not limited to the structure shown in Figure 6.

As shown in Figure 6, the electrostatic discharge (ESD) protection element may include a thin-film transistor T4 and a thin-film transistor T5. Thin-film transistor T4 includes a gate electrode GE1, a semiconductor layer SM1, a drain electrode DE1, and a source electrode SE1. Thin-film transistor T5 includes a gate electrode GE2, a semiconductor layer SM2, a drain electrode DE2, and a source electrode SE2. The source electrode SE1 of thin-film transistor T4 is electrically connected to the semiconductor layer SM1 and the gate electrode GE1, while the drain electrode DE2 of thin-film transistor T5 is electrically connected to the semiconductor layer SM2 and the gate electrode GE2. The component structure layer ES may include an insulating layer IL4, a conductive layer CL5 disposed on the insulating layer IL4, an insulating layer IL5 disposed on the insulating layer IL4 and covering the conductive layer CL5, a semiconductor layer SM1 and a semiconductor layer SM2 disposed on the insulating layer IL5, and a component structure layer ES disposed on the insulating layer IL5 and covering the conductive layer CL5. An insulating layer IL6 covers semiconductor layers SM1 and SM2, wherein a conductive layer CL5 may form gate electrodes GE1 and GE2, and a conductive layer CL4 may form drain electrodes DE1, source electrodes SE1, DE2, and SE2, but is not limited thereto. The thin-film transistors T4 and T5 of this embodiment may be bottom-gate type thin-film transistors, but are not limited thereto. As shown in Figure 6, the source electrode SE1 of the thin-film transistor T4 can be electrically connected between the bonding pads SD1 and SD2 through the conductive layer CL2, while the drain electrode DE2 of the thin-film transistor T5 can be electrically connected to the bottom metal layer UM3 and the bonding pad SD3 through the conductive layer CL2. Specifically, a portion of the conductive layer CL2 can be filled into the through-hole V3 that passes through the insulating layers IL1 and IL2 and contacts the source electrode SE1, thereby electrically connecting the thin-film transistor T4 between the bonding pads SD1 and SD2. Furthermore, another portion of the conductive layer CL2 can be filled into the through-hole V3 and contact the drain electrode DE2, and also filled into the through-hole V2 and contact the bottom metal layer UM3. The bonding pad SD3 can be grounded, that is, electrically connected to the grounding point GP shown in Figure 7. Therefore, the ESD protection element can be grounded through the conductive layer CL2, the bottom metal layer UM3, and the bonding pad SD3. Moreover, although not shown in Figure 6, the source electrode SE1 of the thin-film transistor T4 can be electrically connected to the source electrode SE2 of the thin-film transistor T5, and the drain electrode DE1 of the thin-film transistor T4 can be electrically connected to the drain electrode DE2 of the thin-film transistor T5. The material of the bottom metal layer UM3 can refer to the materials of the bottom metal layers UM1 and UM2 described above. The material of the bonding pad SD3 can be the same as that of the bonding pads SD1 and SD2. With the above structural design, static electricity on the electrical connection path between I/O points IO1 and IO2 can be eliminated by the electrostatic discharge (ESD) protection component, thereby reducing the impact of static electricity on the electronic device ED.

According to this embodiment, in the normal direction of the electronic device ED, the electrostatic discharge (ESD) protection element may not overlap with the side SS of the chip CP, or in other words, may not be positioned corresponding to the side SS of the chip CP. Furthermore, in some embodiments, the ESD protection element may also not overlap with the bonding pads SD1, SD2, and SD3. Therefore, in some embodiments, as shown in FIG. 6, the ESD protection element may be positioned in the second region R2 at a location not corresponding to bonding pads SD2 and SD3. In some embodiments, as shown in FIG. 7, the ESD protection element may be positioned in the third region R3 at a location not corresponding to bonding pad SD1.

Although not shown in Figures 6 and 7, the component structure layer ES of the electronic device ED may also include other electronic components EL (such as the driving element DU shown in Figure 1), electrically connected between I/O points IO1 and IO2, or electrically connected between bonding pads SD1 and SD2. Furthermore, the arrangement of the first opening ST1 and/or the second opening ST2 shown in Figure 7 is merely exemplary and is not limited to this embodiment. The structural features of other components and/or film layers of the electronic device ED shown in Figure 6 can be found above and will not be repeated here.

Please refer to Figure 8, which is a cross-sectional schematic diagram of an electronic device according to the fifth embodiment of this disclosure. According to this embodiment, the method for forming the electronic device ED may include first forming a package structure including a chip CP and a package layer EN disposed around the chip CP, and then forming a circuit structure layer CS on the package structure. For example, a component structure layer ES may be formed on the aforementioned package structure first, and a redistribution structure layer RDL may be formed on the component structure layer ES, but this is not a limitation. In other words, the component structure layer ES may be disposed between the chip CP and the redistribution structure layer RDL. Furthermore, the electronic device ED may also include a buffer layer INL disposed between the package layer EN and the circuit structure layer CS. It should be noted that in some embodiments, the buffer layer INL may comprise a structure formed by stacking conductive and insulating layers as another redistribution layer. External electronic components may be electrically connected to the conductive layer in the redistribution layer RDL via bonding pad SD2 and bottom metal layer UM2, and electrically connected to electronic components EL in the component structure layer ES via the conductive layer in the redistribution layer RDL, for example, electrically connected to the drain electrode DE or source electrode SE (e.g., drain electrode DE, but not limited thereto) of electronic component EL (driver element DU). For the sake of simplicity, Figure 8 uses a single conductive layer CL to represent the conductive layer in the redistribution structure layer RDL, and a single insulating layer IL to represent the insulating layer in the redistribution structure layer RDL, but this embodiment is not limited thereto. The drain electrode DE or source electrode SE (e.g., source electrode SE, but not limited thereto) of the electronic component EL (driver component DU) can be electrically connected to the bottom metal layer UM1 and the conductive layer CL1 through the conductive layer CL in the redistribution structure layer RDL, thereby electrically connecting the chip CP to external electronic components.

In this embodiment, the component structure layer ES may include at least one first opening ST1, wherein the first opening ST1 may overlap with the side SS of the chip CP in the normal direction of the electronic device ED. That is, the first opening ST1 may correspond to the first region R1. In the normal direction of the electronic device ED, the first opening ST1 may surround the chip CP along the side SS, but is not limited thereto. In some embodiments, the first opening ST1 may extend along at least a portion of the side SS. Furthermore, in this embodiment, the conductive layer CL in the redistribution line structure layer RDL may be filled into the first opening ST1, that is, the support element SP1 disposed in the first opening ST1 may include the material of the conductive layer CL, such as a metal material, but is not limited thereto. The structural features of each film layer or element in the component structure layer ES can be referred to the content of the above embodiments, and will not be repeated here. Furthermore, the surface of the redistribution line structure layer RDL in this embodiment may include a groove RS, wherein the groove RS may at least partially overlap with the side SS of the chip CP in the normal direction of the electronic device ED, but is not limited thereto.

Please refer to Figure 9, which is a cross-sectional schematic diagram of the electronic device according to the sixth embodiment of this disclosure. One of the main differences between the electronic device ED shown in Figure 9 and the electronic device ED shown in Figure 8 lies in the structure of the support element SP1. Specifically, as shown in Figure 9, in the electronic device ED, a portion of the insulating layer (denoted as insulating layer IL) and conductive layer (denoted as conductive layer CL) of the redistribution line structure layer RDL can be filled into the first opening ST1. In this case, the support element SP1 disposed within the first opening ST1 may include a combination of conductive and insulating materials. For example, the support element SP1 may include a combination of metallic and organic insulating materials, but is not limited thereto. The structural features of other components or films in the electronic device ED of this embodiment can be found above, and therefore will not be repeated here.

In summary, this disclosure provides an electronic device including a chip and a circuit structure layer overlapping the chip, wherein the circuit structure layer includes a redistribution line structure layer and a component structure layer. At least one of the redistribution line structure layer and the component structure layer includes at least one opening, wherein the opening may overlap at least a portion of at least one side of the chip in the normal direction of the electronic device. This reduces the likelihood of damage to components or film layers in the electronic device due to stress, thereby improving the reliability of the electronic device. The above description is merely an embodiment of this disclosure, and all equivalent variations and modifications made within the scope of the claims of this disclosure should be considered within the scope of this disclosure.

CL1, CL2, CL3, CL4, CL: Conductive layer; CP: Chip; CR: Channel region; CS: Circuit structure layer; DE, DE1, DE2: Drain electrode; DR: Drain region; DU: Driver component; ED: Electronic device; EL: Electronic component; EN: Package layer; ES: Component structure layer; ESD: Electrostatic discharge protection component; GE, GE1, GE2: Gate electrode; GP: Ground point; IN: Signal input terminal; INL: Buffer layer; INL2, IL3, IL1, IL2, IL4, IL5, IL6, IL: Insulation layer; IO1, IO2: I/O point; DMX: Demultiplexer; R1: First... Region R2: Region R3: Region RDL: Redistribution Line Structure Layer RS: Groove S1: Side Surface S2, S3, S4: Surface SD1, SD2, SD3: Bonding Pads SE, SE1, SE2: Source Electrodes SM, SM1, SM2: Semiconductor Layers SP1, SP2: Support Elements SR: Source Region SS: Side ST1: First Opening ST2: Second Opening T1, T2, T3, T4, T5: Thin Film Transistors UM1, UM2, UM3: Bottom Metal Layer V1, V2, V3: Through-hole WL1, WL2: Trace Z: Direction A-A’: Tangent

Figure 1 is a cross-sectional schematic diagram of the electronic device according to the first embodiment of this disclosure. Figure 2 is a top schematic diagram of the component configuration of the electronic device according to the first embodiment of this disclosure. Figure 3 is a cross-sectional schematic diagram of the electronic device according to the second embodiment of this disclosure. Figure 4 is a top schematic diagram of the component configuration of the electronic device according to the third embodiment of this disclosure. Figure 5 is an equivalent circuit diagram of the electronic components of the third embodiment of this disclosure. Figure 6 is a cross-sectional schematic diagram of the electronic device according to the fourth embodiment of this disclosure. Figure 7 is a top schematic diagram of the component configuration of the electronic device according to the fourth embodiment of this disclosure. Figure 8 is a cross-sectional schematic diagram of the electronic device according to the fifth embodiment of this disclosure. Figure 9 is a cross-sectional schematic diagram of the electronic device according to the sixth embodiment of this disclosure.

CL1, CL2, CL3, CL4: Conductive layers; CP: Chip; CR: Channel region; CS: Circuit structure layer; DE: Drain electrode; DR: Drain region; DU: Driver element; ED: Electronic device; EL: Electronic component; EN: Package layer; ES: Component structure layer; GE: Gate electrode; INL: Buffer layer; INL2, IL3, IL1, IL2, IL4, IL5, IL6: Insulation layer; R1: First region. 2: Second region R3: Third region RDL: Redistribution line structure layer RS: Groove S1: Side surface S2, S3, S4: Surface SD1, SD2: Bonding pad SE: Source electrode SM: Semiconductor layer SP1, SP2: Support element SR: Source region SS: Side ST1: First opening ST2: Second opening UM1, UM2: Bottom metal layer V1, V2: Through hole Z: Direction A-A’: Tangent

Claims (9)

An electronic device includes: a chip; and a circuit structure layer overlapping the chip, the circuit structure layer including a redistribution structure layer and a component structure layer, the redistribution structure layer and the component structure layer being electrically connected to the chip; wherein at least one of the redistribution structure layer and the component structure layer includes at least one opening, the at least one opening overlapping one side of the chip in a normal direction of the electronic device; wherein the at least one opening includes a first opening of the component structure layer and a second opening of the redistribution structure layer, and the first opening overlapping the second opening in the normal direction of the electronic device. The electronic device according to claim 1 further includes an encapsulation layer disposed around the chip. According to the electronic device of claim 1, the redistribution line structure layer includes at least one insulating layer and at least one conductive layer, and a portion of the at least one insulating layer extends into the first opening. According to the electronic device of claim 1, the redistribution line structure layer includes at least one insulating layer and at least one conductive layer, and a portion of the at least one conductive layer extends into the first opening. The electronic device according to claim 1 further includes a buffer layer, wherein the component structure layer is disposed between the buffer layer and the redistribution structure layer. According to claim 1, the surface of the redistribution line structure layer has at least one groove, which overlaps the side of the wafer in the normal direction of the electronic device. The electronic device according to claim 1 further includes a support element disposed in the at least one opening, the support element comprising an insulating material, a metallic material, or a combination thereof. The electronic device according to claim 1, wherein the element structure layer includes a thin-film transistor element. According to claim 8, in the electronic device, the thin-film transistor element does not overlap the side of the wafer in the normal direction of the electronic device.