TW202422817A - Electronic device - Google Patents

Abstract

The present disclosure provides an electronic device, comprising: a substrate structure with a conductive via pattern and a dummy via pattern therein; a control unit electrically connected to the conductive via pattern; a first circuit structure electrically connected to the conductive via pattern; and an electronic unit electrically connected to the control unit through the first circuit structure, wherein the dummy via pattern is electrically insulated from the first circuit structure.

Description

Electronic devices

The present invention relates to an electronic device, and more particularly to an electronic device including a dummy through-hole pattern.

As the application of electronic devices continues to advance, display technology is also developing rapidly. However, in the face of different manufacturing technology conditions, the requirements for the structure and quality of electronic devices are getting higher and higher, making the manufacturing of electronic devices face different challenges.

In the packaging technology of electronic components, fan-out wafer level package (FOWLP) and fan-out panel level package (FOPLP) are to form electronic components and redistribution layers on wafer-level substrates or panel-level substrates, followed by packaging and cutting steps to form a large number of packaged components at the same time. However, in such packaged components, due to the different thickness of the film layer on both sides of the substrate, it is easy to cause the substrate to warp due to uneven stress, affecting the yield of electronic components.

In summary, although the existing packaging structures can generally meet their original intended uses, they still do not fully meet the needs in all aspects. For example, how to prevent uneven stress while manufacturing a packaging structure that meets electrical requirements is still a topic that the industry is committed to researching. Therefore, the research and development of electronic devices requires continuous updates and adjustments to solve the various problems faced by the manufacture of electronic devices.

An electronic device is characterized in that it includes: a substrate structure having a conductive through-hole pattern and a dummy through-hole pattern; a control unit electrically connected to the conductive through-hole pattern; a first circuit structure electrically connected to the conductive through-hole pattern; and an electronic unit electrically connected to the control unit through the first circuit structure, wherein the dummy through-hole pattern is electrically insulated from the first circuit structure.

A method for forming an electronic device is characterized in that it includes: forming a substrate structure having a conductive through-hole pattern and a virtual through-hole pattern; forming a control unit electrically connected to the conductive through-hole pattern; forming a first circuit structure electrically connected to the conductive through-hole pattern; and arranging an electronic unit on the first circuit structure, and the electronic unit is electrically connected to the control unit through the first circuit structure, wherein the virtual through-hole pattern is electrically insulated from the first circuit structure.

The following disclosure provides many different embodiments or examples to show different components of the embodiments of the present invention. The following will disclose specific examples of the components of this specification and their arrangement to simplify the disclosure. Of course, these specific examples are not used to limit the disclosure. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which an additional component can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in the disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, to facilitate description of the relationship between one element or component and another element or component in the drawings, spatially relative terms may be used, such as "under," "below," "lower," "above," "upper," and the like. In addition to the orientation depicted in the drawings, spatially relative terms also cover different orientations of the device in use or operation. When the device is turned to a different orientation (for example, rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person skilled in the art to which the present disclosure belongs. It is understood that these terms, such as terms defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure embodiments.

Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

It should be understood that the following embodiments can replace, combine, or reorganize features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. As long as the features between the embodiments do not violate the spirit of the invention or conflict with each other, they can be arbitrarily recombined and used.

Some embodiments of the present invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

As used herein, the term "substantially" means that a given amount of value may vary based on a particular technology node associated with the target semiconductor device. In some embodiments, based on a particular technology node, the term "substantially" may mean that a given amount of value is within a range of, for example, ±10% of a target (or desired) value.

It should be understood that the electronic device disclosed herein may include a semiconductor device, a semiconductor package device, a display device, a sensor device, an antenna device, a radar device, a lidar device, a touch display device, a curved display device, or a free shape display device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include a light-emitting diode, a liquid crystal, fluorescence, phosphor, other suitable display media, or a combination thereof, but is not limited thereto. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a sub-millimeter light-emitting diode (mini-light-emitting diode, mini LED), a micro-light-emitting diode (micro-LED), a quantum dot (QDs) light-emitting diode (such as QLED, QDLED), other suitable materials or any combination of the above, but not limited to this. The display device may include, for example, a spliced display device, but not limited to this. The concepts or principles disclosed herein may also be applied to non-self-luminous liquid crystal displays (LCD), but not limited to this.

The antenna device may be, for example, a 5G antenna, a Beyond-5G antenna, a 6G antenna, a liquid crystal antenna, a phased array antenna, a low-orbit satellite antenna, or other types of antenna types, but is not limited thereto. The antenna device may, for example, include a spliced antenna device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device, or a spliced device. The electronic device disclosed herein may, for example, be a display device, but is not limited thereto.

The present disclosure provides an electronic device and a method for forming the same. By forming a virtual through-hole pattern in a substrate structure, the substrate structure can be prevented from warping due to uneven stress. Compared with the known packaging structure of electronic devices, the electronic device disclosed herein can maintain the stability of the substrate structure without affecting the electrical requirements. The packaging structure formed by such an electronic device can enhance the function of the electronic unit through the through-hole structure and the control unit. In addition, the formation of a virtual through-hole structure that is electrically insulated from the circuit structure can be integrated into the manufacturing process of the conductive through-hole pattern. Therefore, the formation method disclosed herein can manufacture an electronic device with better electrical and structural performance, or does not require complex manufacturing steps, thereby saving manufacturing costs.

FIG. 1 is a schematic cross-sectional view of an electronic device 10 according to some embodiments of the present disclosure. The electronic device 10 includes a substrate structure 100, a control unit 110, a first circuit structure 120, and an electronic unit 130. The substrate structure 100 has a conductive via pattern 101 and a virtual via pattern 102. The control unit 110 is electrically connected to the conductive via pattern 101, the first circuit structure 120 is electrically connected to the conductive via pattern 101, and the electronic unit is electrically connected to the control unit 110 through the first circuit structure 120. The virtual via pattern 102 is electrically insulated from the first circuit structure 120. According to some embodiments, the electronic device 10 may include at least one control unit 110 and at least one electronic unit 130, and the number is not limited.

As shown in FIG. 1 , the substrate structure 100 may include a substrate material 100M and a conductive via pattern 101 and a dummy via pattern 102 disposed in the substrate material 100M. The substrate material 100M may include a hard or soft material, such as glass, ceramic, polyimide (PI), polyethylene terephthalate (PET), steel plate, silicon base, other suitable materials or a combination of the above materials, but is not limited thereto.

The substrate structure 100 may include a transparent material or a translucent material. For example, in some embodiments, the substrate structure 100 has a through-glass via (TGV) structure, which includes a substrate material 100M having an inorganic and amorphous glass material, and a conductive through-hole material is provided in the substrate material 100M. For example, the substrate structure 100 including a transparent material or a translucent material can be used for processing from the other side of the component to be processed, such as laser processing, and is conducive to the alignment of the circuit structures and components on both sides, but is not limited thereto. According to some embodiments, the substrate structure 100 may include an opaque substrate, and the processing of the other side can be performed by setting an alignment mark.

In some embodiments, the conductive via pattern 101 includes a first conductive via 101A and a second conductive via 101B. As shown in FIG. 1 , the first conductive via 101A can be electrically connected to the control unit 110 through the first circuit structure 120, and the second conductive via 101B can be electrically connected to the electronic unit 130 through the portion of the first circuit structure 120 that is separated from the control unit 110. However, the present disclosure is not limited thereto. In other embodiments, the control unit 110 and the electronic unit 130 can be electrically connected to a common conductive via through the first circuit structure 120.

By providing a virtual through hole pattern 102 in the substrate structure 100, the substrate structure 100 can be prevented from warping due to uneven stress. Compared with the known packaging structure of the electronic device, the electronic device 10 including the virtual through hole pattern 102 can maintain the stability of the substrate structure 100 without affecting the electrical requirements of the conductive through hole pattern 101. Although the virtual through hole pattern 102 penetrating the substrate material M is shown in FIG. 1, the present disclosure is not limited thereto. In some embodiments, the virtual through hole pattern 102 is buried in the substrate material M, and the top surface or the bottom surface of the virtual through hole pattern 102 is covered by the substrate material M. It should be understood that the present disclosure does not specifically limit the number, cross-sectional shape, and horizontal position of the through holes included in the virtual through hole pattern 102. For example, the conductive through hole 101 may be an I/O (input/output point) of an electronic device. When the number of I/Os on the substrate is uneven, it may cause uneven stress on the substrate, thereby causing warping. Therefore, the stress can be balanced by elastically setting the virtual through hole pattern 102, but it is not limited to this.

The material of the conductive via pattern 101 may include, for example, copper (Cu), tin (Sn), nickel (Ni), silver (Ag), gold (Au), titanium (Ti), molybdenum (Mo), tungsten (W), aluminum (Al), other suitable conductive materials, or a combination thereof, but not limited thereto. The virtual via pattern 102 may include the same or similar material as the conductive via pattern 101, but the present disclosure is not limited thereto. In some embodiments, at least a portion of the virtual via pattern 102 includes an insulating material. For example, parasitic capacitance may be reduced or electrical interference to nearby conductive via patterns 101 or circuit structures may be reduced, but not limited thereto.

The control unit 110 may be an element for controlling the electronic unit 130, such as a control element including a transistor. In some embodiments, the control unit 110 may be a thin film transistor (TFT) element. The control element 110 may include a semiconductor layer 112, a gate 114, and a source/drain 116. It should be noted that the state of the control unit 110 is not limited in the present disclosure. For example, the control unit 110 may have a top-gated, a bottom-gated, or other suitable states, but is not limited thereto. In some embodiments, as shown in FIG. 1, the control element 110 may be located above the substrate structure 100, and the control unit is located between the substrate structure 100 and the first circuit structure 120. In addition, the semiconductor layer 112, the gate 114, and the source/drain 116 may be completely or partially embedded in the first insulating layer 106 and the second insulating layer 108. In some embodiments, as shown in FIG. 1 , the top surface of the source/drain 116 is exposed above the second insulating layer 108.

The material of the semiconductor layer 112 may include amorphous silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), other suitable semiconductor materials, or a combination thereof, but not limited thereto. The material of the gate 114 may include Al, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but not limited thereto. The material of the source/drain 116 may include Al, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but not limited thereto. In some embodiments, the first insulating layer 106 and the second insulating layer 108 may include the same or similar materials. The materials of the first insulating layer 106 and the second insulating layer 108 may include silicon nitride ( _SiNx ), silicon oxide ( _SiOx ), silicon oxynitride ( _SiOxNy ), aluminum oxide ( _AlxOy ), other suitable insulating materials, or a combination thereof, but are not limited thereto. According to some embodiments, the thickness of the first insulating layer 106 and the second insulating layer 108 is greater than or equal to 500 nanometers ( _nm ) _and less than or equal to 5000 nanometers.

In some embodiments, the electronic device 10 further includes a buffer layer 104 disposed between the substrate structure 100 and the control element 110. As shown in FIG. 1, the buffer layer 104 may cover the top surface of the dummy via pattern 102. Since the material (e.g., copper) in the conductive via pattern 101 may diffuse to the control element 110 at high temperature, by providing the buffer layer 104, the diffusion of the above material can be substantially blocked during the high temperature process to prevent the control element 110 from being contaminated. In some embodiments, the buffer layer 104 has a thickness between about 400 nanometers (nm) and about 1500 nanometers (nm) to achieve the above purpose. In some embodiments, as shown in FIG. 1 , the first circuit structure 120 penetrates the buffer layer 104 to be electrically connected to the conductive via pattern 101. The material of the buffer layer 104 may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable insulating materials, or a combination thereof, but is not limited thereto.

In some embodiments, the electronic device 10 further includes a stress adjustment layer 105 disposed on the substrate structure 100 and located on a side of the substrate structure 100 opposite to the control unit 110. As shown in FIG. 1 , the stress adjustment layer 105 may cover the bottom surface of the dummy through hole pattern 102. By disposing the stress adjustment layer 105 on the substrate structure 100, the stress balance of the substrate structure 100 may be further maintained when depositing components (such as the control unit 110, the first circuit structure 120, and the electronic unit 130) on the other side of the substrate structure 100 to prevent the substrate structure 100 from warping. In some embodiments, the thermal expansion coefficient of the stress adjustment layer 105 is close to that of the insulating layer on the other side of the substrate structure 100, and the insulating layer on the other side includes, for example, the buffer layer 104, the first insulating layer 106, and the second insulating layer 108. The material of the stress adjustment layer 105 may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable insulating materials, or a combination thereof, but is not limited thereto. The thickness of the stress adjustment layer 105 may be between 800 nanometers and about 3000 nanometers.

Referring to FIG. 1 , the first circuit structure 120 is surrounded by a first dielectric layer 122. The material of the first circuit structure 120 may include a material similar to the conductive via pattern 101, such as Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but not limited thereto. The material of the first dielectric layer 122 may include polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), build-up material ABF (Ajinomoto Build-up Film), epoxy resin, other suitable dielectric materials, or a combination thereof, but not limited thereto.

In some embodiments, the electronic device 10 further includes an alignment component 124 disposed on the first circuit structure 120 and electrically connected to the electronic unit 130. As shown in FIG. 1 , the alignment component 124 may have a groove facing the electronic unit 130. The alignment component 124 may be used to align the electronic unit 130 to a specified position above the first circuit structure 120. In addition, by increasing the side stress that the electronic unit 130 can withstand, the groove of the alignment component 124 can be used to strengthen the bonding strength between the first circuit structure 120 and the electronic unit 130. The alignment component 124 may include a material similar to the first circuit structure 120, but is not limited thereto. According to some embodiments, the alignment component 124 may be, for example, a conductive bump (under bump metallization, UBM), but is not limited thereto.

The electronic unit 130 and the first circuit structure 120 may be electrically connected via a bonding material 134. In some embodiments, as shown in FIG. 1 , the bonding material 134 is disposed on the alignment component 124 on the first circuit structure 120, and the electronic unit 130 having the electrical connection portion 132 is disposed on the bonding material 134. In some embodiments, a diffusion region 136 is provided between the electrical connection portion 132 and the bonding material 134, and the diffusion region 136 includes elements from the electrical connection portion 132 and the bonding material 134.

The material of the bonding material 134 may include, for example, Au, Sn, Al, Cu, Ti, Ag, Ga, other suitable metals, or a combination thereof, but is not limited thereto. In some embodiments, the material of the bonding material 134 includes a mixture of particles of the above metals and an organic material. The material of the electrical connection portion 132 includes, for example, Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but is not limited thereto.

Depending on the application of the electronic device 10, the electronic unit 130 can be a variety of components. For example, the electronic unit 130 can be a chip, a die, an integrated circuit, a diode, a capacitor, a resistor, an inductor, a sensor, other suitable components, or a combination thereof, but is not limited thereto. The electronic device 10 further includes a protective layer 140 surrounding the electronic unit 130. For example, the protective layer 140 can prevent moisture from affecting the electronic unit 130 or the circuit structure. According to some embodiments, the protective layer 140 can contact at least two sides of the electronic unit 130. According to some embodiments, at least one surface of the electronic unit 130 can be exposed without contacting the protective layer. The material of the protective layer 140 may include silicone resin, epoxy resin, acrylic adhesive, other suitable materials, or a combination thereof, but is not limited thereto.

According to some embodiments, the protective layer 140 may contact a side surface 122SS of the insulating layer 122. The protective layer 140 may also contact a top surface 108TS of the insulating layer 108. Through the above configuration, the bonding capability between different film layers may be improved, thereby improving the reliability of the electronic device, but the present invention is not limited thereto.

In some embodiments, the electronic device 10 further includes a second circuit structure 150 disposed on the substrate structure 100 and opposite to the first circuit structure 120. In some embodiments, the dummy via pattern 102 is electrically insulated from the second circuit structure 150. As shown in FIG. 1 , for example, the dummy via pattern 102 and the second circuit structure 150 may be separated by a stress adjustment layer 105. In some embodiments, the second circuit structure 150 penetrates the stress adjustment layer 105 to be electrically connected to the conductive via pattern 101. In some embodiments, the first circuit structure 120 and the second circuit structure 150 are electrically connected through the conductive via pattern 101. In some embodiments, the second circuit structure 150 is surrounded by a second dielectric layer 152. The second dielectric layer 152 may include a material similar to the first dielectric layer 122, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, ABF, other suitable dielectric materials, or a combination thereof, but is not limited thereto.

In some embodiments, the electronic device 10 further includes an alignment component 154 disposed on the second circuit structure 150. As shown in FIG. 1, the alignment component 154 may have a groove facing away from the substrate structure 100. The alignment component 154 can be used to align the electronic device 10 to a specified position of an external circuit. In addition, the groove of the alignment component 154 can be used to strengthen the bonding strength between the electronic device 10 and the external circuit. The alignment component 154 may include a material similar to the alignment component 124 or the second circuit structure 150, but is not limited thereto. In some embodiments, as shown in FIG. 1, a bonding material 156 is disposed on the alignment component 154 on the second circuit structure 150, and the bonding material 156 can be used to bond the electronic device 10 to an external circuit. The above-mentioned external circuit may include a printed circuit board (PCB) and a flexible printed circuit board (FPC). For example, the first circuit structure 120 and the second circuit structure 150 may be, for example, a redistribution layer (RDL). Through the design of the redistribution structure, the I/O may be flexibly designed or the fan-out range of the circuit structure may be increased. According to some embodiments, the alignment component 124 or the alignment component 154 may have a convex surface, a flat surface, a concave surface or a curved surface but is not limited thereto. According to some embodiments, the surface of the alignment component 124 may be coplanar or in a different plane with the surface of the dielectric layer 122. In detail, the surface of the alignment component 124 may be higher than the surface of the dielectric layer 122 or the surface of the alignment component 124 may be lower than the surface of the dielectric layer 122. According to some embodiments, the surface of the alignment member 154 may be coplanar with or different from the surface of the dielectric layer 152. In detail, the surface of the alignment member 154 may be higher than the surface of the dielectric layer 152 or the surface of the alignment member 154 may be lower than the surface of the dielectric layer 152.

FIG. 2 is a cross-sectional view of an electronic device array 20′ according to some embodiments of the present disclosure. FIG. 2 shows an electronic device array 20′ including two electronic devices 20, and each electronic device 20 has an electronic unit 130 and a corresponding first circuit structure 120, a control unit 110, and a second circuit structure 150. In fact, the present disclosure does not limit the number of electronic devices 20 included in the electronic device array 20′ and the configuration of each electronic device 20. For example, the electronic device 20 may have a configuration similar to the electronic device 10 described with reference to FIG. 1, or may have a configuration in which the control unit 110 and the electronic unit 130 are located on different sides of the substrate structure 100 (as shown in FIG. 3). In addition, depending on the design requirements of the electronic device array 20', each electronic unit 130 can be the same, similar, or different types of components, which is not limited by the present disclosure. In some embodiments, the circuit structures of adjacent electronic devices 20 have connected conductive lines. Similar components shown in Figures 1 and 2 are represented by the same or similar reference numerals and can be formed with the same or similar materials and configurations. For the sake of simplicity, their detailed description is omitted here.

FIG. 3 is a cross-sectional view of an electronic device 30 according to some other embodiments of the present disclosure. The difference from the electronic device 10 shown in FIG. 1 is that the control unit 110 and the electronic unit 130 of the electronic device 30 are located on different sides of the substrate structure 100. That is, as shown in FIG. 3, the control unit 110 is located below the substrate structure 100, and the substrate structure 100 is located between the control unit 110 and the first circuit structure 120. For example, through the above arrangement, the control unit 110 can be prevented from interfering with the electronic unit 130 during operation, but the present invention is not limited thereto.

In addition, in the embodiment shown in FIG. 3 , since the buffer layer 104 is disposed between the substrate structure 100 and the control unit 110, the buffer layer is also located below the substrate structure 100. The stress adjustment layer 105 can be disposed on the side of the substrate structure 100 opposite to the control unit 110, so that the stress adjustment layer 105 is located between the substrate structure 100 and the electronic unit 130. Similar elements shown in FIGS. 1 and 3 are represented by the same or similar reference numerals and can be formed with the same or similar materials and configurations, and their detailed description is omitted here for simplicity.

FIG. 4 is a cross-sectional view of an electronic device 40 according to some other embodiments of the present disclosure. The difference from the electronic device 10 shown in FIG. 1 is that a conductive material 160 is disposed between the substrate structure 100 and the first circuit structure 120 of the electronic device 40. The substrate structure 100 and the first circuit structure 120 of the electronic device 40 are electrically connected through the conductive material 160. The conductive material 160 may include a material similar to the first circuit structure 120 and the second circuit structure 150, but is not limited thereto. In addition, similar elements shown in FIGS. 1 and 4 are represented by the same or similar reference numerals and may be formed with the same or similar materials and configurations, and their detailed description is omitted here for simplicity. By forming such an electronic device 40 , the complexity of the manufacturing process of respectively forming the first circuit structure 120 and the second circuit structure 150 on the upper and lower sides of the substrate structure 100 can be reduced.

5A to 5F are cross-sectional views showing various stages in the manufacturing process of an electronic device according to some embodiments of the present disclosure.

5A, a substrate structure 100 having a conductive via pattern 101 and a dummy via pattern 102 is first formed. In some embodiments, a plurality of through holes are formed in the substrate material 100M using a removal process, and then materials for the conductive via pattern 101 and the dummy via pattern 102 are deposited in the through holes.

The removal process may include laser processing, a suitable etching process, or a combination thereof, but is not limited thereto. In an embodiment where the thickness of the substrate material 100M is relatively thick, laser processing may be performed on both sides of the substrate material 100M to form a through hole with a larger diameter at the top and bottom and a smaller diameter in the middle. In this case, the conductive through hole pattern 101 and the virtual through hole pattern 102 formed have a larger diameter at the top and bottom and a smaller diameter in the middle, as shown in FIG. 5A.

The process for depositing the conductive via pattern 101 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or a combination thereof, but not limited thereto. In some embodiments, the formation of the conductive via pattern 101 includes first depositing a seed layer in the through hole, and then depositing a conductive material on the seed layer. The material of the seed layer includes titanium (Ti), copper (Cu), other suitable conductive materials, or a combination thereof, but not limited thereto. The conductive material includes, for example, Cu, Sn, Ni, Ag, Au, Ti, Mo, W, other suitable conductive materials, or a combination thereof, but not limited thereto.

The process for depositing the dummy via pattern 102 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or a combination thereof, but is not limited thereto. In some embodiments, the conductive via pattern 101 and the dummy via pattern 102 are formed simultaneously in a deposition process. In fact, the dummy via pattern 102 may also be formed in a deposition process different from that of the conductive via pattern 101, and the dummy via pattern 102 may also include a material different from that of the conductive via pattern 101.

Next, as shown in FIG. 5A , a buffer layer 104 covering the top surface of the dummy via pattern 102 may be formed on the substrate structure 100 before forming the control unit. In this way, the diffusion of the material from the conductive via pattern 101 to the control element 110 may be prevented in the subsequent high-temperature process. Furthermore, a stress adjustment layer 105 may be formed on the substrate structure 100 and on the side opposite to the buffer layer 104, wherein the thickness of the stress adjustment layer 105 is greater than that of the buffer layer 104.

The process for depositing the buffer layer 104 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto. The process for depositing the stress adjustment layer 105 may be similar to the process for depositing the buffer layer 104, including, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto.

Then, a control unit 110 electrically connected to the conductive via pattern 101 is formed. Referring to FIGS. 5A and 5B, a semiconductor layer 112 of the control unit 110 may first be formed above the substrate structure 100, for example, on the buffer layer 104. In an embodiment where the control unit 110 is a transistor, the semiconductor layer 112 may include a channel layer. The formation of the semiconductor layer 112 may include a deposition process and a patterning process. The deposition process may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto. The patterning process includes a suitable lithography and/or etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, or a combination thereof, but not limited thereto. The etching process may include dry etching (e.g., RIE etching), wet etching, other etching methods, or a combination thereof, but not limited thereto.

Next, a first insulating layer 106 may be formed on the semiconductor layer 112. The process for forming the first insulating layer 106 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto. Next, a gate 114 and a source/drain 116 may be formed on the first insulating layer 106. The process for forming the gate 114 and the source/drain 116 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or a combination thereof, but is not limited thereto. Between the formation of the gate 114 and the source/drain 116, the second insulating layer 108 may be formed on the first insulating layer 106 and the gate 114. In some embodiments, a portion of the first insulating layer 106 and the second insulating layer 108 are removed by an etching process to expose the semiconductor layer 112, and then a conductive material for the source/drain 116 is deposited in the openings left by removing the first insulating layer 106 and the second insulating layer 108. The second insulating layer 108 may be formed by a deposition process similar to that of the first insulating layer 106, which is not described in detail for simplicity.

It should be understood that the present disclosure does not limit the formation order of the various parts of the control element 110 (such as the semiconductor layer 112, the gate 114, and the source/drain 116) and the various insulating layers (such as the first insulating layer 106 and the second insulating layer 108). A person skilled in the art can adjust the formation order of the above-mentioned film layers according to the requirements of the process. In addition, it should be understood that the present disclosure does not limit when the stress adjustment layer 105 is formed. A person skilled in the art can form the stress adjustment layer 105 before, during, or after the formation of the control unit 110 according to the requirements of the process.

5C, a first circuit structure 120 electrically connected to the conductive via pattern 101 may be formed, and the dummy via pattern 102 is electrically insulated from the first circuit structure 120. Before, during, or after the formation of the first circuit structure 120, a dielectric material may be deposited to form a first dielectric layer 122 surrounding the first circuit structure 120. The process for depositing the first circuit structure 120 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable processes, or a combination thereof, but is not limited thereto. The process for forming the first dielectric layer 122 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto.

As shown in FIG. 5C , in order to arrange the electronic element 130 on the first circuit structure 120, an alignment member 124 having a groove facing away from the first circuit structure 120 may be formed on the first circuit structure 120. The alignment member 124 may be formed by forming an opening on the first dielectric layer 122 to expose the first circuit structure 120 and forming a conductive material in the opening. The formation of the alignment member 124 may include a deposition process and a patterning process.

The deposition process of the alignment feature 124 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto. The patterning process of the alignment feature 124 may include a suitable lithography and/or etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, or a combination thereof, but is not limited thereto. The etching process may include dry etching (e.g., RIE etching), wet etching, other etching methods, or a combination thereof, but is not limited thereto. In some embodiments, the formed alignment feature 124 may have a top portion that is higher than the top surface of the first dielectric layer 122.

Next, referring to FIG. 5D , the electronic unit 130 is disposed on the first circuit structure 120, and the electronic unit 130 is electrically connected to the control unit 110 through the first circuit structure 120. The disposition of the electronic unit 130 may include aligning any portion of the electronic unit 130 with the alignment component 124. For example, in some embodiments, the alignment component 124 is used to align the electrical connection portion 132 of the electronic unit 130. Then, a heating step may be performed to bond the alignment component 124 and the electrical connection portion 132 through the bonding material 134. After the electronic unit 130 is disposed, a protective layer 140 surrounding the electronic unit 130 may be formed. The process for forming the protection layer 140 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable processes, or a combination thereof, but is not limited thereto.

In some embodiments, the control unit 110 is formed after the electronic unit 130 and the protective layer 140 are formed. More specifically, the protective layer 140 surrounding the electronic unit 130 can be formed in the electronic device where the control element 110 has not yet been formed, and then the entire electronic device is flipped over and the control element 110 is formed on the other side of the substrate structure 100. In this way, an electronic device 30 similar to that shown in FIG. 3 can be formed, wherein the substrate structure 100 is located between the electronic element 130 and the control unit 110. Through the above design, the control unit 110 can be prevented from interfering with the electronic unit 130 during operation, but the present invention is not limited thereto.

In some embodiments, before forming the control element 110, the first circuit structure 120, and the electronic unit 130, a conductive material 160 electrically connected to the conductive via pattern 101 is first formed on the substrate structure 100. In this case, a protective layer 140 surrounding the electronic unit 130 can be formed first, and then the first circuit structure 120 is bonded to the conductive via pattern 101 of the substrate structure 100 with the conductive material 160. In this way, an electronic device 40 including the conductive material 160 similar to that shown in FIG. 4 can be formed. Through the above design, the complexity of the process of forming the first circuit structure 120 and the second circuit structure 150 on the upper and lower sides of the substrate structure 100 can be reduced, but the present invention is not limited thereto.

Next, referring to FIG. 5E , the formation of the electronic device may further include forming a second circuit structure 150 on the substrate structure 100 opposite to the first circuit structure 120, and the dummy via pattern 102 is electrically insulated from the second circuit structure 150. Before, during, or after the formation of the second circuit structure 150, a dielectric material may be deposited to form a second dielectric layer 152 surrounding the second circuit structure 150. The process for depositing the second circuit structure 150 may be similar to that of the first circuit structure 120, and is not described separately for the sake of simplicity. The process for depositing the second dielectric layer 152 may be similar to that of the first dielectric layer 122, and is not described separately for the sake of simplicity.

As shown in FIG. 5E , an alignment feature 154 having a groove facing away from the second circuit structure 150 may be formed on the second circuit structure 150. The alignment feature 154 may be formed by forming an opening on the second dielectric layer 152 to expose the second circuit structure 150 and depositing a conductive material in the opening. The process for depositing the conductive material of the alignment feature 154 may be similar to that of the alignment feature 124 and is not further described herein for simplicity.

Next, referring to FIG. 5F , a bonding material 156 may be formed on the alignment member 154. By forming the bonding material 156, the formed electronic device may be bonded to an external circuit by heating. In some embodiments, after forming an electronic device array including a plurality of electronic units 130, the electronic device array is cut along a cutting line L, such as in FIG. 5F , to form a plurality of electronic devices. Depending on the design requirements of each electronic device after cutting, each electronic unit 130 may be the same, similar, or different types of components, which is not limited by the present disclosure.

It should be understood that the features of the various embodiments of the present disclosure may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

In summary, the present disclosure provides an electronic device and a method for forming the same. By forming a virtual through-hole pattern in a substrate structure, the substrate structure can be prevented from warping due to uneven stress. Compared with the packaging structure of the known electronic device, the electronic device of the present disclosure can maintain the stability of the substrate structure without affecting the electrical requirements. The packaging structure formed by such an electronic device can enhance the function of the electronic unit through the through-hole structure and the control unit. In addition, the formation of the virtual through-hole structure electrically insulated from the circuit structure can be integrated into the manufacturing process of the conductive through-hole pattern. Therefore, the formation method disclosed in the present invention can manufacture electronic devices with better electrical and structural performance, or does not require complicated manufacturing steps, thereby saving manufacturing costs.

The features of several embodiments are summarized above so that those with ordinary knowledge in the art to which the present invention belongs can more easily understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the art to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that such equivalent processes and structures do not violate the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

10,20,30,40: electronic device 20': electronic device array 100: substrate structure 100M: substrate material 101: conductive via pattern 101A: first conductive via 101B: second conductive via 102: virtual via pattern 104: buffer layer 105: stress adjustment layer 106: first insulating layer 108: second insulating layer 108TS: top surface 110: control element 112: semiconductor layer 114: gate 116: source/drain 120: first circuit structure 122: first dielectric layer 122SS: side surface 124,154: alignment component 130: electronic unit 132: electrical connection part 134,156: bonding material 136: diffusion area 140: protective layer 150: second circuit structure 152: second dielectric layer 160: conductive material L: cutting line

The following will be described in detail with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. FIG. 1 is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure. FIG. 2 is a cross-sectional view of an array of electronic devices according to some embodiments of the present disclosure. FIG. 3 is a cross-sectional view of an electronic device according to some other embodiments of the present disclosure. FIG. 4 is a cross-sectional view of an electronic device according to some other embodiments of the present disclosure. FIG. 5A to 5F are cross-sectional views of various stages in the manufacturing process of an electronic device according to some embodiments of the present disclosure.

10: Electronic devices

100: Substrate structure

100M: Substrate material

101: Conductive via pattern

101A: First conductive via

101B: Second conductive via

102: Virtual through hole pattern

104: Buffer layer

105: Stress adjustment layer

106: First insulation layer

108: Second insulation layer

108TS: Upper surface

110: Control element

112: Semiconductor layer

114: Gate

116: Source/Drain

120: First circuit structure

122: First dielectric layer

122SS: Side

124,154: Alignment components

130: Electronic unit

132: Electrical connection part

134,156:Jointing materials

136: Diffusion zone

140: Protective layer

150: Second circuit structure

152: Second dielectric layer

Claims (10)

An electronic device is characterized by comprising: a substrate structure having a conductive through-hole pattern and a virtual through-hole pattern; a control unit electrically connected to the conductive through-hole pattern; a first circuit structure electrically connected to the conductive through-hole pattern; and an electronic unit electrically connected to the control unit through the first circuit structure, wherein the virtual through-hole pattern is electrically insulated from the first circuit structure. The electronic device of claim 1 is characterized in that the conductive via pattern includes: a first conductive via electrically connected to the control unit through the first circuit structure; and a second conductive via electrically connected to the electronic unit through a portion of the first circuit structure separated from the control unit. The electronic device of claim 1 is characterized in that it further includes: A second circuit structure disposed on the substrate structure and opposite to the first circuit structure, wherein the virtual through-hole pattern is electrically insulated from the second circuit structure. The electronic device of claim 3 is characterized in that the first circuit structure and the second circuit structure are electrically connected through the conductive via pattern. The electronic device of claim 1 is characterized in that it further includes: A stress adjustment layer disposed on the substrate structure and located on a side of the substrate structure opposite to the control unit, wherein the stress adjustment layer covers a bottom surface of the virtual through-hole pattern. The electronic device of claim 1 is characterized in that the control unit is located above the substrate structure, and the control unit is located between the substrate structure and the first circuit structure. The electronic device of claim 1 is characterized in that the control unit is located below the substrate structure, and the substrate structure is located between the control unit and the first circuit structure. The electronic device of claim 1 is characterized in that it further includes a protective layer surrounding the electronic unit. The electronic device of claim 1 is characterized in that the substrate structure includes a transparent material. The electronic device of claim 1, wherein the conductive via pattern and the dummy via pattern comprise the same material.

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