TWI893801B - Display driver chip, display and information processing device - Google Patents

Abstract

The present invention primarily discloses a display driver chip characterized by including a display interface physical layer, a signal buffer circuit coupled to the display interface physical layer, and a source driver circuit coupled to the signal buffer circuit. The signal buffer circuit includes Y first buffer units for performing signal inversion and buffering processing on a clock signal, and Y second buffer units for performing signal inversion and buffering processing on display data. Furthermore, the source driver circuit includes alternating Y/2 first source driver modules and Y/2 second source driver modules. Each of the first source driver modules and each of the second source driver modules receives a clock signal through the first buffer unit and receives display data through the second buffer unit. This configuration effectively suppresses peak currents generated when each source driver module transmits and samples display data, while also effectively correcting the duty cycle of clock signals transmitted over long distances.

Description

Display driver chip, display and information processing device

This invention relates to the field of flat-panel displays, and more particularly to a display driver chip capable of reducing (or eliminating) peak current in signal transmission. At least one such display driver chip can be combined with a display panel to form a flat-panel display.

Figure 1 is a block diagram of a conventional flat panel display. As shown in Figure 1, the conventional flat panel display 1c primarily comprises a display panel 10c, at least one display driver chip 11c, and a timing controller (Tcon) 12c. The display panel 10c includes X x Y sub-pixels, and the display driver chip 11c includes a data receiving module 111c, a display interface physical layer (DPHY) 112c, and Y source driver modules 113c. X and Y are positive integers. Furthermore, Figure 2 is a block diagram of the Y source driver modules 111c shown in Figure 1. As shown in Figure 2, the display interface physical layer 112c receives display data (RGB DATA), clock signals (CLK), and other signals transmitted by the timing controller 12c via the data receiving module 111c. It then transmits the display data and clock signals to the Y/2 source driver modules 113c on the left and the Y/2 source driver modules 113c on the right. Ultimately, the Y source driver modules 113c generate Y data (voltage data or current data), which are driven to the Y source lines of the display panel 10c via the Y channels of the display driver chip 11c.

Furthermore, Figure 3 is a first block diagram of a source driver module 113c. As shown in Figure 3, each source driver module 113c primarily comprises a shift register 1131c, a data latch (sampling latch) 1132c, a hold latch 1133c, a level shifter 1134c, a digital-to-analog converter 1135c, and a buffer 1136c. To further illustrate, as shown in Figures 2 and 3, to meet the requirements of high-resolution and high-frame-rate displays, the number of source driver modules 111c integrated into the display driver chip 11c has increased accordingly. Furthermore, in the display driver chip 11c, the display interface physical layer 112c transmits display data (RGB DATA) to each source driver module 113c via a data signal transmission bus (DATA BUS) 114c, and transmits a clock signal (CLK) to each shift register 1131c via a clock signal transmission bus (CLK BUS) 115c.

Practical experience has shown that due to the large number of Y source driver modules 113c and their high clock frequency, the process of transmitting (i.e., writing) data to the data latch (Latch 1) 1132c easily generates large peak currents at low voltage levels. Furthermore, relevant measurement data shows that this peak current not only increases the overall power consumption of the display driver chip 11c but also reduces the power supply voltage (VDD), thereby negatively impacting the normal operation of the display driver chip 12c circuitry.

Figure 4 is a second block diagram of a source driver module 113c. As shown in Figure 4, to reduce peak currents caused by variations in the transmitted signal, conventional technology configures the display interface physical layer 112c and the digital-to-analog converter 1135c with code mapping capabilities. Furthermore, conventional technology also configures the shift register 1131c to perform odd-even phase sampling and latching of the display data (RGB DATA) based on a first clock signal (CLK_EVEN) and a second clock signal (CLK_ODD).

The above methods can all reduce the peak current generated by transmission signal fluctuations to a certain extent. However, when RGB DATA is used to display an image with a specific pattern, peak current will still be generated when transmitting (writing) data to the data latch 1132c. Furthermore, as the number of Y source driver modules 113c increases, as shown in Figure 2, the transmission distance between the data signal transmission bus 114c and the clock signal transmission bus 115c also increases accordingly. This will cause the clock signal duty cycle to gradually deviate, up to 50%. This will have a certain degree of negative impact on the data sampling of the shift register 1131c.

In summary, consideration should be given to redesigning or improving the circuit architecture of existing display driver chips to reduce (or eliminate) the peak current generated during internal data transmission and prevent duty cycle deviation of the clock signal due to increased transmission distance.

From the above description, it can be seen that a new type of display driver chip is urgently needed in this field.

The primary objective of this invention is to provide a display driver chip. Specifically, the present invention adds Y first buffer units to the display driver chip for signal inversion and buffering of clock signals, and Y second buffer units for signal inversion and buffering of display data. Furthermore, at least one inverter is added to each of Y/2 source driver modules, and at least one buffer is added to each of another Y/2 source driver modules. This arrangement effectively suppresses the peak current generated by each source driver module when transmitting and sampling display data, while also effectively correcting the duty cycle of clock signals transmitted over long distances.

Compared to existing code mapping methods and/or odd-even phase sampling latching methods, the present invention's technical solution effectively reduces the peak current generated during the data signal transmission process from the data bus (DATA BUS) to the first latch (Latch 1) and from the first latch to the second latch (Latch 2), even when the display data (RGB DATA) is used to display images with specific patterns. More importantly, the display driver chip of the present invention does not require a specific timing controller (TCON), thus offering greater compatibility and flexibility in display system applications.

In order to achieve the above-mentioned object, the present invention proposes an embodiment of the display driver chip, which is characterized in that it includes a display interface physical layer, a signal buffer circuit coupled to the display interface physical layer, and a source drive circuit coupled to the signal buffer circuit, wherein: the signal buffer circuit includes Y first buffer units and Y second buffer units, the first of the first buffer units The first buffer unit receives a clock signal from the display interface physical layer, the i+1th first buffer unit receives the clock signal from the i-th first buffer unit coupled thereto, the first second buffer unit receives a display data from the display interface physical layer, and the i+1th second buffer unit receives the display data from the i-th second buffer unit coupled thereto. , Y is a positive integer, and i is an integer between 1 and Y; the first buffer unit is configured to perform a clock signal inversion process and a clock signal buffering process on the clock signal, and the second buffer unit is configured to perform a display data inversion process and a display data buffering process on the display data; and the source drive circuit includes P first source The driver module and P second source driver modules are coupled. The jth first source driver module is coupled to the ith first buffer unit and the ith second buffer unit, and the jth second source driver module is coupled to the i+1th first buffer unit and the i+1th second buffer unit. P is a positive integer equal to Y/2, and j is an integer between 1 and P.

In one embodiment, the first buffer unit includes: a first inverter having an input and an output, wherein the input is coupled to the clock signal, the first inverter is configured to perform the clock signal inversion processing on the clock signal, and output the clock signal through the output; and a first buffer having an input and an output, wherein the input is coupled to the output of the first inverter, the first buffer is configured to perform the clock signal buffering processing on the clock signal, and output the clock signal through the output.

In one embodiment, the second buffer unit includes: a second inverter having an input and an output, wherein the input is coupled to the display data, the second inverter is configured to perform the display data inversion processing on the display data, and output the display data through the output; and a second buffer having an input and an output, wherein the input is coupled to the second inverter, the second buffer is configured to perform the display data buffering processing on the display data, and output the display data through the output.

In one possible embodiment, the first source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter. The shift register receives the clock signal from the first buffer via a third inverter; the first latch receives the display data via the second buffer; a first input of the level shifter is coupled to the second latch via a fourth inverter; and a second input of the level shifter is directly coupled to the second latch.

In another possible embodiment, the first source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; wherein the shift register receives the first latch from the first buffer. A clock signal is provided; the shift register further outputs the clock signal through a third inverter; the first latch receives the display data through the second buffer; a first input terminal of the level shifter is directly coupled to the second latch; a second input terminal of the level shifter is coupled to the second latch through a fourth inverter; and the first latch transmits the display data to the second latch through a fifth inverter.

In one possible embodiment, the second source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter. The second source driver module is characterized in that: the shift register receives the clock signal from the first buffer via a third buffer; the first latch receives the display data from the second buffer via a fourth buffer; a first input terminal of the level shifter is directly coupled to the second latch; and a second input terminal of the level shifter is coupled to the second latch via an inverter.

Furthermore, the present invention also provides an embodiment of a display device, comprising a display panel and at least one display driver chip for driving the display panel. The display driver chip includes a display interface physical layer, a signal buffer circuit coupled to the display interface physical layer, and a source driver circuit coupled to the signal buffer circuit, wherein: The first buffer unit and Y second buffer units, the first first buffer unit receives a clock signal from the display interface physical layer, the i+1th first buffer unit receives the clock signal from the i-th first buffer unit coupled thereto, the first second buffer unit receives a display data from the display interface physical layer, the i+1th second buffer unit receives a display data from the i-th first buffer unit coupled thereto The i-th second buffer unit receives the display data, Y is a positive integer, and i is an integer between 1 and Y; the first buffer unit is configured to perform a clock signal inversion process and a clock signal buffering process on the clock signal, and the second buffer unit is configured to perform a display data inversion process and a display data buffering process on the display data; and the source driver The circuit includes P first source driver modules and P second source driver modules. The jth first source driver module is coupled to the ith first buffer unit and the ith second buffer unit, and the jth second source driver module is coupled to the i+1th first buffer unit and the i+1th second buffer unit. P is a positive integer equal to Y/2, and j is an integer between 1 and P.

In one embodiment, the first buffer unit includes: a first inverter having an input and an output, wherein the input is coupled to the clock signal, the first inverter is configured to perform the clock signal inversion processing on the clock signal, and output the clock signal through the output; and a first buffer having an input and an output, wherein the input is coupled to the output of the first inverter, the first buffer is configured to perform the clock signal buffering processing on the clock signal, and output the clock signal through the output.

In one embodiment, the second buffer unit includes: a second inverter having an input and an output, wherein the input is coupled to the display data, the second inverter is configured to perform display data inversion processing on the display data, and output the display data through the output; and a second buffer having an input and an output, wherein the input is coupled to the second inverter, the second buffer is configured to perform display data buffering processing on the display data, and output the display data through the output.

In one possible embodiment, the first source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter. The shift register receives the clock signal from the first buffer via a third inverter; the first latch receives the display data via the second buffer; a first input of the level shifter is coupled to the second latch via a fourth inverter; and a second input of the level shifter is directly coupled to the second latch.

In another possible embodiment, the first source drive module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; wherein the shift register receives the clock from the first buffer. clock signal; the shift register further outputs the clock signal via a third inverter; the first latch receives the display data via the second buffer; a first input terminal of the level shifter is directly coupled to the second latch; a second input terminal of the level shifter is coupled to the second latch via a fourth inverter; and the first latch transmits the display data to the second latch via a fifth inverter.

In one embodiment, the second source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter. The module is characterized in that: the shift register receives the clock signal from the first buffer via a third buffer; the first latch receives the display data from the second buffer via a fourth buffer; a first input terminal of the level shifter is directly coupled to the second latch; and a second input terminal of the level shifter is coupled to the second latch via an inverter.

Furthermore, the present invention also provides an embodiment of an information processing device, characterized in that it has at least one display according to the present invention as described above.

In one embodiment, the information processing device is an electronic device selected from the group consisting of an advertising display device, a multimedia information display device (kiosk), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a laptop computer, an in-car entertainment device, a digital camera, and a video door station.

1c: Flat panel display

10c: Display Panel

11c: Display driver chip

11c: Data receiving module

112c: Display interface entity layer

113c: Source driver module

1131c: Shift register

1132c: Data lock register

1133c: Keep lock register

1134c: Level Shifter

1135c: Digital-to-Analog Converter

1136c: Buffer

114c: First transmission channel

115c: Second transmission channel

12c: Timing Controller

1: Display

10: Display Panel

11: Display driver chip

111: Data receiving module

112: Display interface entity layer

114: Data signal transmission bus

115: Clock signal transmission bus

12: Timing controller

2: Signal buffer circuit

21: First buffer unit

211: First Inverter

212: First buffer

22: Second buffer unit

221: Second Inverter

222: Second buffer

3: Source drive circuit

31: First source driver module

311: Shift Register

312: First lock

313: Second lock

314: Level Shifter

315: Digital-to-Analog Converter

316: Output buffer

310: Third inverter

31A: Fourth inverter

31B: Fifth Inverter

32: Second source driver module

321: Third Buffer

322: Fourth buffer

Figure 1 is a block diagram of a conventional flat panel display; Figure 2 is a block diagram of the Y source driver modules shown in Figure 1; Figure 3 is a first block diagram of a source driver module; Figure 4 is a second block diagram of a source driver module; Figure 5 is a block diagram of a display including a display driver chip of the present invention; Figure 6 is a diagram of the signal buffer circuit and source shown in Figure 5. Figure 7 is a circuit diagram of the first buffer shown in Figure 6; Figure 8 is a circuit diagram of the second buffer shown in Figure 6; Figure 9 is a first circuit block diagram of the first source driver module shown in Figure 6; Figure 10 is a circuit block diagram of the second source driver module shown in Figure 6; and Figure 11 is a second circuit block diagram of the first source driver module shown in Figure 6.

To help you better understand the structure, features, objectives, and advantages of this invention, we have attached drawings and detailed descriptions of preferred embodiments.

Figure 5 is a block diagram of a display including a display driver chip according to the present invention. As shown in Figure 5 , the basic architecture of the display 1 includes a display panel 10, at least one display driver chip 11 according to the present invention, and a timing controller (Tcon) 12. The display panel 10 includes a plurality of sub-pixels (e.g., OLED elements), and the display driver chip 11 includes a data receiver (RX) module 111, a display interface physical layer (DPHY) 112 coupled to the data receiver module 111, a signal buffer circuit 2 coupled to the display interface physical layer 112, and a source driver circuit 3 coupled to the signal buffer circuit 2. When the present invention is actually applied, the display panel 10 may be, but is not limited to, a liquid crystal display panel, an OLED display panel, an LED display panel, or a Micro-LED display panel.

FIG6 is a block diagram of the signal buffer circuit 2 and source drive circuit 3 shown in FIG5 . As shown in FIG6 , the signal buffer circuit 2 includes Y first buffer units 21 and Y second buffer units 22, where Y is a positive integer. According to the design of the present invention, among the Y first buffer units 21, the first first buffer unit 21 is coupled to the display interface physical layer 112, and the output of the i-th first buffer unit 21 is coupled to the input of the i+1-th first buffer unit 21, where i is an integer between 1 and Y. Specifically, the present invention configures the first buffer unit 21 to perform a clock signal inversion process and a clock signal buffering process on a clock signal. In this design, the first first buffer unit 21 receives the clock signal from the display interface physical layer 112 and then performs a clock signal inversion process and a clock signal buffering process on the clock signal. Subsequently, the (i+1)th first buffer unit 21 receives the clock signal from the (i)th first buffer unit 21 coupled thereto and then performs a clock signal inversion process and a clock signal buffering process on the clock signal.

Similarly, among the Y second buffer units 22, the first second buffer unit 22 is coupled to the display interface physical layer 112, and the i-th second buffer unit 22 has its output coupled to the input of the (i+1)-th second buffer unit 22. Specifically, the present invention configures the second buffer unit 22 to perform a display data flipping process and a display data buffering process on display data. With this design, the first second buffer unit 22 receives the display data from the display interface physical layer 112 and then performs a display data flipping process and a display data buffering process on the display data. Subsequently, the (i+1)th second buffer unit 22 receives the display data from the (i)th second buffer unit 22 coupled thereto, and then performs display data flipping processing and display data buffering processing on the display data.

Figure 7 is a circuit diagram of the first buffer unit 21 shown in Figure 6. As shown in Figure 7, the first buffer unit 21 includes a first inverter 211 and a first buffer 212. The first inverter 211 has an input and an output, with the input coupled to the clock signal. Furthermore, the first inverter 211 is configured to perform a clock signal inversion process on the clock signal and output the clock signal through the output. The first buffer 212 has an input and an output, with the input coupled to the output of the first inverter 211. Furthermore, the first buffer 212 is configured to perform a clock signal buffering process on the clock signal transmitted by the first inverter 211 and output the clock signal through the output terminal.

Furthermore, FIG8 is a circuit diagram of the second buffer unit 22 shown in FIG6 . As shown in FIG8 , the second buffer unit 22 includes a second inverter 221 and a second buffer 222. The second inverter 221 has an input and an output, and the input is coupled to the display data. Furthermore, the second inverter 221 is configured to perform a display data inversion process on the display data and output the display data through the output. On the other hand, the second buffer 222 has an input and an output, and the input is coupled to the output of the second inverter 221. Furthermore, the second buffer 222 is configured to perform a display data buffering process on the display data transmitted by the second inverter 221 and output the display data through the output terminal.

Electronic engineers familiar with display driver chips (i.e., DDIC) and/or touch and display driver chips (i.e., TDDI) will undoubtedly know that existing display driver chips contain multiple source driver modules 113c (as shown in Figure 1). Furthermore, as shown in Figure 4, each source driver module 113c basically comprises a shift register 1131c, a data latch (sampling latch, Latch1) 1132c, a holding latch (hold latch, Latch2) 1133c, a level shifter 1134c, a digital-to-analog converter 1135c, and a buffer 1136c.

It should be noted that, taking a D-type flip-flop as a 1-bit shift register 1131c as an example, Y source driver modules 113c comprise a total of Y shift registers 1131c, and these Y shift registers 1131c form a shift register circuit for performing shift register processing on Y bits of display data (RGB data).

Specifically, the present invention adds Y first buffer units 21 for inverting and buffering clock signals, and Y second buffer units 22 for inverting and buffering display data, to the display driver chip 11 shown in FIG5 . Furthermore, as shown in FIG6 , the present invention also adds at least one inverter to each of the Y/2 first source driver modules 31 and at least one buffer to each of the other Y/2 second source driver modules 32. According to this setting, the peak current generated by each source drive module (31, 32) when transmitting and sampling display data is effectively suppressed, and at the same time, it also has a good correction effect on the duty cycle of the clock signal transmitted over long distances.

To explain in more detail, in the display driver chip 11 of the present invention, as shown in FIG6 , the source driver circuit 3 includes P first source driver modules 31 and P second source driver modules 32 , wherein the jth first source driver module 31 is coupled to the ith first buffer unit 21 and the ith second buffer unit 22 , and the jth second source driver module 32 is coupled to the i+1th first buffer unit 21 and the i+1th second buffer unit 22 . Furthermore, P is a positive integer equal to Y/2, and j is an integer between 1 and P.

Figure 9 is a first circuit block diagram of the first source driver module 31 shown in Figure 6 . As shown in Figure 9 , in one embodiment, the basic components of the first source driver module 31 also include: a shift register 311, a first latch (sampling latch, Latch1) 312 coupled to the shift register 311, a second latch (hold latch, Latch2) 313 coupled to the first latch 312, a level shifter 314 coupled to the second latch 313, a digital-to-analog converter 315 coupled to the level shifter 314, and an output buffer 316 coupled to the digital-to-analog converter 315.

As shown in Figure 9, the first source driver module 31 further includes a third inverter 310 and a fourth inverter 31A. This allows the shift register 311 to receive the clock signal from the first buffer 212 via the third inverter 310, and a first input terminal (i.e., the positive terminal) of the level shifter 314 is coupled to the second latch 313 via the fourth inverter 31A. Furthermore, within the first source driver module 31, the first latch 312 receives the display data via the second buffer 222, and a second input terminal (i.e., the negative terminal) of the level shifter 314 is directly coupled to the second latch 313.

As shown in Figures 6 and 9, when the display interface physical layer (DPHY) 112 transmits display data (RGB DATA) to the Y/2 first source driver modules 31 via a data signal transmission bus (DATA BUS) 114, the display data is signal-inverted and buffered by the second buffer unit 22 before being transmitted to the first latch (sampling latch, Latch1) 312 of the first source driver module 31. Furthermore, when the second latch (hold latch, Latch2) 313 loads display data into the level shifter 314 in response to a data load signal (i.e., LD), the fourth inverter 31A inverts the display data and transmits it to the first input terminal (i.e., the + terminal) of the level shifter 314. Simultaneously, the second input terminal (i.e., the - terminal) of the level shifter 314 receives the display data from the second latch (Latch2) 313, before the fourth inverter 31A performs the signal inversion processing.

Furthermore, as shown in Figures 6 and 9, when the display interface physical layer 112 transmits a clock signal (CLK) to the Y/2 first source driver modules 31 via a clock signal transmission bus (CLK BUS) 115, the second buffer unit 22 performs signal inversion and buffering on the clock signal before transmitting the clock signal to the CLK terminal of the shift register 311 of the first source driver module 31 via the third inverter 310. It should be understood that the third inverter 310 performs signal inversion on the clock signal before transmitting it to the CLK terminal of the shift register 311.

Furthermore, Figure 10 is a circuit block diagram of the second source driver module 32 shown in Figure 6. As shown in Figures 9 and 10, the basic components of the second source driver module 32 also include: a shift register 311, a first latch (sampling latch, Latch1) 312 coupled to the shift register 311, a second latch (hold latch, Latch2) 313 coupled to the first latch 312, a level shifter 314 coupled to the second latch 313, a digital-to-analog converter 315 coupled to the level shifter 314, and an output buffer 316 coupled to the digital-to-analog converter 315.

As shown in Figure 10, the second source driver module 32 further includes a third buffer 321, a fourth buffer 322, and the fourth inverter 31A. This allows the shift register 311 to receive the clock signal from the first buffer 212 via the third buffer 321, and the first latch 312 to receive the display data from the second buffer 222 via the fourth buffer 322. Furthermore, a first input terminal (i.e., the positive terminal) of the level shifter 314 is directly coupled to the second latch 313, and a second input terminal (i.e., the negative terminal) of the level shifter 314 is coupled to the second latch 313 via the fourth inverter 31A.

Furthermore, Figure 11 is a second circuit block diagram of the first source driver module 31 shown in Figure 6 . As shown in Figure 11 , in another possible embodiment, the basic components of the first source driver module 31 also include: a shift register 311, a first latch (sampling latch, Latch1) 312 coupled to the shift register 311, a second latch (hold latch, Latch2) 313 coupled to the first latch 312, a level shifter 314 coupled to the second latch 313, a digital-to-analog converter 315 coupled to the level shifter 314, and an output buffer 316 coupled to the digital-to-analog converter 315. Its characteristic is that the first source driver module 31 further includes the fourth inverter 31A and a fifth inverter 31B, allowing the first latch 312 to transmit the display data to the second latch 313 via the fifth inverter 31B. Furthermore, the second input of the level shifter 314 is coupled to the second latch 313 via the fourth inverter 31A, and the first input is directly coupled to the second latch 313. Meanwhile, the first latch 31 receives the display data via the second buffer 222. It is worth noting that in Figure 11, the shift register 311 receives the clock signal from the first buffer 212 and further outputs the clock signal via a third inverter 310.

Thus, the above description has fully and clearly explained the display driver chip of the present invention; and, from the above description, it can be seen that the present invention has the following advantages:

(1) The present invention provides a display driver chip having the function of reducing (eliminating) the peak current of signal transmission. In particular, the present invention adds Y first buffer units for performing signal inversion and buffering processing on clock signals and Y second buffer units for performing signal inversion and buffering processing on display data to the display driver chip, and adds at least one inverter to each of Y/2 source driver modules and at least one buffer to each of another Y/2 source driver modules. With this setup, the peak current generated by each source driver module when transmitting and sampling display data is effectively suppressed, while also effectively correcting the duty cycle of the clock signal transmitted over long distances.

(2) Compared with the prior art code mapping method and/or odd-even phase sampling latch method, even if the display data (RGB DATA) is used to display an image with a specific pattern, the technical solution of the present invention can still effectively reduce the peak current generated during the transmission process from the data signal transmission bus (DATA BUS) to the first latch (Latch1) and from the first latch to the second latch (Latch2).

(3) More importantly, the display driver chip of the present invention does not need to be paired with a specific timing controller (TCON), so it has better compatibility and higher application flexibility in display systems.

(4) Furthermore, the present invention also provides an information processing device having at least one display, characterized in that the display includes a display panel and at least one display driver chip of the present invention as described above. In one embodiment, the information processing device is an electronic device selected from the group consisting of an advertising display device, a multimedia information display device (KIOSK), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a notebook computer, an in-car entertainment device, a digital camera, and a video door machine.

It must be emphasized that the aforementioned disclosure of this case is a preferred embodiment. Any partial changes or modifications that are derived from the technical concept of this case and are easily inferred by those skilled in the art do not deviate from the scope of the patent rights of this case.

In summary, this case demonstrates significant differences from known technologies in terms of purpose, means, and effects. Furthermore, its first invention is practical and truly meets the patent requirements for invention. We sincerely request the Review Commission to carefully examine this matter and grant a patent to this invention as soon as possible to benefit society. This is our utmost prayer.

112: Display interface entity layer

2: Signal buffer circuit

21: First buffer unit

22: Second buffer unit

3: Source drive circuit

31: First source driver module

32: Second source driver module

114: Data signal transmission bus

115: Clock signal transmission bus

Claims (15)

A display driver chip is characterized in that it includes a display interface physical layer, a signal buffer circuit coupled to the display interface physical layer, and a source driver circuit coupled to the signal buffer circuit, wherein: The signal buffer circuit includes Y first buffer units and Y second buffer units, the first first buffer unit receives a clock signal from the display interface physical layer, the (i+1)th first buffer unit receives the clock signal from the (i)th first buffer unit coupled thereto, the first second buffer unit receives display data from the display interface physical layer, the (i+1)th second buffer unit receives the display data from the (i)th second buffer unit coupled thereto, Y is a positive integer, and i is an integer between 1 and Y; The first buffer unit is configured to perform a clock signal flipping process and a clock signal buffering process on the clock signal, and the second buffer unit is configured to perform a display data flipping process and a display data buffering process on the display data. A display driver chip as described in claim 1, wherein the source driver circuit includes P first source driver modules and P second source driver modules, the jth first source driver module is coupled to the ith first buffer unit and the ith second buffer unit, and the jth second source driver module is coupled to the i+1th first buffer unit and the i+1th second buffer unit; P is a positive integer equal to Y/2, and j is an integer between 1 and P. A display driver chip as described in claim 1, wherein the first buffer unit includes: a first inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the clock signal, and the first inverter is configured to perform the clock signal inversion processing on the clock signal and output the clock signal through the output terminal; and a first buffer having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first inverter, and the first buffer is configured to perform the clock signal buffering processing on the clock signal and output the clock signal through the output terminal. A display driver chip as described in claim 1, wherein the second buffer unit includes: a second inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the display data, and the second inverter is configured to perform the display data inversion processing on the display data and output the display data through the output terminal; and a second buffer having an input terminal and an output terminal, wherein the input terminal is coupled to the second inverter, and the second buffer is configured to perform the display data buffering processing on the display data and output the display data through the output terminal. A display driver chip as described in claim 2, wherein the first source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; which is characterized in that: the shift register receives the clock signal from the first buffer unit through a third inverter; the first latch receives the display data through the second buffer unit; a first input terminal of the level shifter is coupled to the second latch through a fourth inverter; and A second input terminal of the level shifter is directly coupled to the second latch. A display driver chip as described in claim 2, wherein the first source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; its characteristics are: the shift register receives the clock signal from the first buffer unit; the shift register further outputs the clock signal through a third inverter; the first latch receives the display data through the second buffer unit; a first input terminal of the level shifter is directly coupled to the second latch; A second input terminal of the level shifter is coupled to the second latch through a fourth inverter; and the first latch transmits the display data to the second latch through a fifth inverter. The display driver chip as described in claim 2, wherein the second source driver module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; which is characterized in that: the shift register receives the clock signal from the first buffer unit through a third buffer; the first latch receives the display data from the second buffer unit through a fourth buffer; a first input terminal of the level shifter is directly coupled to the second latch; and A second input terminal of the level shifter is coupled to the second latch through an inverter. A display comprises a display panel and at least one display driver chip for driving the display panel. The display driver chip comprises a display interface physical layer, a signal buffer circuit coupled to the display interface physical layer, and a source driver circuit coupled to the signal buffer circuit, wherein: The signal buffer circuit includes Y first buffer units and Y second buffer units, the first first buffer unit receives a clock signal from the display interface physical layer, the (i+1)th first buffer unit receives the clock signal from the i-th first buffer unit coupled thereto, the first second buffer unit receives a display data from the display interface physical layer, the (i+1)th second buffer unit receives the display data from the i-th second buffer unit coupled thereto, Y is a positive integer, and i is an integer between 1 and Y; The first buffer unit is configured to perform a clock signal inversion process and a clock signal buffering process on the clock signal, and the second buffer unit is configured to perform a display data inversion process and a display data buffering process on the display data. A display as described in claim 8, wherein the source driver circuit includes P first source driver modules and P second source driver modules, the jth first source driver module is coupled to the ith first buffer unit and the ith second buffer unit, and the jth second source driver module is coupled to the i+1th first buffer unit and the i+1th second buffer unit; P is a positive integer equal to Y/2, and j is an integer between 1 and P. A display as described in claim 8, wherein the first buffer unit includes: a first inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the clock signal, and the first inverter is configured to perform the clock signal inversion processing on the clock signal and output the clock signal through the output terminal; and a first buffer having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first inverter, and the first buffer is configured to perform the clock signal buffering processing on the clock signal and output the clock signal through the output terminal. A display as described in claim 8, wherein the second buffer unit includes: a second inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the display data, and the second inverter is configured to perform the display data inversion processing on the display data and output the display data through the output terminal; and a second buffer having an input terminal and an output terminal, wherein the input terminal is coupled to the second inverter, and the second buffer is configured to perform the display data buffering processing on the display data and output the display data through the output terminal. The display as described in claim 9, wherein the first source drive module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; which is characterized in that: the shift register receives the clock signal from the first buffer unit through a third inverter; the first latch receives the display data through the second buffer unit; a first input terminal of the level shifter is coupled to the second latch through a fourth inverter; and A second input terminal of the level shifter is directly coupled to the second latch. The display as described in claim 9, wherein the first source drive module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; which is characterized in that: the shift register receives the clock signal from the first buffer unit; the shift register further outputs the clock signal through a third inverter; the first latch receives the display data through the second buffer unit; a first input terminal of the level shifter is directly coupled to the second latch; A second input terminal of the level shifter is coupled to the second latch through a fourth inverter; and the first latch transmits the display data to the second latch through a fifth inverter. The display as described in claim 9, wherein the second source drive module includes a shift register, a first latch coupled to the shift register, a second latch coupled to the first latch, a level shifter coupled to the second latch, a digital-to-analog converter coupled to the level shifter, and an output buffer coupled to the digital-to-analog converter; which is characterized in that: the shift register receives the clock signal from the first buffer unit through a third buffer; the first latch receives the display data from the second buffer unit through a fourth buffer; a first input terminal of the level shifter is directly coupled to the second latch; and A second input terminal of the level shifter is coupled to the second latch through an inverter. An information processing device is characterized by having at least one display as described in any one of claim 8 to claim 14.