TWI840040B - Pixel data copying method, display device and information processing device - Google Patents

Abstract

The present invention mainly discloses a pixel data copying method, which is applied to a display device including a display panel and at least one display driver chip, so that the display driver chip executes the pixel data copying method of the present invention when the resolution of the display device is reduced, thereby realizing pixel data copying while reducing data transmission power consumption and time.

Description

Pixel data copying method, display device and information processing device

The present invention relates to the technical field of display devices, and in particular to a pixel data copying method that can realize pixel data copying while reducing data transmission power consumption and time.

It is known that flat panel displays include non-self-luminous flat panel displays and self-luminous flat panel displays, wherein liquid crystal displays are a type of non-self-luminous flat panel displays that have been used for a long time, while organic light-emitting diode (OLED) displays and light-emitting diode (LED) displays are self-luminous flat panel displays with mainstream applications. FIG1 is a block diagram of a known liquid crystal display device. As shown in FIG1, the known liquid crystal display device 1a mainly includes: a liquid crystal panel 11a and at least one display driver chip 12a, wherein the display driver chip 12a includes: a timing controller 121a, a source driver unit 122a and a gate driver unit 120a.

FIG2 is a block diagram of the internal structure of a source drive circuit. As shown in FIG1 and FIG2, the source drive unit 122a includes a source drive circuit 123a with N drive channels (CH1~CHn), and N is a positive integer. In more detail, the source drive circuit 123a mainly includes: a shift register 1231a, a sampling latch 1232a, a holding latch 1233a, a level shifter 1234a, a digital-to-analog converter (DAC) 1235a, N drivers 1236a, and a gamma voltage generating unit 1237a.

FIG3 is a timing diagram of the first display data, bus transmission data and clock signal. As shown in FIG2 and FIG3, the prior art utilizes the following method steps to complete data locking of a first display data received from a data transmission interface: the shift register 1231a generates N/m enable signals according to a clock signal; wherein each of the enable signals includes a pulse width, each of the pulse widths is (m/3)*T, and N and m are both positive integers; the first display data is received through the data transmission interface; wherein the first display data includes N/3 sets of RGB pixel data, the time taken by the data transmission interface to receive the first display data is (N/3)*T, and the data transmission interface receives a set of RGB pixel data; GB pixel data takes T time; the first display data is arranged into a second display data; wherein the first display data is a serial data, and the second display data is a parallel data; and the second display data is transmitted to a sampling latch 1232a included in the source drive circuit by using a data transmission bus (i.e., bus), so that the sampling latch 1232a performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch 1232a after N/m times of the data latch operation.

It should be understood that a pixel includes an R sub-pixel, a G sub-pixel, and a B sub-pixel. Therefore, using the m sub-pixel data, the source driver circuit 123a can light up m/3 pixels of the liquid crystal display panel 11a. Further, FIG. 4 and FIG. 5 are first and second block diagrams of a set of source driver circuits. As shown in FIG. 2 and FIG. 4, during normal operation, the data voltage (or data current) output by each of the three driver channels corresponds to a set of RGB data (such as: R1/G1/B1). According to the prior art, when the resolution of the liquid crystal display device 1a is reduced, as shown in FIG. 5, each of the source driver circuits 123a will perform a pixel data copy function so that two adjacent pixels correspond to the same set of RGB data. However, practical experience shows that when the pixel data copy function is executed, the input amount of display data of each source drive circuit 123a does not change and remains the same, so the time and power consumption of receiving input display data will not be reduced.

From the above description, it can be seen that a pixel data replication method is urgently needed in this field.

The main purpose of the present invention is to provide a pixel data copying method, which is applied to a display device including a display panel and at least one display driver chip, so that the display driver chip executes the pixel data copying method of the present invention when the resolution of the display device is reduced, thereby realizing pixel data copying while reducing data transmission power consumption and time.

To achieve the above object, the present invention proposes a first embodiment of the pixel data copying method, which is executed by a display driver chip, wherein the display driver chip includes a source driver circuit with N driving channels, and the pixel data copying method includes: multiplying a first clock signal into a second clock signal, so that a shift register included in the source driver circuit generates N/m enable signals according to the second clock signal; wherein each of the enable signals has a pulse width, and N and m are both positive integers; arranging a first display data received through a data transmission interface into a second display data; wherein the first display data and the second display data each include N/6 sets of RG B Pixel data, each two groups of RGB pixel data in the second display data contain the same content, the time taken by the data transmission interface to receive the first display data is (N/6)*T, the time taken by the data transmission interface to receive a group of RGB pixel data is T, and the width of each pulse is (m/6)*T; and the second display data is transmitted to a sampling latch included in the source drive circuit by using a data transmission bus, so that the sampling latch performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch after N/m times of the data latch operation.

To achieve the above object, the present invention also proposes a second embodiment of the pixel data copying method, which is executed by a display driver chip, wherein the display driver chip includes a source driver circuit with N driving channels, and the pixel data copying method includes: allowing a shift register included in the source driver circuit to generate N/2m first enable signals and N/2m second enable signals according to a clock signal. enable signal; wherein each of the first enable signals has a first pulse width, each of the second enable signals has a second pulse width, and N and m are both positive integers; receiving a first display data through a data transmission interface; wherein the first display data includes N/6 sets of RGB pixel data, and the time taken for the data transmission interface to receive the first display data is (N/6)*T, and the data transmission interface The time taken to receive a set of RGB pixel data on the surface is T, the width of each first pulse is (m/3)*T, and the width of each second pulse is (m/3)*T; the first display data is arranged into a second display data; and the second display data is transmitted to a sampling latch included in the source drive circuit by using a data transmission bus, so that the sampling latch is based on the first use A first data latching operation is performed on the m sub-pixel data of the second display data according to a first enable signal, and a second data latching operation is performed on the m sub-pixel data of the second display data according to a second enable signal. Finally, the second display data is completely latched in the sampling latch after N/2m times of the first data latching operation and N/2m times of the second data latching operation.

In a first feasible embodiment, the source drive circuit includes: the shift register, the sampling latch coupled to the shift register, a holding latch coupled to the sampling latch, a level shifter coupled to the holding latch, a digital-to-analog converter coupled to the level shifter, and N drivers coupled to the digital-to-analog converter, and the source drive circuit further includes: a multiplexer coupled between the sampling latch and the data transmission bus; wherein the multiplexer The multiplexer transmits the jth group of data including m sub-pixel data to the sampling latch within an enable time period of the first enable signal, so that the sampling latch performs the first data latch operation on the m sub-pixel data, and j is a positive integer; wherein the multiplexer transmits the j+1th group of data including m sub-pixel data to the sampling latch within an enable time period of the second enable signal, so that the sampling latch performs the second data latch operation on the m sub-pixel data.

In a second feasible embodiment, the source drive circuit includes: the shift register, the sampling latch coupled to the shift register, a holding latch coupled to the sampling latch, a level shifter coupled to the holding latch, a digital-to-analog converter coupled to the level shifter, and N drivers coupled to the digital-to-analog converter, and the source drive circuit further includes: a multiplexer coupled between the holding latch and the sampling latch; wherein the sampling latch is connected to the first drive The jth group of data is locked in the sampling latch during the enabling time period of the second enabling signal, and the multiplexer further transmits the jth group of data locked in the sampling latch to the holding latch, the jth group of data includes m sub-pixel data, and j is a positive integer; wherein, the sampling latch locks the j+1th group of data in the enabling time period of the second enabling signal, and the multiplexer further transmits the j+1th group of data locked in the sampling latch to the holding latch, the j+1th group of data includes m sub-pixel data.

In a third feasible embodiment, the source drive circuit includes: the shift register, the sampling latch coupled to the shift register, a holding latch coupled to the sampling latch, a level shifter coupled to the holding latch, a digital-to-analog converter coupled to the level shifter, and N drivers coupled to the digital-to-analog converter, and the source drive circuit further includes: a A multiplexer is coupled between the holding latch and the level shifter; wherein the holding latch transmits the jth set of data to the level shifter through the multiplexer, the jth set of data includes m sub-pixel data, and j is a positive integer; wherein the holding latch transmits the j+1th set of data to the level shifter through the multiplexer, and the j+1th set of data includes m sub-pixel data.

To achieve the above-mentioned purpose, the present invention also proposes a third embodiment of the pixel data copying method, which is executed by a display driver chip, wherein the display driver chip includes a source driver circuit with N driving channels, and the pixel data copying method includes: Let a shift register included in the source driver circuit generate N/m enable signals according to a clock signal; wherein each of the enable signals has a pulse width, and N and m are both positive integers; transmit a first display data received through a data transmission interface to a first-in-first-out register; read the first display data from the first-in-first-out register, and arrange the first display data into a second display data; wherein the first display data and the second display data are read from the first-in-first-out register; The data includes N/6 groups of RGB pixel data, each two groups of RGB pixel data in the second display data include the same content, the time taken by the data transmission interface to receive the first display data is (N/6)*T, the time taken by the data transmission interface to receive a group of RGB pixel data is T, and the width of each pulse is (m/3)*T; and the second display data is transmitted to a sampling latch included in the source drive circuit by using the data transmission bus, so that the sampling latch performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch after undergoing N/m times of the data latch operation.

Furthermore, the present invention also proposes an embodiment of a display device, which includes a display panel and at least one display driver chip, wherein the display driver chip executes the pixel data copying method of the present invention as described above when the resolution of the display device is reduced, thereby realizing pixel data copying while reducing the power consumption and time of data transmission.

Furthermore, the present invention also proposes an information processing device, which is characterized in that it has a display device, and the display includes a display panel and at least one display driver chip, and the display driver chip executes the pixel data copying method of the present invention as described above when the resolution of the display device is reduced, thereby realizing pixel data copying while reducing data transmission power consumption and time. In one embodiment, the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a tablet computer, a laptop computer, an all-in-one computer, a smart TV, a car entertainment device, an access control device, a clock-in device, and an electronic door lock.

1a: Liquid crystal display device

11a: LCD panel

12a: Display driver chip

120a: Gate drive unit

121a: Timing controller

122a: Source drive unit

123a: Source drive circuit

1231a: Shift register

1232a: Sampling latch

1233a: Keep lock register

1234a:Level shifter

1235a: Digital to Analog Converter

1236a:Driver

1237a: Gamma voltage generating unit

1: Display device

11: Display panel

12: Display driver chip

120: Gate drive unit

121: Timing controller

122: Source drive unit

123: Source drive circuit

1230:Multiplexer

1231: Shift register

1232: Sampling latch

1233: Keep lock register

1234:Level shifter

1235: Digital to Analog Converter

1236:Driver

1237: Gamma voltage generating unit

S1: Multiply a first clock signal into a second clock signal, so that a shift register included in the source drive circuit generates N/m enable signals according to the second clock signal.

S2: Arrange a first display data received through a data transmission interface into a second display data

S3: Using a data transmission bus to transmit the second display data to a sampling latch included in the source drive circuit, so that the sampling latch performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal. Finally, the second display data is completely latched in the sampling latch after N/m times of the data latch operation.

S1a: A shift register included in the source drive circuit generates N/2m first enable signals and N/2m second enable signals according to a clock signal

S2a: Receive a first display data through a data transmission interface

S3a: Arrange the first display data into a second display data

S4a: Using a data transmission bus to transmit the second display data to a sampling latch included in the source drive circuit, the sampling latch performs a first data latch operation on the m sub-pixel data of the second display data according to the first enable signal, and performs a second data latch operation on the m sub-pixel data of the second display data according to the second enable signal. Finally, the second display data is completely latched in the sampling latch after N/2m times of the first data latch operation and N/2m times of the second data latch operation.

S1b: A shift register included in the source drive circuit generates N/m enable signals according to a clock signal

S2b: Transmitting a first display data received through a data transmission interface to a first-in-first-out register

S3b: Read the first display data from the first-in-first-out register, and arrange the first display data into a second display data

S4b: Using the data transmission bus to transmit the second display data to a sampling latch included in the source drive circuit, the sampling latch performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch after N/m times of the data latch operation.

FIG. 1 is a block diagram of a known liquid crystal display device; FIG. 2 is a block diagram of the internal structure of a source drive circuit; FIG. 3 is a timing diagram of first display data, bus transmission data and N/m enable signals; FIG. 4 is a first block diagram of a source drive circuit; FIG. 5 is a second block diagram of a source drive circuit; FIG. 6 is a display device using a pixel data copying method of the present invention. FIG. 7 is a block diagram of an internal structure of a source driving circuit; FIG. 8 is a flow chart of a first embodiment of a pixel data copying method of the present invention; FIG. 9 is a timing chart of first display data, bus transmission data and N/m enable signals; FIG. 10 is a block diagram of a source driving circuit; FIG. 11 is a flow chart of a second embodiment of a pixel data copying method of the present invention; FIG12 is a timing diagram of the first display data, bus transmission data, N/2m first enable signals and N/2m second enable signals; FIG13A is a first block diagram of a sampling latch and a holding latch; FIG13B is a second block diagram of a sampling latch and a holding latch; FIG14A is a third block diagram of a sampling latch and a holding latch; FIG14B is a third block diagram of a sampling latch and a holding latch; FIG15A is a fourth block diagram of a sampling latch and a holding latch; FIG15B is a sixth block diagram of a sampling latch and a holding latch; FIG16 is a flow chart of the third embodiment of the pixel data copying method of the present invention; and FIG17 is a timing diagram of the first display data, bus transmission data and N/m enable signals.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

FIG6 is a block diagram of a display device to which a pixel data copying method of the present invention is applied. As shown in FIG6 , the display device 1 mainly includes: a display panel 11 and at least one display driver chip 12, wherein the display driver chip 12 includes: a timing controller 121, a source driver unit 122 and a gate driver unit 120. In a feasible embodiment, the display panel 11 is preferably an LCD panel, but can also be an OLED panel, an LED panel, or a QLED panel, and the display device 1 can be integrated into an electronic device, wherein the electronic device can be but is not limited to a smart phone, a smart watch, a tablet computer, a laptop computer, an all-in-one computer, a smart TV, a car entertainment device, an access control device, a clock-in device, or an electronic door lock. Furthermore, FIG. 7 is a block diagram of the internal structure of a source drive circuit. As shown in FIG. 6 and FIG. 7, the source drive unit 122 includes a source drive circuit 123 with N drive channels (CH1~CHn), wherein the source drive circuit 123 mainly includes: a shift register 1231, a sampling latch 1232, a holding latch 1233, a level shifter 1234, a digital-to-analog converter (DAC) 1235, N drivers 1236, and a gamma voltage generating unit 1237.

The present invention mainly discloses a pixel data copying method, which is applied in the display device 1, so that the display driver chip 12 executes the pixel data copying method of the present invention when the resolution of the display device 1 is reduced, thereby realizing pixel data copying while reducing data transmission power consumption and time. FIG8 is a flow chart of a first embodiment of the pixel data copying method of the present invention, which includes the following steps: Step S1: multiplying a first clock signal into a second clock signal, so that a shift register 1231 included in the source driving circuit 123 generates N/m enable signals according to the second clock signal; wherein each of the enable signals has a pulse width, and N and m are both positive integers; Step S2: receiving a first display signal received through a data transmission interface; The data is arranged into a second display data; and step S3: using a data transmission bus to transmit the second display data to a sampling latch 1232 included in the source drive circuit 123, so that the sampling latch 1232 performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch 1232 after N/m times of the data latch operation.

FIG9 is a timing diagram of the first display data, bus transmission data and N/m enable signals. As shown in FIG7 and FIG9, the time taken by the data transmission interface to receive the first display data is (N/6)*T, wherein the time taken by each set of RGB pixel data is T, and the enable time width of each enable signal No is (m/6)*T, and N and m are both positive integers. As shown in FIG9, the first display data and the second display data (i.e., bus transmission data) both include N/6 sets of RGB pixel data, and each two sets of RGB pixel data in the second display data include the same content. For example, RGB[1] is the first set of RGB pixel data including R1 sub-pixel data, B1 sub-pixel data, and G1 sub-pixel data, and RGB[2] is the second set of RGB pixel data including R2 sub-pixel data, B2 sub-pixel data, and G2 sub-pixel data. The second display data is generated by arranging two first display data in two rows, wherein the first set of data in the first row (i.e., RGB[1]) and the first set of data in the second row (i.e., RGB[1]) contain the same content, and the second set of data in the first row (i.e., RGB[2]) and the second set of data in the second row (i.e., RGB[2]) contain the same content, and so on.

According to the above plan, after the second display data is arranged, as shown in FIG. 9 , the second display data is sent to a data transmission bus (ie, data bus), and then transmitted to the sampling latch 1232 included in the source driving circuit 123 by the data transmission bus. Since the shift register 1231 generates N/m enable signals NO according to the clock signal and transmits them to the sampling latch 1232, the sampling latch 1232 performs a data latch operation on the m sub-pixel data of the second display data according to each of the enable signals NO. Finally, the second display data is completely latched in the sampling latch 1232 after N/m data latch operations. Furthermore, FIG10 is a block diagram of a source drive circuit. As shown in FIG. 7, FIG. 9 and FIG. 10, when the resolution of the display device 1 is reduced, each of the source drive circuits 123 will execute the pixel data copy method of the present invention, thereby enabling a pixel data copy function so that two adjacent pixels correspond to the same set of RGB data. For example, the data voltage (or data current) output by channels CH1~CH3 corresponds to the first set of RGB data (including R1/G1/B1), and the data voltage (or data current) output by channels CH4~CH6 also corresponds to the first set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data. Furthermore, the data voltage (or data current) output by channels CH7~CH9 corresponds to the second set of RGB data (including R2/G2/B2), and the data voltage (or data current) output by channels CH10~CH12 also corresponds to the second set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data.

In simple terms, to achieve pixel duplication, RGB1 needs to be repeatedly input to ensure that RGB2=RGB1 (i.e., each two sets of RGB pixel data contain the same content). Therefore, in the first embodiment, by adjusting the timing of the N/m pulse widths contained in the second clock signal and arranging the first display data received by the data transmission interface into the second display data, it is ensured that the data received by the two adjacent pixels are the same, thereby avoiding repeated input and reducing input time and power consumption. Here, the two adjacent pixels refer to two adjacent pixels on the display panel 11, and one pixel includes an R sub-pixel, a G sub-pixel, and a B sub-pixel.

Furthermore, the present invention also discloses a second embodiment of a pixel data copying method. FIG11 is a flow chart of the second embodiment of the pixel data copying method of the present invention, which includes the following steps: Step S1a: a shift register 1231 included in the source driving circuit 123 generates N/2m first enable signals and N/2m second enable signals according to a clock signal; wherein each of the first enable signals has a first pulse width, and each of the second enable signals has a first pulse width. There are two first pulse widths, and N and m are both positive integers; step S2a: receiving a first display data through a data transmission interface; wherein the first display data includes N/6 sets of RGB pixel data, the time taken by the data transmission interface to receive the first display data is (N/6)*T, the time taken by the data transmission interface to receive a set of RGB pixel data is T, and each of the first pulse widths The width of each of the second pulses is (m/3)*T; step S3a: arranging the first display data into a second display data; and step S4a: using a data transmission bus to transmit the second display data to a sampling latch 1232 included in the source driving circuit 123, so that the sampling latch 1232 is based on the first enable signal to the second display data. A first data latching operation is performed on the m sub-pixel data of the second display data, and a second data latching operation is performed on the m sub-pixel data of the second display data according to the second enable signal. Finally, the second display data is completely latched in the sampling latch 1232 after N/2m times of the first data latching operation and N/2m times of the second data latching operation.

FIG12 is a timing diagram of the first display data, bus transmission data, N/2m first enable signals and N/2m second enable signals. As shown in FIG7 and FIG12, the time taken by the data transmission interface to receive the first display data is (N/6)*T, wherein the time taken for each set of RGB pixel data is T. On the other hand, the N/2m first enable signals are respectively NO[1], NO[3], ..., NO[N/m-1], and the N/2m second enable signals are respectively NO[2], NO[4], ..., NO[N/m], and the first enable signal and each of the second enable signals have an enable time width of (m/3)*T, and N and m are both positive integers. As shown in FIG. 12 , the first display data includes N/6 groups of RGB pixel data, including: RGB[1], RGB[2], ..., RGB[N/6-1], and RGB[N/6]. Specifically, RGB[1] is the first group of RGB pixel data including R1 sub-pixel data, B1 sub-pixel data, and G1 sub-pixel data, and RGB[2] is the second group of RGB pixel data including R2 sub-pixel data, B2 sub-pixel data, and G2 sub-pixel data, and so on.

FIG. 13A is a first block diagram of a sampling latch and a holding latch, and FIG. 13B is a second block diagram of a sampling latch and a holding latch. As shown in FIG. 13A and FIG. 13B, in the second embodiment, a multiplexer 1230 may be further planned and arranged to be coupled between the sampling latch 1232 and the data transmission bus (i.e., the data bus). According to this arrangement, the second display data is sent to the data transmission bus, and then transmitted to the multiplexer 1230 by the data transmission bus. As shown in FIG13A , within the enable time width of the first enable signal (NO[1], NO[3], ... NO[N/m-1]) of the multiplexer, the jth group of data (e.g., RGB[1]) including m sub-pixel data is transmitted to the sampling latch 1232, so that the sampling latch 1232 performs the first data latch operation on the m sub-pixel data, where j is a positive integer. Furthermore, as shown in FIG. 13B , the multiplexer 1230 transmits the j+1th group of data (e.g., RGB[2]) including m sub-pixel data to the sampling latch 1232 within the enable time width of the second enable signal (NO[2], NO[4], ... NO[N/m]), so that the sampling latch 1232 performs the second data latch operation on the m sub-pixel data. Finally, after N/2m times of the first data latch operation and N/2m times of the second data latch operation, the second display data is completely latched in the sampling latch 1232. As shown in FIG. 7 , FIG. 12 and FIG. 10 , when the resolution of the display device 1 is reduced, each of the source driving circuits 123 will execute the pixel data copy method of the present invention, thereby enabling a pixel data copy function so that two adjacent pixels correspond to the same set of RGB data. For example, the data voltage (or data current) output by channels CH1 to CH3 corresponds to the first set of RGB data (including R1/G1/B1), and the data voltage (or data current) output by channels CH4 to CH6 also corresponds to the first set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data. Furthermore, the data voltage (or data current) output by channels CH7~CH9 corresponds to the second set of RGB data (including R2/G2/B2), and the data voltage (or data current) output by channels CH10~CH12 also corresponds to the second set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data.

Further, FIG. 14A is a third block diagram of a sampling latch and a holding latch, and FIG. 14B is a fourth block diagram of a sampling latch and a holding latch. As shown in FIG. 14A and FIG. 14B, in practice, a multiplexer 1230 may be further planned and arranged to be coupled between the holding latch 1233 and the sampling latch 1232. According to this arrangement, the second display data is sent to a data transmission bus (i.e., a data bus), and then transmitted to the holding latch 1233 by the data transmission bus. As shown in Figure 14A, the sampling latch 1232 latches the jth group of data (e.g., RGB[1]) within the enable time width of the first enable signal (NO[1], NO[3], ... NO[N/m-1]), and the multiplexer 1230 further transmits the RGB[1] latched in the sampling latch 1232 to the holding latch 1233. Furthermore, as shown in FIG14B, the sampling latch 1232 latches the j+1th set of data (e.g., RGB[2]) within the enable time width of the second enable signal (NO[2], NO[4], ... NO[N/m]), and the multiplexer 1230 further transmits the RGB[2] latched in the sampling latch 1232 to the holding latch 1233. As shown in FIG7, FIG12 and FIG10, when the resolution of the display device 1 is reduced, each of the source driving circuits 123 will execute the pixel data copy method of the present invention, thereby enabling a pixel data copy function so that two adjacent pixels correspond to the same set of RGB data. For example, the data voltage (or data current) output by channels CH1~CH3 corresponds to the first set of RGB data (including R1/G1/B1), and the data voltage (or data current) output by channels CH4~CH6 also corresponds to the first set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data. In addition, the data voltage (or data current) output by channels CH7~CH9 corresponds to the second set of RGB data (including R2/G2/B2), and the data voltage (or data current) output by channels CH10~CH12 also corresponds to the second set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data.

In addition, FIG15A is a fifth block diagram of a sampling latch and a holding latch, and FIG15B is a sixth block diagram of a sampling latch and a holding latch. As shown in FIG15A and FIG15B, in practice, a multiplexer 1230 may be further planned and arranged to be coupled between the holding latch 1233 and the level shifter 1234. According to this arrangement, the second display data is sent to a data transmission bus (i.e., a data bus), and then transmitted from the data transmission bus to the sampling latch 1232, and then transmitted from the sampling latch 1232 to the holding latch 1233. Next, as shown in FIG15A, the holding latch 1233 transmits the j-th group of data (e.g., RGB[1]) to the level shifter 1234 via the multiplexer 1230. Furthermore, as shown in FIG15B, the holding latch 1233 transmits the j+1-th group of data (e.g., RGB[2]) to the level shifter 1234 via the multiplexer 1230. As shown in FIG7, FIG12 and FIG10, when the resolution of the display device 1 is reduced, each of the source driving circuits 123 executes the pixel data copying method of the present invention, thereby enabling a pixel data copying function so that two adjacent pixels correspond to the same group of RGB data. For example, the data voltage (or data current) output by channels CH1~CH3 corresponds to the first set of RGB data (including R1/G1/B1), and the data voltage (or data current) output by channels CH4~CH6 also corresponds to the first set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data. In addition, the data voltage (or data current) output by channels CH7~CH9 corresponds to the second set of RGB data (including R2/G2/B2), and the data voltage (or data current) output by channels CH10~CH12 also corresponds to the second set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data.

Furthermore, the present invention also discloses a third embodiment of a pixel data copying method. FIG16 is a flow chart of the third embodiment of the pixel data copying method of the present invention, which includes the following steps: Step S1b: a shift register 1231 included in the source drive circuit 123 generates N/m enable signals according to a clock signal; wherein each of the enable signals has a pulse width, and N and m are both positive integers; Step S2b: a first display data received through a data transmission interface is transmitted to a first-in-first-out (FIFO) register; Step S3b: the first display data is read from the first-in-first-out register, and the first display data is arranged into a second display data; wherein the first display data and the second display data both include N/6 sets of RGB pixel data, and the second display data includes N/6 sets of RGB pixel data. In the display data, each two groups of RGB pixel data contain the same content, the time taken by the data transmission interface to receive the first display data is (N/6)*T, the time taken by the data transmission interface to receive a group of RGB pixel data is T, and the width of each pulse is (m/3)*T; and step S4b: using the data transmission bus to transmit the second display data to a sampling latch 1232 included in the source drive circuit 123, so that the sampling latch 1232 performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch 1232 after N/m times of the data latch operation.

FIG. 17 is a timing diagram of the first display data, bus transmission data and N/m enable signals. As shown in FIG. 7 and FIG. 17, the time taken by the data transmission interface to receive the first display data is (N/6)*T, wherein the time taken for each set of RGB pixel data is T. On the other hand, the N/m enable signals are respectively NO[1], NO[2], ..., NO[N/m-1], NO[N/m], and each of the enable signals has an enable time width of (m/3)*T. As shown in FIG. 17, the first display data and the second display data (i.e., bus transmission data) both include N/6 sets of RGB pixel data, and each two sets of RGB pixel data in the second display data include the same content. For example, RGB[1] is the first set of RGB pixel data including R1 sub-pixel data, B1 sub-pixel data, and G1 sub-pixel data, and RGB[2] is the second set of RGB pixel data including R2 sub-pixel data, B2 sub-pixel data, and G2 sub-pixel data. The second display data is generated by arranging two first display data in two rows, wherein the first set of data in the first row (i.e., RGB[1]) and the first set of data in the second row (i.e., RGB[1]) contain the same content, and the second set of data in the first row (i.e., RGB[2]) and the second set of data in the second row (i.e., RGB[2]) contain the same content, and so on.

According to the above plan, after the arrangement of the second display data is completed, as shown in FIG. 17 , the second display data is sent to a data transmission bus (i.e., bus data bus). Since the shift register 1231 generates N/m enable signals NO according to the clock signal and transmits them to the sampling latch 1232, the sampling latch 1232 performs a data latch operation on the m sub-pixel data of the second display data according to each enable signal NO, that is, the second display data is read from the first-in-first-out register and the m sub-pixel data is latched. Finally, after N/m times of the data latch operation, the second display data is completely latched in the sampling latch 1232. Furthermore, FIG. 10 is a block diagram of a source driver circuit. As shown in FIG. 7, FIG. 9 and FIG. 10, when the resolution of the display device 1 is reduced, each of the source driver circuits 123 will execute the pixel data copying method of the present invention, thereby enabling a pixel data copying function so that two adjacent pixels correspond to the same set of RGB data. For example, the data voltage (or data current) output by channels CH1~CH3 corresponds to the first set of RGB data (including R1/G1/B1), and the data voltage (or data current) output by channels CH4~CH6 also corresponds to the first set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data. Moreover, the data voltage (or data current) output by channels CH7~CH9 corresponds to the second set of RGB data (including R2/G2/B2), and the data voltage (or data current) output by channels CH10~CH12 also corresponds to the second set of RGB data, that is, two adjacent pixels correspond to the same set of RGB data.

It is additionally explained that since the time taken by the data transmission interface to receive the first display data is (N/6)*T, there is a time difference between it and the sum of the enable time widths of the N/m enable signals (i.e., (m/3)*T*(N/m)=(N/3)*T). Therefore, the first display data must be stored in the FIFO register first, and then the second display data formed by the first display data is transmitted to the sampling latch 1232.

As can be seen from the above, the present invention discloses a pixel data duplication method, which is executed by a display driver chip, wherein the display driver chip includes a source driver circuit with N drive channels, N is a positive integer multiple of 6, and the pixel data duplication method includes: receiving N/6 sets of RGB data within N/6 clock cycles of the clock signal under the control of a clock signal; and Generate at least one set of enable pulse signals to repeatedly lock each of the N/6 sets of RGB data in two storage units of the N/3 sets of storage units of a retention latch within N/6 clock cycles, wherein the at least one set of enable pulse signals has a total of N/3 pulses within the N/6 clock cycles, and each set of the storage units of the retention latch corresponds to the three drive channels.

Thus, the above has completely and clearly explained the pixel data copying method of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention provides a pixel data copying method, which is applied to a display device including a display panel and at least one display driver chip, so that the display driver chip executes the pixel data copying method of the present invention when the resolution of the display device is reduced, thereby realizing pixel data copying while reducing data transmission power consumption and time.

(2) In addition, the present invention also provides an embodiment of a display device, which includes a display panel and at least one display driver chip, wherein the display driver chip executes the pixel data copying method of the present invention as described above when the resolution of the display device is reduced, thereby realizing pixel data copying while reducing data transmission power consumption and time.

(3) Furthermore, the present invention also provides an information processing device, which is characterized by having a display device as described above.

It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

S1: Multiply a first clock signal into a second clock signal, so that a shift register included in the source drive circuit generates N/m enable signals according to the second clock signal.

S2: Arrange a first display data received through a data transmission interface into a second display data

S3: Using a data transmission bus to transmit the second display data to a sampling latch included in the source drive circuit, so that the sampling latch performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal. Finally, the second display data is completely latched in the sampling latch after N/m times of the data latch operation.

Claims (13)

A pixel data duplication method is performed by a display driver chip, wherein the display driver chip includes a source driver circuit with N driving channels, and the pixel data duplication method includes: multiplying a first clock signal into a second clock signal, so that a shift register included in the source driver circuit generates N/m enable signals according to the second clock signal; wherein each of the enable signals has a pulse width, and N and m are both positive integers; arranging a first display data received through a data transmission interface into a second display data; wherein the first display data and the second display data both include N/6 sets of RGB pixel data, and the second display data includes N/6 sets of RGB pixel data. Each two groups of RGB pixel data in the display data contain the same content, the time taken by the data transmission interface to receive the first display data is (N/6)*T, the time taken by the data transmission interface to receive a group of RGB pixel data is T, and the width of each pulse is (m/6)*T; and the second display data is transmitted to a sampling latch included in the source drive circuit by using a data transmission bus, so that the sampling latch performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch after N/m times of the data latch operation. A display device includes a display panel and at least one display driver chip, wherein the display driver chip executes the pixel data copying method as described in claim 1 when the resolution of the display device is reduced. A pixel data copying method is performed by a display driver chip, wherein the display driver chip includes a source driver circuit with N driving channels, and the pixel data copying method includes: allowing a shift register included in the source driver circuit to generate N/2m first enable signals and N/2m second enable signals according to a clock signal; wherein each of the first enable signals has a first pulse width, each of the second enable signals has a second pulse width, and N and m are both positive integers; receiving a first display data through a data transmission interface; wherein the first display data includes N/6 sets of RGB pixel data, the time taken by the data transmission interface to receive the first display data is (N/6)*T, and the data transmission interface receives a set of RGB pixel data. The time taken for the first display data to be displayed is T, the width of each first pulse is (m/3)*T, and the width of each second pulse is (m/3)*T; the first display data is arranged into a second display data; and the second display data is transmitted to a sampling latch included in the source driving circuit by using a data transmission bus, so that the sampling latch is based on the first enable signal to the first display data. A first data latching operation is performed on the m sub-pixel data of the second display data, and a second data latching operation is performed on the m sub-pixel data of the second display data according to the second enable signal. Finally, the second display data is completely latched in the sampling latch after N/2m times of the first data latching operation and N/2m times of the second data latching operation. The pixel data copying method as described in claim 3, wherein the source driving circuit comprises: the shift register, the sampling latch coupled to the shift register, a holding latch coupled to the sampling latch, a level shifter coupled to the holding latch, a digital-to-analog converter coupled to the level shifter, and N drivers coupled to the digital-to-analog converter, and the source driving circuit further comprises: a multiplexer coupled between the sampling latch and the data transmission bus; wherein the multiplexer transmits the jth group of data including m sub-pixel data to the sampling latch within an enabling time period of the first enabling signal, so that the sampling latch performs the first data latching operation on the m sub-pixel data, and j is a positive integer; wherein the multiplexer transmits the j+1th group of data including m sub-pixel data to the sampling latch within an enabling time period of the second enabling signal, so that the sampling latch performs the second data latching operation on the m sub-pixel data. The pixel data copying method as described in claim 3, wherein the source driving circuit includes: the shift register, the sampling latch coupled to the shift register, a holding latch coupled to the sampling latch, a level shifter coupled to the holding latch, a digital-to-analog converter coupled to the level shifter, and N drivers coupled to the digital-to-analog converter, and the source driving circuit further includes: a multiplexer coupled between the holding latch and the sampling latch; wherein the sampling latch is a level shifter coupled to the holding latch; The jth group of data is locked in the enabling time period of the first enabling signal, and the multiplexer further transmits the jth group of data locked in the sampling latch to the holding latch, the jth group of data includes m sub-pixel data, and j is a positive integer; wherein, the sampling latch locks the j+1th group of data in the enabling time period of the second enabling signal, and the multiplexer further transmits the j+1th group of data locked in the sampling latch to the holding latch, the j+1th group of data includes m sub-pixel data. The pixel data copying method as described in claim 3, wherein the source driving circuit includes: the shift register, the sampling latch coupled to the shift register, a holding latch coupled to the sampling latch, a level shifter coupled to the holding latch, a digital-to-analog converter coupled to the level shifter, and N drivers coupled to the digital-to-analog converter, and the source driving circuit further The step includes: a multiplexer coupled between the holding latch and the level shifter; wherein the holding latch transmits the jth set of data to the level shifter through the multiplexer, the jth set of data includes m sub-pixel data, and j is a positive integer; wherein the holding latch transmits the j+1th set of data to the level shifter through the multiplexer, and the j+1th set of data includes m sub-pixel data. A display device includes a display panel and at least one display driver chip, wherein the display driver chip executes a pixel data copying method as described in any one of claim 3 to claim 6 when the resolution of the display device is reduced. A pixel data copying method is performed by a display driver chip, wherein the display driver chip includes a source driver circuit with N driving channels, and the pixel data copying method includes: allowing a shift register included in the source driver circuit to generate N/m enable signals according to a clock signal; wherein each of the enable signals has a pulse width, and N and m are both positive integers; transmitting a first display data received through a data transmission interface to a first-in-first-out register; reading the first display data from the first-in-first-out register, and arranging the first display data into a second display data; wherein the first display data and the second display data both include N/6 groups of RGB pixel data, each two groups of RGB pixel data in the second display data contain the same content, the time taken by the data transmission interface to receive the first display data is (N/6)*T, the time taken by the data transmission interface to receive a group of RGB pixel data is T, and the width of each pulse is (m/3)*T; and the second display data is transmitted to a sampling latch included in the source drive circuit by using the data transmission bus, so that the sampling latch performs a data latch operation on the m sub-pixel data of the second display data according to an enable signal, and finally the second display data is completely latched in the sampling latch after N/m times of the data latch operation. A pixel data duplication method is performed by a display driver chip, wherein the display driver chip includes a source driver circuit with N driver channels, N being a positive integer multiple of 6, and the pixel data duplication method includes: receiving N/6 sets of RGB data within N/6 clock cycles of the clock signal under the control of a clock signal; and generating at least one set of RGB data according to the clock signal. The enable pulse signal is used to repeatedly lock N/6 groups of RGB data in two storage units of N/3 storage units of a retention latch within N/6 clock cycles, wherein at least one group of enable pulse signals has a total of N/3 pulses within N/6 clock cycles, and each group of storage units of the retention latch corresponds to the three drive channels. A display device includes a display panel and at least one display driver chip, wherein the display driver chip executes the pixel data copying method as described in claim 8 or 9 when the resolution of the display device is reduced. An information processing device, characterized in that it has a display device as described in claim 2. An information processing device, characterized in that it has a display device as described in claim 7. An information processing device, characterized in that it has a display device as described in claim 10.

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