TWI888131B - Bidirectionally drivable buffer, electronic chip and information processing device - Google Patents

Abstract

The present invention mainly discloses a bidirectionally drivable buffer, comprising: a first P-type MOSFET element, a first N-type MOSFET element, a first logic unit, a second P-type MOSFET element, a second N-type MOSFET element, and a second logic unit, wherein the first P-type MOSFET element and the first N-type MOSFET element are stacked to form a first CMOS unit, the first logic unit is coupled between a first input/output terminal and the first CMOS unit, and the first CMOS unit is coupled to a second input/output terminal. In contrast, the second P-type MOSFET element and the second N-type MOSFET element are stacked to form a second CMOS unit, the second logic unit is coupled between the second input/output terminal and the second CMOS unit, and the second CMOS unit is coupled to the first input/output terminal.

Description

Bidirectionally drivable buffer, electronic chip and information processing device

The present invention relates to the technical field of display driver chips, and in particular to a bidirectional drive buffer with the function of reducing/eliminating peak current, which is applied to multiple source drive modules of the display driver chip.

FIG1 is a block diagram of a known flat panel display. As shown in FIG1 , the known flat panel display 1a mainly includes: a display panel 10a, at least one display driver chip 11a and a timing controller (Tcon) 12a, wherein the display driver chip 11a includes N source driver modules 111a for generating N display driver signals (i.e., data voltage or drive current) corresponding to the N source lines of the display panel 10a.

FIG2 is a block diagram of the N source driver modules 111a shown in FIG1. As shown in FIG2, the display driver chip 11a also has a display interface physical layer (D-PHY) 110a, and the display interface physical layer 110a is configured to receive display data (RGB DATA), clock signal (CLK) and other signals transmitted from the timing controller 12a, and transmit the display data and the clock signal to the N/2 source driver modules 111a on the left and the N/2 source driver modules 111a on the right. The physical layer is transmitted to each output channel. As shown in Figure 2, due to the large number of signal transmission channels and high signal frequency, a large peak current is easily generated when data is transmitted at a low voltage level as data is written. Relevant measurement data show that the peak current not only increases the overall power consumption of the display driver chip 12a, but also reduces the power supply voltage (VDD), thus causing a negative impact on the normal operation of the display driver chip 12a circuit.

Fig. 3 is an internal circuit block diagram of the source driver module 111a shown in Fig. 2. As shown in Fig. 3, the source driver module 111a generally includes: a shift register 1111a, a data latch 1112a, a level shifter 1113a, a digital-to-analog converter 1114a, a buffer 1115a, and an orthogonal multiplexer 1116a. Furthermore, in order to reduce the peak current derived from the change of the transmission signal, the prior art configures the display interface physical layer 110a and the digital-to-analog converter 1114a to have a code mapping function, and at the same time, configures the shift register 1111a to perform odd-even phase sampling and storage of the display data (i.e., RGB DATA) according to a first clock signal (CLK_EVEN) and a second clock signal (CLK_ODD).

For a flat panel display 1a with a medium or large screen, the display driver chip 11a used therein has relatively more drive channels. Therefore, in order to simplify the circuit layout of the display driver chip 11a, the prior art provides a display interface physical layer 110a on the left and right sides of the circuit layout of the display driver chip 11a. It is easy to understand that the display interface physical layer 110a on the left transmits the corresponding display data and clock signals to the N/2 source drive modules 111a on the left, while the display interface physical layer 110a on the right transmits the corresponding display data and clock signals to the N/2 source drive modules 111a on the right. It is worth noting that the aforementioned code mapping and odd-even phase sampling register can also be used to reduce peak current. However, due to the large number of drive channels, the circuit area of the display driver chip 11a used to drive the medium and large-sized display panel 10a is relatively large, so the buffer 1115a included in the source driver module 111a is required to have high drive capability and bidirectional drive function. Practical experience shows that when the buffer 1115a is designed to have high drive capability and bidirectional drive function, the peak current generated by the change of the transmission signal becomes significant.

To explain in more detail, FIG4 is a circuit topology diagram of the buffer 1115a shown in FIG3. As shown in FIG4, the conventional buffer 1115a is unidirectionally driven and includes: an inverter 1117a, a P-type MOSFET element 1118a, and an N-type MOSFET element 1119a cascoded with the P-type MOSFET element 1118a. On the other hand, FIG5 is a circuit topology diagram of a buffer having high driving capability and bidirectional driving function. As shown in FIG5 , the buffer 2a with high driving capability and bidirectional driving function includes: a first inverter 20a, a first P-type MOSFET element 21a, a second P-type MOSFET element 22a, a first N-type MOSFET element 23a, a second N-type MOSFET element 24a, a second inverter 25a, a third P-type MOSFET element 26a, a fourth P-type MOSFET element 27a, a third N-type MOSFET element 28a, and a fourth N-type MOSFET element 29a.

In order to further improve the driving capability, as shown in FIG. 4 and FIG. 5, the area (i.e., W×L) of the first P-type MOSFET element 21a, the second P-type MOSFET element 22a, the third P-type MOSFET element 26a, and the fourth P-type MOSFET element 27a are all the same as the P-type MOSFET element 1118a. It can be seen that, in terms of the P-type MOSFET element, the total area of the buffer 2a with high driving capability and bidirectional driving function is 8 times that of the buffer 1115a.

In summary, for a display driver chip 11a used to drive a medium or large-sized display panel 10a, if the buffer 1115a (as shown in FIG. 3 and FIG. 4 ) of its source driver module 111a is replaced with a buffer 2a (as shown in FIG. 5 ) having a high driving capability and a bidirectional driving function, not only will the peak current become significant, but the circuit area of the buffer of the source driver module 111a will also increase exponentially. In view of this, it should be considered to redesign or improve the buffer 2a having a high driving capability and a bidirectional driving function as shown in FIG. 5 , so that its circuit area can be effectively reduced while retaining the function of reducing/eliminating the peak current.

From the above description, it can be seen that a bidirectionally driven buffer is urgently needed in this field.

The main purpose of the present invention is to provide a bidirectionally drivable buffer for integration into a source drive module. It is worth mentioning that the circuit area ratio of the known unidirectionally driven buffer, the known buffer with high driving capability and bidirectional driving function, and the bidirectionally drivable buffer of the present invention is 1:8:2. In other words, the circuit area of the bidirectionally drivable buffer of the present invention is only twice that of the known unidirectionally driven buffer, and 1/4 of that of the known buffer with high driving capability and bidirectional driving function. Therefore, compared with the known buffer with high driving capability and bidirectional driving function, the circuit cost of the bidirectionally drivable buffer of the present invention is significantly reduced by 75%.

Furthermore, after a first latch unit is provided between a first input/output terminal of the bidirectionally drivable buffer and the first logic unit and a second latch unit is provided between a second input/output terminal of the bidirectionally drivable buffer and the second logic unit, by controlling the working timing of the first latch unit and the first latch unit, the output of the buffer can be set to 0 potential or 1 potential before the buffer is enabled and after it is turned off, thereby achieving the specific effect of greatly reducing (or eliminating) the peak current. At the same time, the additional effects of reducing power drop and eliminating circuit EMI (electromagnetic interference) can also be achieved.

In order to achieve the above-mentioned purpose, a bidirectionally drivable buffer is proposed, which includes: a first P-type MOSFET element, having a gate terminal, a source terminal and a drain terminal, wherein the source terminal is coupled to a working voltage; a first N-type MOSFET element, having a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the first P-type MOSFET element are coupled to a first common point; a first logic unit, having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the first P-type MOSFET element, the second output terminal is coupled to the gate terminal of the first N-type MOSFET element, the second input terminal is coupled to a first control signal, and the third input terminal is coupled to a second control signal; a second P-type MOSFET element having a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to the drain terminal of the first N-type MOSFET element; a second N-type MOSFET element having a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the second P-type MOSFET element are coupled to a second common point; and a second logic unit having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the second P-type MOSFET element, and the second output terminal is coupled to the drain terminal of the second P-type MOSFET element. The gate terminal of the second N-type MOSFET element, the second input terminal is coupled to the second control signal, and the third input terminal is coupled to the first control signal; wherein the first input terminal of the first logic unit is coupled to a first input/output terminal of the bidirectionally drivable buffer, and is also coupled to the second common point; wherein the first input terminal of the second logic unit is coupled to a second input/output terminal of the bidirectionally drivable buffer, and is also coupled to the first common point.

In one embodiment, the first logic unit includes: a first AND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal respectively serve as the second input terminal and the first output terminal of the first logic unit; and a first NOR gate, also having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal respectively serve as the third input terminal and the second output terminal of the first logic unit; wherein the second gate input terminal of the first NAND gate and the first gate input terminal of the first NOR gate are both coupled to the first input terminal of the first logic unit.

In one embodiment, the second logic unit includes: a second NAND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal respectively serve as the second input terminal and the first output terminal of the second logic unit; and a second NOR gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal respectively serve as the third input terminal and the second output terminal of the second logic unit; wherein the second gate input terminal of the second NAND gate and the first gate input terminal of the second NOR gate are both coupled to the first input terminal of the second logic unit.

In a feasible embodiment, the bidirectionally drivable buffer further includes a first latch unit coupled between the first input terminal and the first input/output terminal of the first logic unit, and the first latch unit includes: a first inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the first logic unit; a first switch element having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first input/output terminal, and the second terminal is coupled to the first inverter. The input terminal, and the control terminal is coupled to a first switch control signal; a second inverter, having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the first logic unit and the output terminal of the first inverter; a second switch element, having a first terminal, a second terminal and a control terminal, wherein the first terminal is simultaneously coupled to the first input/output terminal and the first terminal of the first switch element, the second terminal is coupled to the input terminal of the second inverter, and the control terminal is coupled to a second switch control signal.

In another feasible embodiment, the bidirectionally drivable buffer further includes a second latch unit coupled between the first input terminal and the second input/output terminal of the second logic unit, and the second latch unit includes: a third inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the second logic unit; a third switch element having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the second input/output terminal, and the first terminal is coupled to the output terminal of the third inverter; The input terminal, and the control terminal is coupled to the first switch control signal; a fourth inverter, having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the second logic unit and the output terminal of the third inverter; a fourth switch element, having a first terminal, a second terminal and a control terminal, wherein the second terminal is simultaneously coupled to the second input/output terminal and the first terminal of the third switch element, the first terminal is coupled to the input terminal of the fourth inverter, and the control terminal is coupled to the second switch control signal.

In order to achieve the above-mentioned purpose, the present invention further proposes a bidirectionally drivable buffer, which has: a first end and a second end; a first gate buffer circuit, having a first input end, a first pair of control ends and a first output end, the first input end is coupled to the first end, the first pair of control ends is coupled to a pair of first complementary control signals, and the first output end is coupled to the second end; and a second gate buffer circuit, having a second input end, a second pair of control ends and a second output end, the second input end is coupled to the second end, the second pair of control ends is coupled to a pair of second complementary control signals, and the second output end is coupled to the first end, wherein the pair of second complementary control signals is the inverse signal of the pair of first complementary control signals.

Furthermore, the present invention also provides an electronic chip, which is used to drive a display panel, and contains a plurality of source drive modules; the characteristic is that each of the source drive modules has at least one bidirectionally drivable buffer, and the bidirectionally drivable buffer includes: a first P-type MOSFET element, having a gate terminal, a source terminal and a drain terminal, wherein the source terminal is coupled to a working voltage; a first N-type MOSFET element, having a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the first P-type MOSFET element are coupled to a first common point; a first logic unit having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the first P-type MOSFET element, the second output terminal is coupled to the gate terminal of the first N-type MOSFET element, the second input terminal is coupled to a first control signal, and the third input terminal is coupled to a second control signal; a second P-type MOSFET A T element having a gate terminal, a source terminal and a drain terminal, wherein the source terminal is coupled to the working voltage; a second N-type MOSFET element having a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the second P-type MOSFET element are coupled to a second common point; a second logic unit having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the second P-type MOSFET element. The gate terminal of the device, the second output terminal is coupled to the gate terminal of the second N-type MOSFET element, the second input terminal is coupled to the second control signal, and the third input terminal is coupled to the first control signal; wherein the first input terminal of the first logic unit is coupled to a first input/output terminal of the bidirectionally drivable buffer, and is also coupled to the second common point; wherein the first input terminal of the second logic unit is coupled to a second input/output terminal of the bidirectionally drivable buffer, and is also coupled to the first common point.

In one embodiment, the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip.

In one embodiment, the first logic unit includes: a first NAND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal respectively serve as the second input terminal and the first output terminal of the first logic unit; and a first NOR gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal respectively serve as the third input terminal and the second output terminal of the first logic unit; wherein the second gate input terminal of the first NAND gate and the first gate input terminal of the first NOR gate are both coupled to the first input terminal of the first logic unit.

In one embodiment, the second logic unit includes: a second NAND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal respectively serve as the second input terminal and the first output terminal of the second logic unit; and a second NOR gate, also having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal respectively serve as the third input terminal and the second output terminal of the second logic unit; wherein the second gate input terminal of the second NAND gate and the first gate input terminal of the second NOR gate are both coupled to the first input terminal of the second logic unit.

In a feasible embodiment, the bidirectionally drivable buffer further includes a first latch unit coupled between the first input terminal and the first input/output terminal of the first logic unit, and the first latch unit includes: a first inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the first logic unit; a first switch element having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first input/output terminal, and the second terminal is coupled to the first inverter. The input terminal, and the control terminal is coupled to a first switch control signal; a second inverter, having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the first logic unit and the output terminal of the first inverter; a second switch element, having a first terminal, a second terminal and a control terminal, wherein the first terminal is simultaneously coupled to the first input/output terminal and the first terminal of the first switch element, the second terminal is coupled to the input terminal of the second inverter, and the control terminal is coupled to a second switch control signal.

In another feasible embodiment, the bidirectional drive buffer further includes a second latch unit coupled between the first input terminal and the second input/output terminal of the second logic unit, and the second latch unit includes: a third inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the second logic unit; a third switch element having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the second input/output terminal, and the first terminal is coupled to the output terminal of the third inverter; An input terminal, and the control terminal is coupled to the first switch control signal; a fourth inverter, having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the second logic unit and the output terminal of the third inverter; a fourth switch element, having a first terminal, a second terminal and a control terminal, wherein the second terminal is simultaneously coupled to the second input/output terminal and the first terminal of the third switch element, the first terminal is coupled to the input terminal of the fourth inverter, and the control terminal is coupled to the second switch control signal.

The present invention also provides an electronic chip, which is used to drive a display panel, and contains a plurality of source drive modules; the characteristic is that each of the source drive modules has at least one bidirectional drive buffer, and the bidirectional drive buffer includes: a first end and a second end; a first gate control buffer circuit, having a first input end, a first pair of control ends and a first output end, the first input end is coupled to the first end, the The first pair of control terminals is coupled to a pair of first complementary control signals, and the first output terminal is coupled to the second terminal; and a second gate buffer circuit has a second input terminal, a second pair of control terminals and a second output terminal, the second input terminal is coupled to the second terminal, the second pair of control terminals is coupled to a pair of second complementary control signals, and the second output terminal is coupled to the first terminal, wherein the pair of second complementary control signals is an inverted signal of the pair of first complementary control signals.

Furthermore, the present invention also provides an information processing device having at least one display device, and the feature of the display device is that the display device has a display panel and at least one electronic chip of the present invention as described above.

In a possible embodiment, the information processing device may be a multimedia information display device (KIOSK), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a laptop computer, an in-vehicle entertainment device, a digital camera, or a video door machine.

1a: Flat panel display

10a: Display panel

11a: Display driver chip

110a: Display interface entity layer

111a: Source driver module

1111a: shift register

1112a: Data lock register

1113a:Level shifter

1114a: Digital to Analog Converter

1115a: Buffer

1116a: Orthogonal multiplexer

1117a: Inverter

1118a: P-type MOSFET element

1119a: N-type MOSFET element

12a: Timing controller

2a: Buffer with high drive capability and bidirectional drive function

20a: First inverter

21a: First P-type MOSFET element

22a: Second P-type MOSFET element

23a: First N-type MOSFET element

24a: Second N-type MOSFET element

25a: Second inverter

26a: The third P-type MOSFET element

27a: Fourth P-type MOSFET element

28a: The third N-type MOSFET element

29a: The third N-type MOSFET element

1: Display device

11: Display panel

12: Electronic chips

121: Source driver module

2: Bidirectionally drivable buffer

21: First P-type MOSFET element

22: First N-type MOSFET element

23: First logic unit

231: The first anti-gate

232: First reverse or gate

24: Second P-type MOSFET element

25: Second N-type MOSFET element

26: Second logic unit

261: Second anti-gate

262: Second reverse or gate

27: First locking unit

271: First inverter

272: First switch element

273: Second inverter

274: Second switch element

28: Second locking unit

281: The third inverter

282: The third switch element

283: The fourth inverter

284: The fourth switch element

FIG. 1 is a block diagram of a known flat panel display; FIG. 2 is a block diagram of N source drive modules shown in FIG. 1; FIG. 3 is a block diagram of the internal circuit of the source drive module shown in FIG. 2; FIG. 4 is a circuit topology of the buffer shown in FIG. 3; FIG. 5 is a circuit topology of a buffer with high driving capability and bidirectional driving function; FIG. 6 is a block diagram of a display device including a bidirectionally drivable buffer of the present invention; FIG. 7 is a first circuit diagram of a bidirectionally drivable buffer of the present invention; and FIG. 8 is a second circuit diagram of the bidirectionally drivable buffer of the present invention.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

FIG. 6 is a block diagram of a display device including a bidirectionally driveable buffer according to the present invention. As shown in FIG. 6 , the display device 1 includes a display panel 11 and at least one electronic chip 12 for driving the display panel 11 to display images. In a feasible embodiment, the electronic chip 12 may be, but is not limited to, a display driver chip or a touch and display driver integration (TDDI) chip. Furthermore, the display panel 11 may be, but is not limited to, any one of the group consisting of a liquid crystal display panel, an OLED display panel, an LED display panel, and a Micro-LED display panel. To further explain, the electronic chip 12 contains a plurality of source drive modules 121, wherein each of the source drive modules 121 has at least one bidirectionally drivable buffer of the present invention.

FIG7 is a first circuit diagram of a bidirectionally drivable buffer of the present invention. As shown in FIG7 , the bidirectionally drivable buffer 2 of the present invention includes: a first P-type MOSFET element 21, a first N-type MOSFET element 22, a first logic unit 23, a second P-type MOSFET element 24, a second N-type MOSFET element 25, and a second logic unit 26, wherein the first P-type MOSFET element 21 has a gate terminal, a source terminal and a drain terminal, wherein the source terminal is coupled to an operating voltage. In contrast, the first N-type MOSFET element 22 has a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the first P-type MOSFET element 21 are coupled together at a first common point. On the other hand, the second P-type MOSFET element 24 has a gate terminal, a source terminal and a drain terminal, wherein the source terminal is coupled to the working voltage. In addition, the second N-type MOSFET element 25 has a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the second P-type MOSFET element 24 are coupled to a second common point.

According to the design of the present invention, as shown in FIG7 , the first logic unit 23 has a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the first P-type MOSFET element 21, the second output terminal is coupled to the gate terminal of the first N-type MOSFET element 22, the second input terminal is coupled to a first control signal, and the third input terminal is coupled to a second control signal. Specifically, the first logic unit 23 is composed of a first NAND gate 231 and a first NOR gate 232, and its first input terminal is coupled to a first input/output terminal of the bidirectionally drivable buffer 2 and is also coupled to the second common point. As shown in FIG7 , the first NAND gate 231 has a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal respectively serve as the second input terminal and the first output terminal of the first logic unit 23. On the other hand, the first NOR gate 232 also has a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal respectively serve as the third input terminal and the second output terminal of the first logic unit 23. It is worth noting that the second gate input terminal of the first NAND gate 231 and the first gate input terminal of the first NOR gate 232 are both coupled to the first input terminal of the first logic unit 23.

As shown in FIG7 , the second logic unit 26 has a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the second P-type MOSFET element 24, the second output terminal is coupled to the gate terminal of the second N-type MOSFET element 25, the second input terminal is coupled to the second control signal, and the third input terminal is coupled to the first control signal. Specifically, the second logic unit 26 is composed of a second NAND gate 261 and a second NOR gate 262, and its first input terminal is coupled to a second input/output terminal of the bidirectionally drivable buffer 2 and is also coupled to the first common point. As shown in FIG. 7 , the second NAND gate 261 has a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal respectively serve as the second input terminal and the first output terminal of the second logic unit 26. On the other hand, the second NOR gate 262 also has a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal respectively serve as the third input terminal and the second output terminal of the second logic unit 26. It is worth noting that the second gate input terminal of the second NAND gate 261 and the first gate input terminal of the second NOR gate 262 are both coupled to the first input terminal of the second logic unit 26.

For example, in normal operation, when the first control signal is at a high level (i.e., DIR=1) and the second control signal is at a low level (i.e., DIRB=0), the bidirectionally drivable buffer 2 of the present invention receives data at its first input/output end and transmits data at its second input/output end. Conversely, when the second control signal is at a high level (i.e., DIRB=1) and the first control signal is at a low level (i.e., DIR=0), the bidirectionally drivable buffer 2 of the present invention receives data at its second input/output end and transmits data at its first input/output end.

As can be seen from the above, the present invention discloses a bidirectionally drivable buffer, which has: a first end and a second end; a first gate buffer circuit, having a first input end, a first pair of control ends and a first output end, the first input end is coupled to the first end, the first pair of control ends is coupled to a pair of first complementary control signals, and the first output end is coupled to the second end; and a second gate buffer circuit, having a second input end, a second pair of control ends and a second output end, the second input end is coupled to the second end, the second pair of control ends is coupled to a pair of second complementary control signals, and the second output end is coupled to the first end, wherein the pair of second complementary control signals is the inverse signal of the pair of first complementary control signals.

In addition, it is worth mentioning that the circuit area ratio of the known unidirectional drive buffer (as shown in FIG. 4 ), the known buffer with high drive capability and bidirectional drive function (as shown in FIG. 5 ), and the bidirectional drive buffer of the present invention (as shown in FIG. 7 ) is 1:8:2. In other words, the circuit area of the bidirectional drive buffer 2 of the present invention is only twice that of the known unidirectional drive buffer, and 1/4 of that of the known buffer with high drive capability and bidirectional drive function. Therefore, it is easy to calculate that the circuit cost of the bidirectionally drivable buffer 2 of the present invention is significantly reduced by 75% compared with the known buffer with high drivability and bidirectional driving function.

Furthermore, FIG8 is a second circuit diagram of the bidirectionally drivable buffer of the present invention. As shown in FIG8, after a first latch unit 27 is set between the first input/output terminal and the first logic unit 23 and a second latch unit 28 is set between the second input/output terminal and the second logic unit 26, by controlling the working timing of the first latch unit 27 and the second latch unit 28, the output of the bidirectionally drivable buffer 2 can be set to 0 potential or 1 potential before enabling and after shutting down, thereby achieving the specific effect of greatly reducing (or eliminating) the peak current.

As shown in FIG8 , the first latch unit 27 is coupled between the first input terminal and the first input/output terminal of the first logic unit 23, and includes: a first inverter 271, a first switch element 272, a second inverter 273, and a second switch element 274, wherein the first inverter 271 has an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the first logic unit 23. In contrast, the second inverter 273 has an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the first logic unit 23 and the output terminal of the first inverter 271 at the same time. On the other hand, the first switch element 272 has a first end, a second end and a control end, wherein the first end is coupled to the first input/output end, the second end is coupled to the input end of the first inverter 271, and the control end is coupled to a first switch control signal. In addition, the second switch element 274 has a first end, a second end and a control end, wherein the first end is coupled to the first input/output end and the first end of the first switch element 272 at the same time, the second end is coupled to the input end of the second inverter 273, and the control end is coupled to a second switch control signal.

On the other hand, the second latch unit 28 is coupled between the first input terminal and the second input/output terminal of the second logic unit 26, and includes: a third inverter 281, a third switch element 282, a fourth inverter 283 and a fourth switch element 284, wherein the third inverter 281 has an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the second logic unit 26. In contrast, the fourth inverter 283 has an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the second logic unit 26 and the output terminal of the third inverter 281 at the same time. As shown in FIG8 , the third switch element 282 has a first end, a second end and a control end, wherein the second end is coupled to the second input/output end, the first end is coupled to the input end of the third inverter 281, and the control end is coupled to the first switch control signal. In addition, the fourth switch element 284 has a first end, a second end and a control end, wherein the second end is coupled to the second input/output end and the first end of the third switch element 282 at the same time, the first end is coupled to the input end of the fourth inverter 283, and the control end is coupled to the second switch control signal.

In this way, when the first switch control signal is at a high level (i.e., EN=1) and the second switch control signal is at a low level (i.e., ENB=0), the bidirectionally drivable buffer 2 of the present invention receives data (or transmits data) at its first input/output end and transmits data (or receives data) at its second input/output end. On the contrary, when the second switch control signal is at a high level (i.e., ENB=1) and the first switch control signal is at a low level (i.e., EN=0), the output of the bidirectionally drivable buffer 2 of the present invention latches on the last updated data. Therefore, when the EN/ENB level is reversed again, if the transmission data of the front-end circuit is not updated, the bidirectionally drivable buffer 2 of the present invention will not generate additional peak current. At the same time, it can also achieve the additional effect of reducing power drop and eliminating circuit EMI.

Thus, the above has completely and clearly described the bidirectionally drivable buffer of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention provides a bidirectionally drivable buffer for integration into a source drive module, and includes: a first P-type MOSFET component, a first N-type MOSFET component, a first logic unit, a second P-type MOSFET component, a second N-type MOSFET component, and a second logic unit. It is worth mentioning that the circuit area ratio of the known unidirectional drive buffer, the known buffer with high drive capability and bidirectional drive function, and the bidirectionally drivable buffer of the present invention is 1:8:2. In other words, the circuit area of the bidirectionally drivable buffer of the present invention is only twice that of the known unidirectionally drivable buffer, and 1/4 of the known buffer with high drivability and bidirectional drivability. Therefore, compared with the known buffer with high drivability and bidirectional drivability, the circuit cost of the bidirectionally drivable buffer of the present invention is significantly reduced by 75%.

(2) Further, after a first latch unit is provided between a first input/output terminal of the bidirectionally drivable buffer and the first logic unit and a second latch unit is provided between a second input/output terminal of the bidirectionally drivable buffer and the second logic unit, by controlling the working timing of the first latch unit and the second latch unit, the output of the buffer can be set to 0 potential or 1 potential before the buffer is enabled and after it is turned off, thereby achieving the specific effect of significantly reducing (or eliminating) the peak current. At the same time, the additional effects of reducing power drop and eliminating circuit EMI (electromagnetic interference) can also be achieved.

(3) In addition, the present invention also provides an electronic chip for driving a display panel, and includes a plurality of source drive modules; the characteristic of the electronic chip is that each of the source drive modules has at least one bidirectionally drivable buffer as described above.

(4) Furthermore, the present invention also provides an information processing device having at least one display device, and characterized in that the display device has a display panel and at least one electronic chip of the present invention as described above. In possible embodiments, the information processing device may be a multimedia information display device (KIOSK), a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a laptop computer, a car entertainment device, a digital camera or a video door machine.

It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the technology do not deviate from the scope of the patent rights of this case.

In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

2: Bidirectionally drivable buffer

21: First P-type MOSFET element

22: First N-type MOSFET element

23: First logic unit

231: The first anti-gate

232: First reverse or gate

24: Second P-type MOSFET element

25: Second N-type MOSFET element

26: Second logic unit

261: Second anti-gate

262: Second reverse or gate

Claims (12)

A bidirectionally drivable buffer comprises: A first P-type MOSFET element having a gate terminal, a source terminal and a drain terminal, wherein the source terminal is coupled to a working voltage; A first N-type MOSFET element having a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the first P-type MOSFET element are coupled to a first common point; A first logic unit having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the first P-type MOSFET element, the second output terminal is coupled to the gate terminal of the first N-type MOSFET element, the second input terminal is coupled to a first control signal, and the third input terminal is coupled to a second control signal; A second P-type MOSFET element having a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to the operating voltage; A second N-type MOSFET element having a gate terminal, a source terminal, and a drain terminal, wherein the drain terminal and the drain terminal of the second P-type MOSFET element are coupled together to a second common point; and A second logic unit has a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the second P-type MOSFET element, the second output terminal is coupled to the gate terminal of the second N-type MOSFET element, the second input terminal is coupled to the second control signal, and the third input terminal is coupled to the first control signal; wherein the first input terminal of the first logic unit is coupled to a first input/output terminal of the bidirectionally drivable buffer, and is also coupled to the second common point; wherein the first input terminal of the second logic unit is coupled to a second input/output terminal of the bidirectionally drivable buffer, and is also coupled to the first common point. A bidirectionally drivable buffer as described in claim 1, wherein the first logic unit comprises: a first AND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal serve as the second input terminal and the first output terminal of the first logic unit respectively; and a first NOR gate also having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal serve as the third input terminal and the second output terminal of the first logic unit respectively; Wherein, the second gate input terminal of the first AND gate and the first gate input terminal of the first OR gate are both coupled to the first input terminal of the first logic unit. A bidirectionally drivable buffer as described in claim 2, wherein the second logic unit comprises: a second NAND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal serve as the second input terminal and the first output terminal of the second logic unit respectively; and a second NOR gate also having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal serve as the third input terminal and the second output terminal of the second logic unit respectively; The second gate input terminal of the second AND gate and the first gate input terminal of the second OR gate are both coupled to the first input terminal of the second logic unit. The bidirectionally drivable buffer as described in claim 1 further includes a first latch unit coupled between the first input terminal and the first input/output terminal of the first logic unit, and the first latch unit includes: A first inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the first logic unit; A first switch element having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first input/output terminal, the second terminal is coupled to the input terminal of the first inverter, and the control terminal is coupled to a first switch control signal; A second inverter having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the first logic unit and the output terminal of the first inverter; and A second switch element has a first end, a second end and a control end, wherein the first end is coupled to the first input/output end and the first end of the first switch element at the same time, the second end is coupled to the input end of the second inverter, and the control end is coupled to a second switch control signal. The bidirectionally drivable buffer as described in claim 4 further includes a second latch unit coupled between the first input terminal and the second input/output terminal of the second logic unit, and the second latch unit includes: a third inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the second logic unit; a third switch element having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the second input/output terminal, the first terminal is coupled to the input terminal of the third inverter, and the control terminal is coupled to the first switch control signal; a fourth inverter having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the second logic unit and the output terminal of the third inverter; and A fourth switch element having a first end, a second end and a control end, wherein the second end is coupled to the second input/output end and the first end of the third switch element at the same time, the first end is coupled to the input end of the fourth inverter, and the control end is coupled to the second switch control signal. An electronic chip is used to drive a display panel, and contains a plurality of source drive modules; the characteristic is that each of the source drive modules has at least one bidirectionally drivable buffer, and the bidirectionally drivable buffer includes: A first P-type MOSFET element, having a gate terminal, a source terminal and a drain terminal, wherein the source terminal is coupled to a working voltage; A first N-type MOSFET element, having a gate terminal, a source terminal and a drain terminal, wherein the drain terminal and the drain terminal of the first P-type MOSFET element are coupled to a first common point; A first logic unit having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the first P-type MOSFET element, the second output terminal is coupled to the gate terminal of the first N-type MOSFET element, the second input terminal is coupled to a first control signal, and the third input terminal is coupled to a second control signal; A second P-type MOSFET element having a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is coupled to the operating voltage; A second N-type MOSFET element having a gate terminal, a source terminal, and a drain terminal, wherein the drain terminal and the drain terminal of the second P-type MOSFET element are coupled together to a second common point; A second logic unit has a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, wherein the first output terminal is coupled to the gate terminal of the second P-type MOSFET element, the second output terminal is coupled to the gate terminal of the second N-type MOSFET element, the second input terminal is coupled to the second control signal, and the third input terminal is coupled to the first control signal; wherein the first input terminal of the first logic unit is coupled to a first input/output terminal of the bidirectionally drivable buffer, and is also coupled to the second common point; wherein the first input terminal of the second logic unit is coupled to a second input/output terminal of the bidirectionally drivable buffer, and is also coupled to the first common point. An electronic chip as described in claim 6, wherein the electronic chip is any one selected from the group consisting of a display driver chip and a touch and display driver integration (TDDI) chip. An electronic chip as described in claim 6, wherein the first logic unit includes: a first AND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal serve as the second input terminal and the first output terminal of the first logic unit respectively; and a first NOR gate, also having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal serve as the third input terminal and the second output terminal of the first logic unit respectively; wherein the second gate input terminal of the first NAND gate and the first gate input terminal of the first NOR gate are both coupled to the first input terminal of the first logic unit. An electronic chip as described in claim 6, wherein the second logic unit includes: a second AND gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal and the gate output terminal serve as the second input terminal and the first output terminal of the second logic unit respectively; and a second NOR gate, also having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the second gate input terminal and the gate output terminal serve as the third input terminal and the second output terminal of the second logic unit respectively; wherein the second gate input terminal of the second NAND gate and the first gate input terminal of the second NOR gate are both coupled to the first input terminal of the second logic unit. An electronic chip as described in claim 6, wherein the bidirectionally drivable buffer further includes a first latch unit coupled between the first input terminal and the first input/output terminal of the first logic unit, and the first latch unit includes: A first inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the first logic unit; A first switch element having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first input/output terminal, the second terminal is coupled to the input terminal of the first inverter, and the control terminal is coupled to a first switch control signal; A second inverter having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the first logic unit and the output terminal of the first inverter; A second switch element has a first end, a second end and a control end, wherein the first end is coupled to the first input/output end and the first end of the first switch element at the same time, the second end is coupled to the input end of the second inverter, and the control end is coupled to a second switch control signal. An electronic chip as described in claim 10, wherein the bidirectionally drivable buffer further includes a second latch unit coupled between the first input terminal and the second input/output terminal of the second logic unit, and the second latch unit includes: a third inverter having an input terminal and an output terminal, and the output terminal is coupled to the first input terminal of the second logic unit; a third switch element having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the second input/output terminal, the first terminal is coupled to the input terminal of the third inverter, and the control terminal is coupled to the first switch control signal; a fourth inverter having an input terminal and an output terminal, and the output terminal is simultaneously coupled to the first input terminal of the second logic unit and the output terminal of the third inverter; A fourth switch element having a first end, a second end and a control end, wherein the second end is coupled to the second input/output end and the first end of the third switch element at the same time, the first end is coupled to the input end of the fourth inverter, and the control end is coupled to the second switch control signal. An information processing device has at least one display device, characterized in that the display device has a display panel and at least one electronic chip as described in any one of claim 6 to claim 11.

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