TWI892661B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes a substrate, multiple first bit line structures, multiple second bit line structures, a first contact, and a second contact. The substrate includes a device region and a dummy region. The first bit line structures are located on the substrate and in the device region. The second bit line structures are located on the substrate and in the dummy region. The first contact is located on the substrate and in the device region. The first contact is located between the first bit line contact structures. The second contact is located on the substrate and in the dummy region. The second contact is located between the second bit line contact structures.

Description

semiconductor structure

The present disclosure relates to a semiconductor structure and a method for manufacturing the same.

As the minimum feature width or critical dimension (CD) within semiconductor devices continues to shrink, the device density is increased and the size of the device is reduced. However, as the spacing between closely packed components decreases, the chance of short circuits in the conductive traces between components may also increase.

In view of this, how to provide a display device that can solve the above problems is still the goal of research and development in this field.

One technical aspect of the present disclosure is a semiconductor structure.

In one embodiment of the present disclosure, a semiconductor structure includes multiple active regions, multiple isolation regions, multiple bitline structures, and dummy contacts. The isolation regions separate the active regions. The bitline structures are located above the active regions and the isolation regions. The dummy contacts are located above the active regions and between the bitline structures. The dummy contacts have a bottom portion facing the active regions and separated from the active regions.

In one embodiment of the present disclosure, the semiconductor structure further includes a bit line spacer layer located at the bottom of the dummy contact.

In one embodiment of the present disclosure, the active area includes an edge portion and an inner portion, and the dummy contact element is located at the edge portion of the active area.

In one embodiment of the present disclosure, the plurality of bit line structures include a plurality of first bit line structures located inside the active region and a plurality of second bit line structures located at the edge of the active region.

In one embodiment of the present disclosure, the dummy contacts are located between the second bit line structures.

In one embodiment of the present disclosure, the semiconductor structure further includes a first contact located inside the active region.

In one embodiment of the present disclosure, the first contact is located between the first bit line structures.

In one embodiment of the present disclosure, the first contact extends into the active area.

In one embodiment of the present disclosure, the semiconductor structure further includes a bit line spacer layer located on the sidewalls of each of the first bit line structures and on the sidewalls of each of the second bit line structures.

In one embodiment of the present disclosure, the semiconductor structure further includes a bit line contact contacting the active region, wherein the bit line contact is located below one of the first bit line structures and electrically connected to the first bit line structure.

In the above-described embodiment, the second contact in the dummy region and the underlying inter-bitline spacer layer together fill the space between the second bitline structures. In other words, the second contact is a dummy contact. As a result, no current-carrying circuits are formed in the dummy region. The dummy region can be used to prevent short circuits between adjacent circuits in the active region. The oxide layer formed by the plasma process has good adhesion to the photoresist layer. This protects the second contact in the dummy region from etching during subsequent processing.

The following drawings disclose several embodiments of the present invention. For the sake of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, these practical details are not necessary in some embodiments of the present invention. In addition, to simplify the drawings, some commonly used structures and components will be depicted in a simple schematic manner in the drawings. For the sake of clarity, the thickness of layers and regions in the drawings may be exaggerated, and the same element symbols represent the same elements in the description of the drawings.

FIG1 is a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. The semiconductor structure 100 includes a substrate 110, a first bit line structure 120, a second bit line structure 130, a first contact 140, and a second contact 150.

The semiconductor structure 100 can be implemented in an integrated circuit (IC) or a component thereof, such as a logic circuit, a resistor, a capacitor, an inductor, or a memory (e.g., a dynamic random access memory (DRAM)). It should be understood that some elements of the semiconductor structure 100 are not shown in the figure, and other embodiments may include additional elements.

In some embodiments, substrate 110 may be a semiconductor substrate, such as a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate, wherein the insulator may be a buried oxide (BOX) layer or a silicon oxide layer. In some embodiments, the semiconductor material of substrate 110 may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), an alloy semiconductor, or a combination thereof. Substrate 110 may also be formed of other materials, such as sapphire or tin indium oxide.

A substrate 110 has a plurality of active regions 112 and a plurality of isolation regions 114 separating the active regions 112. The substrate 110 may be doped with N-type or P-type dopants through an ion implantation process. In some embodiments, source and drain regions (not shown) may be formed by doping the active regions 112 of the substrate 110 with N-type or P-type dopants. The isolation regions 114 may be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The substrate 110 includes a device region 1102 and a dummy region 1104. A first bit line structure 120 is located on the substrate 110 and in the device region 1102. A second bit line structure 130 is located on the substrate 110 and in the dummy region 1104. The device region 1102 and the dummy region 1104 are divided along a horizontal direction of the substrate 110, such as a first direction D1. A portion of the active region 112 is located in the device region 1102, and a portion is located in the dummy region 1104. Specifically, the dummy region 1104 corresponds to the edge of the active region 112 and is adjacent to other active regions (not shown). The device region 1102 corresponds to the interior of the active region 112.

The first bit line structure 120 and the second bit line structure 130 protrude from the substrate 110 along a second direction D2 perpendicular to the substrate 110. The first bit line structure 120 and the second bit line structure 130 extend along a direction parallel to the substrate 110, such as another horizontal direction different from the first direction D1.

The first bit line structure 120 and the second bit line structure 130 can be formed by stacking multiple layers of material. For example, the first bit line structure 120 includes a first conductive layer 124, a second conductive layer 126, and an insulating cap layer 128 stacked along a second direction D2. The first conductive layer 124 and the second conductive layer 126 are made of different materials. The first conductive layer 124 and the second conductive layer 126 can include polysilicon, a semiconductor material, a doped semiconductor material, a metal, a metal nitride, a metal silicide, other suitable conductive materials, or a combination thereof.

In other embodiments, the first conductive layer 124 and the second conductive layer 126 of the first cell line structure 120 may further include other conductive layers, such as a third conductive layer 125. The material of the insulating cap layer 128 may include silicon oxide, silicon nitride, other dielectric materials, or a combination thereof.

The second bit line structure 130 also includes a first conductive layer 134 , a third conductive layer 135 , a second conductive layer 136 , and an insulating cap layer 138 similar to the first bit line structure 120 .

The first bit line structure 120 and the second bit line structure 130 may further include isolation layers 129 and 139. The isolation layers 129 and 139 are located on the substrate 110 to isolate the first conductive layers 124 and 134 from the structures thereunder.

A first contact 140 is located on the substrate 110 in the device region 1102. The first contact 140 is located between the first bit line structure 120. The first contact 140 extends into the substrate 110. A second contact 150 is located on the substrate 110 in the dummy region 1104. The second contact 150 is located between the second bit line structure 130. The second contact 150 does not extend into the substrate 110.

The semiconductor structure 100 further includes a bitline contact 160. The bitline contact 160 is located in the substrate 110. The bitline contact 160 contacts the active region 112 and can be electrically connected to the active region 112. The bitline contact 160 is located below one of the first bitline structures 120 and is configured to electrically connect to the first bitline structure 120. The bitline contact 160 can also be located below one of the second bitline structures 130. The bitline contact 160 is made of a conductive material, such as polysilicon.

The semiconductor structure 100 further includes a bitline spacer layer 170. The bitline spacer layer 170 is located on the sidewalls 122 of the first bitline structure 120, the sidewalls 132 of the second bitline structure 130, and the bottom 152 of the second contact 150. The bitline spacer layer 170 prevents the first bitline structure 120 and the second bitline structure 130 from being damaged during subsequent manufacturing processes, thereby improving the reliability of the semiconductor structure 100.

The second contact 150 and the bitline spacer layer 170 located at the bottom 152 together fill the space between the second bitline structures 130. In other words, the second contact 150 is a dummy contact. As a result, no current-carrying lines are formed in the dummy region 1104. In other words, the dummy region 1104 prevents short circuits between lines in the active region 112 and adjacent lines.

It should be understood that the previously described device connection relationships, materials, and functions will not be repeated and will be described first. In the following description, the manufacturing method of the semiconductor structure 100 will be described.

Figures 2 through 7 are cross-sectional views illustrating intermediate steps of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Referring to Figure 2 , the method for fabricating semiconductor structure 100 begins by forming a first bit line structure 120 and a second bit line structure 130 in a device region 1102 and a dummy region 1104 , respectively, and forming a bit line spacer layer 170 to surround the first bit line structure 120 and the second bit line structure 130.

Specifically, in this step, the bitline spacer layer 170 conformally covers the first bitline structure 120 and the second bitline structure 130. Next, the second contacts 150 are formed between the first bitline structure 120 and the second bitline structure 130. Subsequently, a planarization process is performed to align the top surfaces of the first bitline structure 120, the second bitline structure 130, the second contacts 150, and the bitline spacer layer 170.

Refer to FIG. 3 . After forming the second contact 150, a plasma process P is used to form an oxide layer 180 over the first bit line structure 120, the second bit line structure 130, and the second contact 150. In this step, a dense oxide layer is formed using a high-temperature oxygen plasma or a hydrogen-nitrogen mixture plasma. Oxide layer 180 is formed on the top surface 120T of the first bit line structure 120, the top surface 130T of the second bit line structure 130, and the top surface 150T of the second contact 150.

Refer to FIG. 4 . After forming the oxide layer 180 using plasma, a photoresist layer 190 is formed on the oxide layer 180 in the dummy region 1104. The oxide layer 180 formed by the plasma process P has good adhesion to the photoresist layer 190. This protects the second contact 150 in the dummy region 1104 from being affected by the etching process in subsequent processes.

Refer to FIG. 5 . After forming a photoresist layer 190 in the dummy region 1104, the second contact 150 in the device region 1102 is removed. Specifically, the second contact 150 in the device region 1102 is removed by performing a wet etching process on the device region 1102 and the second contact 150 in the dummy region 1104, while retaining the second contact 150 in the dummy region 1104 through the photoresist layer 190. Due to the good adhesion between the oxide layer 180 and the photoresist layer 190, the wet etching process does not affect the second contact 150 in the dummy region 1104.

Generally, the top surface 150T of the second contact 150 and the top surface 130T of the second bit line structure 130 are naturally oxidized to form an oxide layer. However, such a natural oxide layer has poor adhesion to the photoresist layer 190, and thus cannot prevent the second contact 150 in the dummy region 1104 from being etched.

See FIG. 6 . After removing the second contact 150 in the device region 1102, the photoresist layer 190 is removed. During this step, the oxide layer 180 may remain over the second bit line structure 130 and the second contact 150 in the dummy region 1104. The oxide layer 180 in the dummy region 1104 may also provide protection during subsequent processing.

Refer to FIG. 7 . After removing the photoresist layer 190, the bitline spacer layer 170 previously located at the bottom 152 of the second contact 150 (see FIG. 2 ) in the device region 1102 is etched. In other words, the portion of the bitline spacer layer 170 extending horizontally (e.g., in the first direction D1) in the device region 1102 is etched. In this step, the oxide layer 180 in the dummy region 1104 may also be removed. Etching the bitline spacer layer 170 in the device region 1102 is performed using a dry etching process.

In some embodiments, the dry etching process in this step may also etch a portion of the second contact 150 in the dummy region 1104. However, since the second contact 150 is intact in the previous step, even if a portion of the second contact 150 is partially etched in the subsequent step, it will not affect the bit line spacer layer 170 at the bottom 152 of the second contact 150, thereby ensuring that the line in the dummy region 1104 is not conductive.

Returning to FIG. 1 , after the aforementioned steps, a first contact 140 is formed between the first bit line structures 120 in the device region 1102 . The first contact 140 passes through the bit line spacer layer 170 and extends into the substrate 110 .

In summary, the second contacts in the dummy region and the underlying inter-bitline spacer layer together fill the space between the second bitline structures. In other words, the second contacts are dummy contacts. This prevents the formation of current-carrying lines in the dummy region. The dummy region prevents short circuits between lines in the active region and adjacent lines. The oxide layer formed by the plasma process has excellent adhesion to the photoresist layer. This protects the second contacts in the dummy region from etching during subsequent processing.

Although the present invention has been disclosed in the form of embodiments as described above, it is not intended to limit the present invention. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Semiconductor structure 110: Substrate 1102: Component region 1104: Dummy region 112: Active region 114: Isolation region 120: First bit line structure 120T: Top surface 122: Sidewalls 124, 134: First conductive layer 125, 135: Third conductive layer 126, 136: Second conductive layer 128, 138: Insulating cap layer 129, 139: Isolation layer 130: Second bit line structure 130T: Top surface 132: Sidewalls 140: First contact 150: Second contact 150T: Top surface 152: Bottom surface 160: Bit line contacts 170: Bit line spacer 180: Oxide layer 190: Photoresist layer D1: First direction D2: Second direction P: Plasma process

Figure 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. Figures 2 through 7 are cross-sectional views of intermediate steps in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

100:Semiconductor structure

110: Base material

1102: Component Area

1104: Virtual District

112: Active Area

114: Isolation Area

120: First bit line structure

122: Sidewall

124,134: First conductive layer

125,135: Third conductive layer

126,136: Second conductive layer

128,138: Insulating covering layer

129,139: Isolation layer

130: Second bit line structure

132: Sidewall

140: First contact

150: Second contact

152: Bottom

160: Bit line contacts

170: Bit line spacing layer

D1: First Direction

D2: Second Direction

Claims (9)

A semiconductor structure includes: a plurality of active regions; a plurality of isolation regions separating the active regions; a plurality of bitline structures located above the active regions and the isolation regions, wherein the bitline structures include a plurality of first bitline structures and a plurality of second bitline structures; a dummy contact located above the active regions and between the bitline structures, the dummy contact having a bottom facing the active regions and separated from the active regions; and an inter-bitline spacer located below the dummy contact, wherein the dummy contact and the inter-bitline spacer located above the bottom together fill the space between the second bitline structures. The semiconductor structure as described in claim 1, wherein the active regions include an edge portion and an inner portion, and the dummy contact is located at the edge portion of the active regions. The semiconductor structure as described in claim 2, wherein the first bit line structures of the bit line structures are located in the inner part of the active regions, and the second bit line structures are located in the edge part of the active regions. The semiconductor structure of claim 1, wherein the dummy contact is located between the second bit line structures. The semiconductor structure as described in claim 2 further includes: a first contact located inside the active regions. A semiconductor structure as described in claim 5, wherein the first contact is located between the first bit line structures. A semiconductor structure as described in claim 5, wherein the first contact extends into the active regions. The semiconductor structure of claim 1, wherein the bit line spacer is located on a sidewall of each of the first bit line structures and on a sidewall of each of the second bit line structures. The semiconductor structure of claim 1 further comprises: a bit line contact contacting the active regions, wherein the bit line contact is located below one of the first bit line structures and electrically connected to the first bit line structures.