TWI779639B - Semiconductor structure and method of forming the same - Google Patents

Abstract

The present disclosure provides a semiconductor structure including a substrate, a metal bit line on the substrate, a bit line spacer on a sidewall of the metal bit line, a contact adjacent to the metal bit line. The semiconductor device includes a capping layer covering the metal bit line, the bit line spacer, and the contact, in which the capping layer includes a first portion covering a sidewall of the bit line spacer, a second portion covering a sidewall of the contact, and a third portion covering a top surface of the contact. The semiconductor structure includes an air gap between the first portion and the second portion of the capping layer, in which a top portion of the air gap inclines toward the bit line spacer, and the first portion and the third portion contacts each other above the air gap.

Description

Semiconductor structures and methods of forming them

The present disclosure relates to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures having air gaps and methods of forming the same.

As the minimum feature width or critical dimension (CD) in a semiconductor device continues to shrink, the device density of the semiconductor device is increased and the size of the device is reduced. However, as the pitch between closely arranged elements shrinks, the parasitic capacitance between elements may increase. Therefore, how to form a structurally complete air gap between elements to effectively reduce the parasitic capacitance of the device is an important development item for semiconductor devices.

According to an embodiment of the present disclosure, a semiconductor structure is provided that includes a substrate, metal bit lines on the substrate, bit line spacers on sidewalls of the metal bit lines, and contacts adjacent to the metal bit lines. The semiconductor structure includes a capping layer covering the metal bitlines, the bitline spacers, and the contacts, wherein the capping layer includes a first portion covering sidewalls of the bitline spacers, a second portion covering sidewalls of the contacts, and covering the contacts The third part of the top surface. The semiconductor structure includes an air gap between first and second portions of the capping layer, wherein a top portion of the air gap is sloped toward the bit line spacer, and the first and third portions of the capping layer contact each other above the air gap.

In an embodiment of the present disclosure, the bottom width of the air gap is larger than the top width.

In an embodiment of the present disclosure, the width of the bottom of the air gap is between 1 nm and 10 nm.

In an embodiment of the present disclosure, the upper width of the contact element is larger than the lower width.

In an embodiment of the present disclosure, the top surface of the contact has a first width, the portion of the contact that is coplanar with the top surface of the substrate has a second width, and the difference between the first width and the second width is between 5 nm and 20 nm.

In an embodiment of the present disclosure, the metal bit line includes a gate metal layer, and the top surface of the contact is interposed between the top surface of the metal bit line and the top surface of the gate metal layer.

In an embodiment of the present disclosure, the thickness of the covering layer is between 3 nm and 5 nm.

According to an embodiment of the present disclosure, a method for forming a semiconductor structure is provided, including forming a plurality of metal bit lines on a substrate, forming a plurality of bit line spacers on sidewalls of each metal bit line, and forming a first sacrificial layer. Etching the first sacrificial layer on the sidewall of each bit line spacer to form a second sacrificial layer with a lower width greater than the upper width, forming contacts contacting the second sacrificial layer between adjacent metal bit lines, removing A second sacrificial layer to form a gap between the bitline spacer and the contact, and deposit a capping layer covering the metal bitline, bitline spacer, and contact to form an air gap in the gap, wherein the capping The layer includes a first portion covering a sidewall of the bitline spacer, a second portion covering a sidewall of the contact, and a third portion covering a top surface of the contact, the first portion and the third portion contacting each other.

In an embodiment of the present disclosure, the width of the lower portion of the second sacrificial layer is between 10 nm and 15 nm.

In an embodiment of the present disclosure, forming a contact between adjacent metal bit lines further includes forming a contact material layer covering the second sacrificial layer between adjacent metal bit lines, and etching the contact material layer to The contacts are formed such that the top surfaces of the contacts are lower than the top surfaces of the metal bit lines.

The following disclosure presents a number of different embodiments or examples in order to achieve the different features of the mentioned subject matter. Specific examples of components, values, operations, materials, configurations, etc. are described below to simplify the present disclosure. Of course, these are examples only, not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where the first feature and the second feature are formed in direct contact. An embodiment in which an additional feature is formed between such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to facilitate describing an element or feature as shown in the drawings. A relationship to another component or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present disclosure provides a semiconductor structure and a method of forming the same, wherein the semiconductor structure includes a capping layer covering metal bit lines, bit line spacers and contacts. Since the cover layer forms a structurally complete air gap between the bit line spacer and the contact, the parasitic capacitance between the metal bit line and the contact is effectively reduced, thereby increasing the stability of the device including the semiconductor structure.

FIG. 1 shows a flowchart of a method 1000 for forming a semiconductor structure according to some embodiments of the present disclosure. The method 1000 includes step 1002 , step 1004 , step 1006 , step 1008 , step 1010 , step 1012 , step 1014 and step 1016 . In some implementations, additional steps may be added before, during, and after method 1000 . In some other implementations, some steps of method 1000 described below may be replaced, reduced or moved.

2 to 9 are cross-sectional views of the semiconductor structure 10 at various stages of formation according to some embodiments of the present disclosure. The semiconductor structure 10 can be applied to an integrated circuit (integrated circuit, IC) or a part thereof, such as a logic circuit, a resistor, a capacitor, an inductor, a memory (such as a dynamic random access memory (Dynamic Random Access Memory, DRAM) ))Wait. It should be understood that some elements of the semiconductor structure 10 are not shown in FIGS. 2-9 to simplify the drawings, and that additional elements may be included in other embodiments of the semiconductor structure 10 .

Referring to FIG. 1 in conjunction with FIG. 2 , in step 1002 , metal bit lines 130 are formed on the substrate 100 of the semiconductor structure 10 , and a bit line spacer layer 140 covering the metal bit lines 130 is formed. Specifically, the bit line spacer 140 conformally covers the metal bit line 130 to isolate the sidewall of the metal bit line 130 from the outside world, so that the bit line spacer 140 can protect the metal bit line 130 in subsequent manufacturing processes. It is protected from damage, thereby increasing the reliability of the semiconductor structure 10 .

In some embodiments, the substrate 100 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (Semiconductor-On-Insulator, SOI) substrate, etc., wherein the insulator may be a buried oxide (Buried Oxide, BOX) layer, silicon oxide layer, etc. In some embodiments, the substrate 100 can be doped (eg, containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 100 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), alloy semiconductors or a combination thereof. The substrate 100 can also be formed of other materials, such as sapphire, indium tin oxide, and the like.

In some embodiments, the substrate 100 may include polysilicon bitlines 110 and polysilicon bitlines 120 for electrically connecting to other components of the semiconductor structure 10 to form a circuit of the semiconductor structure 10 . Specifically, the polysilicon bit line 110 and the polysilicon bit line 120 can be disposed under the metal bit line 130 for transmitting current to the metal bit line 130 . In some embodiments, the polysilicon bitline 110 can be disposed in the substrate 100 not covered by the metal bitline 130, so as to be used as a wire to transmit current to an element above it (such as the contact 162 shown in FIG. 7 ). .

In some embodiments, the metal bit lines 130 may extend on the substrate 100 along a first direction D1 (as shown in FIG. 2 , a direction perpendicular to the paper). In some embodiments, the metal bit line 130 may include a stack of multiple material layers, so as to have the function of reading and writing electronic signals. As shown in FIG. 2 , the metal bit line 130 may include a stack formed of a first conductive layer 134 and a second conductive layer 136 to serve as a gate structure of the metal bit line 130 . In some embodiments, the first conductive layer 134 and the second conductive layer 136 may include different wire materials. For example, the first conductive layer 134 may include doped polysilicon, and the second conductive layer 136 may include metal or metal nitride. In the above example, the first conductive layer 134 may be called a gate polysilicon layer, and the second conductive layer 136 may be called a gate metal layer. In other examples, the first conductive layer 134 may include metal or metal nitride, and the second conductive layer 136 may include polysilicon. In some other embodiments, the metal bit line 130 may include an additional conductive layer, for example, a metal silicide layer may be included between the first conductive layer 134 and the second conductive layer 136 .

In some embodiments, the metal bitline 130 may further include a dielectric layer 132 isolating the first conductive layer 134 from an underlying structure, such as the polysilicon bitline 110 or the polysilicon bitline 120 . For example, the material forming the dielectric layer 132 may include silicon oxide, silicon nitride, a high-k dielectric material, other suitable materials, or a combination thereof. In some embodiments, the metal bitline 130 may further have a dielectric layer 138 formed on the second conductive layer 136 to isolate the second conductive layer 136 from other features subsequently formed on the metal bitline 130 . For example, the material forming the dielectric layer 138 may include silicon oxide, silicon nitride, other dielectric materials or combinations thereof.

In some embodiments, the bit line spacer layer 140 covering the metal bit line 130 may have an appropriate thickness to protect the structure of the metal bit line 130 . For example, the bit line spacer layer 140 can have a thickness between 1 nm and 2 nm, and uniformly cover the dielectric layer 132 , the first conductive layer 134 , the second conductive layer 136 and the sidewalls of the dielectric layer 138 and the dielectric layer 138 of the top surface. In some embodiments, the bit line spacer 140 may further extend into the substrate 100 such that the bit line spacer 140 contacts the polysilicon bit lines 120 , thereby separating multiple regions of the semiconductor structure 10 . In some embodiments, the material forming the bit line spacer layer 140 may be a suitable dielectric material, such as silicon nitride, a low-k dielectric material, or a combination thereof. For example, the bit line spacer layer 140 can be a dielectric material with a single-layer structure, a double-layer structure or a multi-layer structure, and the multi-layer materials can respectively include different compositions. In some embodiments, the bit line spacer layer 140 can be formed using a suitable deposition process, such as chemical vapor deposition (chemical vapor deposition, CVD), plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD), atomic layer Deposition (atomic layer deposition, ALD) and so on.

Referring to FIG. 1 in combination with FIG. 3 , in step 1004 , part of the bit line spacing layer 140 on the substrate 100 and the metal bit line 130 is removed. Specifically, the top surface of the substrate 100 and the bit line spacer 140 on the top surface of the metal bit lines 130 are selectively removed, and the bit line spacer 140 on the sidewalls of the metal bit lines 130 remains. Since the uppermost dielectric layer (such as the dielectric layer 138 shown in FIG. 2 ) in the metal bitline 130 can protect other material layers below it, the top surface of the metal bitline 130 can be removed. The bit line spacer layer 140 , thereby reducing the thickness of the semiconductor structure 10 . In some embodiments, removing a portion of the bitline spacer layer 140 may include forming a photoresist over the substrate 100 and the metal bitlines 130 using a patterning process, etching the exposed portions of the substrate 100 and the metal bitlines 130 exposed by the photoresist. bit line spacer 140 , and retain the bit line spacer 140 on the sidewall of the metal bit line 130 .

Referring to FIG. 1 in conjunction with FIG. 4 , in step 1006 , a first sacrificial layer 150 is formed on the sidewall of the bit line spacer layer 140 . Specifically, the first sacrificial layer 150 may be formed using steps similar to the steps of forming the bit line spacer 140 . For example, after forming a sacrificial material layer conformally covering the metal bit lines 130, the bit line spacing layer 140, and the substrate 100, selectively removing the horizontal portion of the sacrificial material layer on the substrate 100 and the metal bit lines 130, thereby forming The first sacrificial layer 150 . The first sacrificial layer 150 is formed outside the sidewall of the bit line spacer 140, so that when other elements (such as contacts) are subsequently formed between adjacent metal bit lines 130, the metal bit lines 130 and other elements can be retained. A space forming an air gap (such as the air gap 190 shown in FIG. 9 ) therebetween.

In some embodiments, the first sacrificial layer 150 may have a width W1 in a second direction D2 different from the first direction D1. In some embodiments, the first sacrificial layer 150 may have an appropriate width W1 such that the first sacrificial layer 150 may reserve enough space for the subsequently formed air gap. For example, the width W1 of the first sacrificial layer 150 may be between 10 nm and 15 nm. In some embodiments, the material forming the first sacrificial layer 150 may include a dielectric material different from the bit line spacer layer 140, so that the first sacrificial layer 150 undergoes a selective etching process in a subsequent step (as shown in FIG. As shown), the bit line spacer layer 140 is not affected by it. For example, if the bit line spacer layer 140 is silicon nitride, the first sacrificial layer 150 can be silicon oxide, for example.

In some embodiments, the sacrificial material layer of the first sacrificial layer 150 can be formed using a suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, and the like. In some embodiments, selectively removing horizontal portions of the sacrificial material layer on the substrate 100 and the metal bitlines 130 may include forming a photoresist over the substrate 100 and the metal bitlines 130 using a patterning process, etching the substrate 100 and The sacrificial material layer on the metal bitline 130 is exposed by the photoresist to retain the sacrificial material layer on the sidewall of the metal bitline 130 such that the top surface of the first sacrificial layer 150 is coplanar with the top surface of the metal bitline 130 .

Referring to FIG. 1 in conjunction with FIG. 5 , in step 1008 , the first sacrificial layer 150 is etched to form the second sacrificial layer 152 , so that the width W1 of the lower portion of the second sacrificial layer 152 is greater than the width W2 of the upper portion. Herein, "upper" is used to refer to a position higher than the work function region (eg, the gate metal layer) of the metal bit line 130 . In contrast, “lower portion” is used to refer to a position lower than the work function region of the metal bit line 130 . Specifically, the upper portion of the first sacrificial layer 150 may be etched so that the upper portion of the second sacrificial layer 152 has a structure whose width tapers upward. Therefore, the lower part of the second sacrificial layer 152 (for example, a position close to the bottom surface of the second sacrificial layer 152) has a width W1 in the second direction D2, so as to reserve enough space for the subsequently formed air gap; The upper portion of the second sacrificial layer 152 has a width W2 smaller than the width W1 in the second direction D2.

In some embodiments, the upper portion of the second sacrificial layer 152 may have a continuous and smooth curved surface through etching, so as to form a tapered structure leaning against the bit line spacer 140 . In some embodiments where the second conductive layer 136 is a gate metal layer, the width of the second sacrificial layer 152 may start to taper above the top surface of the second conductive layer 136, that is, the width of the second sacrificial layer 152 The position of the width W2 is higher than the top surface of the second conductive layer 136 .

Referring to FIG. 1 in conjunction with FIG. 6 , in step 1010 , a contact material layer 160 is formed between adjacent metal bit lines 130 , wherein the contact material layer 160 covers the second sacrificial layer 152 . Specifically, a suitable deposition process (such as chemical vapor deposition) may be used to form the contact material layer 160 , which fills the gap between adjacent metal bit lines 130 and covers the second sacrificial layer 152 . Next, a planarization process may be performed so that the top surface of the contact material layer 160 and the top surface of the metal bit line 130 are coplanar. As shown in FIG. 6, since the second sacrificial layer 152 has a lower width W1 greater than an upper width W2 in the second direction D2, the contact material layer 160 has an upper width W4 greater than a lower width in the second direction D2. W3. It should be understood that although FIG. 6 depicts a combination of three metal bit lines 130 and two contact material layers 160, the semiconductor structure 10 may include other numbers of metal bit lines 130 and contact material layers 160, for example may include Two metal bit lines 130 and three contact material layers 160 are alternately arranged on the substrate 100 .

In some embodiments, the contact material layer 160 may extend into the substrate 100, or further extend into the polysilicon bitline 120, thereby forming a vertically oriented conductive path so that the semiconductor structure 10 may be connected to conductive features on or below it. . In some embodiments, the material forming the contact material layer 160 may include conductive materials, such as doped polysilicon, metal, metal silicide, metal nitride, suitable materials or combinations thereof. In some embodiments, the contact material layer 160 may further include a barrier layer (not shown) formed on the side surface and the bottom surface of the contact material layer 160 so that the contact material layer 160 contacts the substrate 100 through the barrier layer.

Referring to FIG. 1 in conjunction with FIG. 7 , in step 1012 , the contact material layer 160 is etched to form contacts 162 . Specifically, the contact material layer 160 is selectively etched such that the top surface of the contact material layer 160 is lower than the top surface of the metal bit line 130 , thereby forming the contact 162 . In more detail, the etching process of the contact material layer 160 may stop at the upper portion of the second sacrificial layer 152 such that the top surface of the contact 162 contacts the upper portion of the second sacrificial layer 152 having a tapered width. In other words, the contact member 162 is similar to the contact material layer 160 , and has an upper width greater than a lower width in the second direction D2 .

In some embodiments, the top surface of the contact 162 may have a width W6 in the second direction D2, and the portion of the contact 162 that is coplanar with the top surface of the substrate 100 may have a width W5 in the second direction D2. As shown in FIG. 7 , the difference between the width W5 and the width W6 of the contact element 162 depends on the tapered structure of the second sacrificial layer 152 . For example, the difference between the width W5 and the width W6 of the contact 162 may be between 5 nm and 20 nm. In some embodiments where the second conductive layer 136 is a gate metal layer, the top surface of the contact 162 contacts the upper portion of the second sacrificial layer 152 and the upper portion of the second sacrificial layer 152 may be higher than the top surface of the second conductive layer 136 , so the top surface of the contact 162 may be between the top surface of the metal bit line 130 and the top surface of the second conductive layer 136 . In some embodiments where the first conductive layer 134 is a gate metal layer, the top surface of the contact 162 may be between the top surface of the metal bit line 130 and the top surface of the first conductive layer 134 and may be lower than the top surface of the second conductive layer 136 .

Referring to FIG. 1 in conjunction with FIG. 8 , in step 1014 , the second sacrificial layer 152 between the metal bit line 130 and the contact 162 is removed to form a gap 170 . Specifically, the second sacrificial layer 152 is removed using a selective etching process (eg, wet etching), thereby forming a gap 170 between the bit line spacer 140 and the contact 162 . As shown in FIG. 8, the gap 170 formed by removing the second sacrificial layer 152 has a profile similar to that of the second sacrificial layer 152, so that the distance between the upper portion of the contact 162 and the bit line spacer 140 is smaller than that of the contact. The distance between the lower part of 162 and the bit line spacer layer 140 . Since the second sacrificial layer 152 has a sufficient width W1 (as shown in FIG. 5 ), the selective etching process can completely remove the second sacrificial layer 152 . Therefore, in the semiconductor structure 10 with multiple second sacrificial layers 152 , removing the second sacrificial layers 152 can form multiple gaps 170 with the same depth, so that air gaps with uniform depth and complete structure can be formed in subsequent processes.

Referring to FIG. 1 in conjunction with FIG. 9 , in step 1016 , a capping layer 180 covering metal bitlines 130 , bitline spacers 140 and contacts 162 is deposited to form air gaps 190 . Specifically, capping layer 180 may be conformally formed over the structure shown in FIG. 8 such that capping layer 180 forms an air gap 190 in gap 170 between bit line spacer 140 and contact 162 . Air gap 190 formed in gap 170 has a profile similar to gap 170 such that a top portion of air gap 190 slopes toward bit line spacer 140 . The air gap 190 can reduce the parasitic capacitance between the metal bit line 130 and the contact 162 , thereby increasing the reliability of the semiconductor structure 10 .

As shown in FIG. 9, cover layer 180 includes a first portion 182 covering the sidewalls of bit line spacer 140, a second portion 184 covering the sidewalls of contacts 162, and a third portion 186 covering the top surface of contacts 162. . When the cover layer 180 is conformally formed on the bit line spacer 140 and the contact 162, since the distance between the upper part of the contact 162 and the bit line spacer 140 is smaller than the distance between the lower part of the contact 162 and the bit line spacer 140, the third portion 186 and the first portion 182 are in contact with each other, while the second portion 184 and the first portion 182 remain separated. In other words, the covering layer 180 forms the air gap 190 in the gap 170 between the first portion 182 and the second portion 184 through self-sealing. It is worth noting that since the cover layer 180 forms the air gap 190 through self-encapsulation, it is possible to avoid using an additional material layer for encapsulation and causing material to infiltrate into the air gap 190, thereby maintaining the structural integrity of the air gap 190 and effectively reducing the Parasitic capacitance of the semiconductor structure 10 .

In some embodiments, the cover layer 180 may have an appropriate thickness such that the first portion 182 and the second portion 184 of the cover layer 180 remain separated while the first portion 182 and the third portion 186 of the cover layer 180 are in contact with each other. For example, the thickness of the covering layer 180 may be between 3 nm and 5 nm. However, it should be understood that the thickness of the capping layer 180 may not be within the above range according to the width of the gap 170 and the design of the semiconductor structure 10 . In some embodiments, the material forming the capping layer 180 may include silicon nitride, silicon oxide, silicon oxynitride, metal, metal nitride or other suitable materials. In some embodiments, the cover layer 180 and the bit line spacer 140 may include the same material to increase the adhesion between the cover layer 180 and the bit line spacer 140 . In some embodiments, the capping layer 180 can be formed using a suitable deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, and the like.

In some embodiments, the bottom width of the air gap 190 may be greater than the top width. For example, the bottom width of the air gap 190 in the second direction D2 may be between 1 nm and 10 nm. In some embodiments, the air gap 190 need not be filled with air, it may be filled with other types of gas, or it may be a vacuum.

According to the above embodiments of the present disclosure, the present disclosure provides a semiconductor structure and a method for forming the same. In the process of forming the semiconductor structure, the air gap space in the semiconductor structure is reserved by the sacrificial layer with sufficient width, so that an air gap with uniform depth and complete structure can be formed between the metal bit line and the contact. In addition, the capping layer in the semiconductor structure forms an air gap through self-encapsulation, further maintaining the structural integrity of the air gap. Therefore, the air gap of the semiconductor structure effectively reduces the parasitic capacitance between the metal bit line and the contact, thereby increasing the stability of the device including the semiconductor structure.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of this disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

10:Semiconductor structure 100: Substrate 110,120: polysilicon bit lines 130: metal bit line 132: dielectric layer 134: the first conductive layer 136: the second conductive layer 138: dielectric layer 140: bit line spacing layer 150: the first sacrificial layer 152: The second sacrificial layer 160: contact material layer 162: contact piece 170: Gap 180: Overlay 182: Part 1 184: Part Two 186: Part Three 190: air gap 1000: method 1002, 1004, 1006, 1008, 1010, 1012, 1014, 1016: steps D1: the first direction D2: Second direction W1, W2, W3, W4, W5, W6: Width

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. 2-9 illustrate cross-sectional views of various intermediate stages in the formation of a semiconductor device according to an embodiment of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

10:Semiconductor structure

100: Substrate

110,120: polysilicon bit lines

130: metal bit line

140: bit line spacing layer

162: contact piece

180: Overlay

182: Part 1

184: Part Two

186: Part Three

190: air gap

D1: the first direction

D2: Second direction

Claims (9)

A semiconductor structure, comprising: a substrate; a metal bit line on the substrate; a bit line spacer layer on the sidewall of the metal bit line; a contact adjacent to the metal bit line, wherein the An upper width of the contact is greater than a lower width; a cover layer covers the metal bit line, the bit line spacer and the contact, wherein the cover layer includes a first sidewall covering the bit line spacer a portion, a second portion covering the sidewall of the contact and a third portion covering a top surface of the contact; and an air gap between the first portion and the second portion of the cover, wherein A top portion of the air gap is sloped toward the bit line spacer, and the first portion and the third portion of the capping layer contact each other above the air gap. The semiconductor structure of claim 1, wherein a bottom width of the air gap is greater than a top width. The semiconductor structure according to claim 2, wherein the width of the bottom of the air gap is between 1 nm and 10 nm. The semiconductor structure as claimed in claim 1, wherein the top surface of the contact has a first width, the portion of the contact coplanar with the top surface of the substrate has a second width, the first width and the first width Erkuan The difference in degree is between 5nm and 20nm. The semiconductor structure of claim 1, wherein the metal bit line includes a gate metal layer, the top surface of the contact is between the top surface of the metal bit line and the top surface of the gate metal layer between. The semiconductor structure according to claim 1, wherein the thickness of the capping layer is between 3nm and 5nm. A method of forming a semiconductor structure, comprising: forming a plurality of metal bit lines on a substrate; forming a plurality of bit line spacers on the sidewalls of each of the metal bit lines; forming a first sacrificial layer on each of the metal bit lines on the sidewalls of the bit line spacers; etch the first sacrificial layer to form a second sacrificial layer, wherein the lower width of the second sacrificial layer is greater than an upper width; form a contact between the adjacent metals between the bit lines, wherein the contact contacts the second sacrificial layer; removing the second sacrificial layer to form a gap between each of the bit line spacers and the contact; metal bit lines, the bit line spacers and a cover layer of the contact to form an air gap in the gap, wherein the cover layer includes a first portion covering sidewalls of the bit line spacers, Covering a second portion of the sidewall of the contact and covering a top surface of the contact A third part, the first part and the third part are in contact with each other. The method according to claim 7, wherein the width of the lower portion of the second sacrificial layer is between 10 nm and 15 nm. The method as claimed in claim 7, wherein forming the contact between the adjacent metal bit lines further comprises: forming a contact material layer between the adjacent metal bit lines, wherein the contact a material layer covering the second sacrificial layer; and etching the contact material layer to form the contact such that the top surface of the contact is lower than a top surface of the metal bit lines.

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