TWI847378B - Semiconductor structure and mounting method of the same - Google Patents

Abstract

A semiconductor structure includes a substrate, multiple first bit line structures, multiple second bit line structures, a first contact, and a second contact. The substrate includes a device region and a dummy region. The first bit line structures are located on the substrate and in the device region. The second bit line structures are located on the substrate and in the dummy region. The first contact is located on the substrate and in the device region. The first contact is located between the first bit line contact structures. The second contact is located on the substrate and in the dummy region. The second contact is located between the second bit line contact structures.

Description

Semiconductor structure and method for manufacturing the same

The present disclosure relates to a semiconductor structure and a manufacturing method thereof.

As the minimum feature width or critical dimension (CD) within a semiconductor device continues to shrink, the component density of the semiconductor device is increased and the size of the device is reduced. However, as the spacing between closely arranged components decreases, the chance of short circuits in the conductive lines between components may also increase.

In view of this, how to provide a display device that can solve the above problems is still a goal of research and development in this field.

One technical aspect of the present disclosure is a semiconductor structure.

In one embodiment of the present disclosure, a semiconductor structure includes a substrate, a plurality of first bit line structures, a plurality of second bit line structures, a first contact, and a second contact. The substrate includes a component region and a dummy region. The first bit line structure is located on the substrate and in the component region. The second bit line structure is located on the substrate and in the dummy region. The first contact is located on the substrate and in the component region. The first contact is located between the first bit line structures. The second contact is located on the substrate and in the dummy region. The second contact is located between the second bit line structures.

In one embodiment of the present disclosure, the first contact extends into the substrate.

In one embodiment of the present disclosure, the second contact does not extend into the substrate.

In one embodiment of the present disclosure, the semiconductor structure further includes a bit line contact located in the substrate. The bit line contact is located below one of the first bit line structures and is electrically connected to the first bit line structure.

In one embodiment of the present disclosure, the semiconductor structure further includes a bit line spacer layer located on the sidewalls of each of the first bit line structures, the sidewalls of each of the second bit line structures, and the bottom of the second contact.

One technical aspect of the present disclosure is a method for manufacturing a semiconductor structure.

In one embodiment of the present disclosure, a method for manufacturing a semiconductor structure includes forming a plurality of first bit line structures in a device region of a substrate; forming a plurality of second bit line structures in a dummy region of the substrate; forming a plurality of second contacts between the first bit line structures in the device region and between the second bit line structures in the dummy region; and removing the second contacts in the device region.

In one embodiment of the present disclosure, after forming the second contact, an oxide layer is formed over the first bit line structure, the second bit line structure and the second contact.

In one embodiment of the present disclosure, forming the oxide layer is performed by a plasma process.

In one embodiment of the present disclosure, after forming the oxide layer, a photoresist layer is formed on the oxide layer in the dummy region.

In one embodiment of the present disclosure, removing the second contact in the device region further includes etching the second contact in the device region after forming a photoresist layer in the dummy region, and retaining the second contact in the dummy region.

In one embodiment of the present disclosure, removing the second contact in the device region includes performing a wet etching process on the device region.

In one embodiment of the present disclosure, the method for manufacturing a semiconductor structure further includes forming a bit line spacer layer to cover the first bit line structure and the second bit line structure before forming the second contact, so that the bit line spacer layer is located on the sidewalls of each of the first bit line structures, the sidewalls of each of the second bit line structures, and the bottom of each of the second contacts.

In one embodiment of the present disclosure, after removing the second contact in the device region, a portion of the bit line spacer layer located in the device region and extending along the horizontal direction is etched.

In one embodiment of the present disclosure, the method for manufacturing a semiconductor structure further includes forming a plurality of first contacts between the first bit line structures in the device region.

In one embodiment of the present disclosure, etching of the bit line spacer layer located in the device region and extending in the horizontal direction is performed by dry etching.

In the above embodiment, the second contact in the dummy area and the bit line spacer layer at the bottom together fill the space between the second bit line structures. In other words, the second contact is a dummy contact. In this way, no line for transmitting current is formed in the dummy area. The dummy area can be used to prevent the line in the active area from short-circuiting with the adjacent line. The oxide layer formed by the plasma process has good adhesion to the photoresist layer. In this way, in the subsequent process, the second contact in the dummy area can be protected from the etching process.

The following will disclose multiple embodiments of the present invention with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner. And for the sake of clarity, the thickness of the layers and regions in the drawings may be exaggerated, and the same element symbols represent the same elements in the description of the drawings.

FIG. 1 is a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. The semiconductor structure 100 includes a substrate 110, a first bit line structure 120, a second bit line structure 130, a first contact 140, and a second contact 150.

The semiconductor structure 100 may be applied to an integrated circuit (IC) or a part thereof, such as a logic circuit, a resistor, a capacitor, an inductor, a memory (such as a dynamic random access memory (DRAM)), etc. It should be understood that some elements of the semiconductor structure 100 are not shown in the figure, and additional elements may be included in other embodiments.

In some embodiments, the substrate 110 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, the semiconductor material of the substrate 110 may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide), an alloy semiconductor or a combination thereof. The substrate 110 may also be formed of other materials, such as sapphire, tin indium oxide, etc.

The substrate 110 has a plurality of active regions 112 and a plurality of isolation regions 114 separating the active regions 112. The substrate 110 may be doped with N-type or P-type dopants by an ion implantation process. In some embodiments, source and drain regions (not shown) may be formed by doping the active regions 112 of the substrate 110 with N-type or P-type dopants. The material of the isolation region 114 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The substrate 110 includes a device region 1102 and a dummy region 1104. The first bit line structure 120 is located on the substrate 110 and in the device region 1102. The second bit line structure 130 is located on the substrate 110 and in the dummy region 1104. The device region 1102 and the dummy region 1104 are divided according to the horizontal direction of the substrate 110, such as the first direction D1. A portion of the active region 112 is located in the device region 1102, and a portion is located in the dummy region 1104. Specifically, the dummy region 1104 is equivalent to the edge portion of the active region 112 and is adjacent to other active regions (not shown). The device region 1102 is equivalent to the inside of the active region 112.

The first bit line structure 120 and the second bit line structure 130 protrude from the substrate 110 along a second direction D2 perpendicular to the substrate 110. The first bit line structure 120 and the second bit line structure 130 extend along a direction parallel to the substrate 110, such as another horizontal direction different from the first direction D1.

The first bit line structure 120 and the second bit line structure 130 may be formed by stacking multiple layers of materials. For example, the first bit line structure 120 includes a first conductive layer 124, a second conductive layer 126, and an insulating cap layer 128 stacked along the second direction D2. The first conductive layer 124 and the second conductive layer 126 have different materials. The first conductive layer 124 and the second conductive layer 126 may include polysilicon, semiconductor materials, doped semiconductor materials, metals, metal nitrides, metal silicides, other suitable conductive materials, or combinations thereof.

In other embodiments, the first conductive layer 124 and the second conductive layer 126 of the first bit line structure 120 may further include other conductive layers, such as a third conductive layer 125. The material of the insulating cap layer 128 may include silicon oxide, silicon nitride, other dielectric materials, or a combination thereof.

The second bit line structure 130 also includes a first conductive layer 134 , a third conductive layer 135 , a second conductive layer 136 , and an insulating cap layer 138 similar to the first bit line structure 120 .

The first bit line structure 120 and the second bit line structure 130 may further include isolation layers 129 and 139. The isolation layers 129 and 139 are located on the substrate 110 to isolate the first conductive layers 124 and 134 from the structures thereunder.

The first contact 140 is located on the substrate 110 and in the device region 1102. The first contact 140 is located between the first bit line structures 120. The first contact 140 extends into the substrate 110. The second contact 150 is located on the substrate 110 and in the dummy region 1104. The second contact 150 is located between the second bit line structures 130. The second contact 150 does not extend into the substrate 110.

The semiconductor structure 100 further includes a bit line contact 160. The bit line contact 160 is located in the substrate 110. The bit line contact 160 contacts the active region 112 and can be electrically connected to the active region 112. The bit line contact 160 is located below one of the first bit line structures 120 and is configured to be electrically connected to the first bit line structure 120. The bit line contact 160 can also be located below one of the second bit line structures 130. The material of the bit line contact 160 is a conductive material, such as polysilicon.

The semiconductor structure 100 further includes a bit line spacer layer 170. The bit line spacer layer 170 is located on the sidewall 122 of the first bit line structure 120, the sidewall 132 of the second bit line structure 130, and the bottom 152 of the second contact 150. The bit line spacer layer 170 can prevent the first bit line structure 120 and the second bit line structure 130 from being damaged in subsequent manufacturing processes, thereby improving the reliability of the semiconductor structure 100.

The second contact 150 and the bit line spacer layer 170 located at the bottom 152 together fill the space between the second bit line structures 130. In other words, the second contact 150 is a dummy contact. As a result, no line for transmitting current is formed in the dummy area 1104. In other words, the dummy area 1104 is used to prevent the line in the active area 112 from short-circuiting with the adjacent line.

It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, and are described first. In the following description, a method for manufacturing the semiconductor structure 100 will be described.

FIG. 2 to FIG. 7 are cross-sectional views of intermediate steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Referring to FIG. 2, the method for manufacturing the semiconductor structure 100 begins by forming a first bit line structure 120 and a second bit line structure 130 in a device region 1102 and a dummy region 1104, respectively, and forming a bit line spacer layer 170 to surround the first bit line structure 120 and the second bit line structure 130.

Specifically, the bit line spacer layer 170 in this step conformally covers the first bit line structure 120 and the second bit line structure 130. Then, the second contact 150 is formed between the first bit line structure 120 and the second bit line structure 130. Subsequently, a planarization process may be performed to make the top surfaces of the first bit line structure 120, the second bit line structure 130, the second contact 150, and the bit line spacer layer 170 flush.

Refer to FIG. 3 . After forming the second contact 150 , a plasma process P is used to form an oxide layer 180 on the first bit line structure 120 , the second bit line structure 130 , and the second contact 150 . In this step, a dense oxide layer is formed by high temperature oxygen plasma or hydrogen-nitrogen mixture plasma. The oxide layer 180 is formed on the top surface 120T of the first bit line structure 120 , the top surface 130T of the second bit line structure 130 , and the top surface 150T of the second contact 150 .

Refer to FIG. 4. After the oxide layer 180 is formed by plasma, a photoresist layer 190 is formed on the oxide layer 180 in the dummy region 1104. The oxide layer 180 formed by the plasma process P has good adhesion to the photoresist layer 190. In this way, in the subsequent process, the second contact 150 in the dummy region 1104 can be protected from being affected by the etching process.

Refer to FIG. 5. After forming the photoresist layer 190 in the dummy region 1104, the second contact 150 in the device region 1102 is removed. Specifically, the second contact 150 in the device region 1102 is removed by performing a wet etching process on the device region 1102 and the second contact 150 in the dummy region 1104, while retaining the second contact 150 in the dummy region 1104 through the photoresist layer 190. Since the oxide layer 180 and the photoresist layer 190 have good adhesion, the wet etching process will not affect the second contact 150 in the dummy region 1104.

Generally speaking, the top surface 150T of the second contact 150 and the top surface 130T of the second bit line structure 130 are naturally oxidized to generate an oxide layer. However, such a natural oxide layer has poor adhesion to the photoresist layer 190, and thus the second contact 150 in the dummy region 1104 cannot be prevented from being etched.

Refer to FIG. 6. After removing the second contact 150 in the device region 1102, the photoresist layer 190 is removed. In this step, the oxide layer 180 may also remain on the second bit line structure 130 and the second contact 150 in the dummy region 1104. In subsequent processes, the oxide layer 180 in the dummy region 1104 may also provide a protection function.

Refer to FIG. 7. After removing the photoresist layer 190, the bit line spacer layer 170 originally located at the bottom 152 (see FIG. 2) of the second contact 150 in the device region 1102 is etched. In other words, a portion of the bit line spacer layer 170 extending along the horizontal direction (e.g., the first direction D1) in the device region 1102 is etched. In this step, the oxide layer 180 in the dummy region 1104 may also be removed. Etching the bit line spacer layer 170 in the device region 1102 is performed by a dry etching process.

In some embodiments, the dry etching process in this step may also etch a portion of the second contact 150 in the dummy area 1104. However, since the complete second contact 150 is retained in the previous step, in the subsequent step, even if a portion of the second contact 150 is partially etched, it will not affect the bit line spacer layer 170 at the bottom 152 of the second contact 150, so it can still be ensured that the line in the dummy area 1104 is not conductive.

Returning to FIG. 1 , after the aforementioned steps, a first contact 140 is formed between the first bit line structures 120 in the device region 1102 . The first contact 140 passes through the bit line spacer layer 170 and extends into the substrate 110 .

In summary, the second contact in the dummy area and the bit line spacer layer at the bottom together fill the space between the second bit line structures. In other words, the second contact is a dummy contact. In this way, no line for transmitting current is formed in the dummy area. The dummy area can be used to prevent the line in the active area from short-circuiting with the adjacent line. The oxide layer formed by the plasma process has good adhesion to the photoresist layer. In this way, in the subsequent process, the second contact in the dummy area can be protected from the etching process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100: semiconductor structure 110: substrate 1102: device region 1104: dummy region 112: active region 114: isolation region 120: first bit line structure 120T: top surface 122: side wall 124,134: first conductive layer 125,135: third conductive layer 126,136: second conductive layer 128,138: insulating cover layer 129,139: isolation layer 130: second bit line structure 130T: top surface 132: side wall 140: first contact 150: second contact 150T: Top surface 152: Bottom surface 160: Bit line contact 170: Bit line spacer layer 180: Oxide layer 190: Photoresist layer D1: First direction D2: Second direction P: Plasma process

Figure 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. Figures 2 to 7 are cross-sectional views of intermediate steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

100: semiconductor structure 110: substrate 1102: device area 1104: dummy area 112: active area 114: isolation area 120: first bit line structure 122: sidewall 124,134: first conductive layer 125,135: third conductive layer 126,136: second conductive layer 128,138: insulating cover layer 129,139: isolation layer 130: second bit line structure 132: sidewall 140: first contact 150: second contact 152: bottom 160: bit line contact 170: Bit line spacing layer D1: First direction D2: Second direction

Claims (15)

A semiconductor structure includes: a substrate including a device region and a dummy region; a plurality of first bit line structures located on the substrate and in the device region; a plurality of second bit line structures located on the substrate and in the dummy region; a first contact located on the substrate and in the device region, wherein the first contact is located between the first bit line structures; a second contact located on the substrate and in the dummy region, wherein the second contact is located between the second bit line structures; and an inter-bit line spacer located at a bottom of the second contact. A semiconductor structure as described in claim 1, wherein the first contact extends into the substrate. A semiconductor structure as described in claim 1, wherein the second contact does not extend into the substrate. The semiconductor structure as described in claim 1 further comprises: a bit line contact located in the substrate, wherein the bit line contact is located below one of the first bit line structures and electrically connects the first bit line structures. A semiconductor structure as described in claim 1, wherein the bit line spacer layer is located on a side wall of each of the first bit line structures and a side wall of each of the second bit line structures. A method for manufacturing a semiconductor structure includes: forming a plurality of first bit line structures in a component region of a substrate; forming a plurality of second bit line structures in a dummy region of the substrate; forming a plurality of second contacts between the first bit line structures in the component region and between the second bit line structures in the dummy region; removing the second contacts in the component region; and forming a bit line spacer layer between the second contacts to cover the first bit line structures and the second bit line structures, so that the bit line spacer layer is located at a bottom of each of the second contacts. The method for manufacturing a semiconductor structure as described in claim 6 further comprises: after forming the second contacts, forming an oxide layer on the first bit line structures, the second bit line structures and the second contacts. A method for manufacturing a semiconductor structure as described in claim 7, wherein the oxide layer is formed by a plasma process. The method for manufacturing a semiconductor structure as described in claim 7, further comprising: after forming the oxide layer, forming a photoresist layer on the oxide layer in the dummy region. The method for manufacturing a semiconductor structure as described in claim 9, wherein removing the second contacts in the device region further comprises: after forming the photoresist layer in the dummy region, etching the second contacts in the device region and retaining the second contacts in the dummy region. A method for manufacturing a semiconductor structure as described in claim 6, wherein removing the second contacts in the device region includes performing a wet etching process on the device region. A method for manufacturing a semiconductor structure as described in claim 6, wherein forming the bit line spacer layer further includes positioning the bit line spacer layer on a side wall of each of the first bit line structures and a side wall of each of the second bit line structures. The method for manufacturing a semiconductor structure as described in claim 6 further comprises: after removing the second contacts in the device region, etching a portion of the bit line spacer layer located in the device region and extending along a horizontal direction. The method for manufacturing a semiconductor structure as described in claim 13 further includes: forming a plurality of first contacts between the first bit line structures in the device region. A method for manufacturing a semiconductor structure as described in claim 13, wherein etching the bit line spacer layer located in the device region and extending in the horizontal direction is performed by dry etching.

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